Claims
- 1. A method of producing a SiGe-on-insulator substrate material comprising the steps of:
forming a Ge-containing layer on a surface of a first single crystal Si layer, said first single crystal Si layer is present atop a barrier layer that is resistant to Ge diffusion; and heating said layers to a temperature at or near the melting point of a selected SiGe alloy which causes a substantial reduction in strained relaxation defects while permitting interdiffusion of Ge throughout said first single crystal Si layer and said Ge-containing layer thereby forming a low-defect, substantially relaxed, single crystal SiGe layer atop said barrier layer, said temperature being at or above that which limits generation of stacking fault defects.
- 2. The method of claim 1 wherein said first single crystal Si layer and said barrier layer are components of a silicon-on-insulator (SOI) substrate.
- 3. The method of claim 1 wherein said first single crystal Si layer and said barrier layer are components of a non-SOI substrate.
- 4. The method of claim 1 wherein said barrier layer is a patterned barrier layer.
- 5. The method of claim 1 wherein said barrier layer is an unpatterned barrier layer.
- 6. The method of claim 1 wherein said barrier layer comprises crystalline or non-crystalline oxides, or crystalline or non-crystalline nitrides.
- 7. The method of claim 1 wherein said barrier layer is a buried oxide region.
- 8. The method of claim 1 wherein said Ge-containing layer is a SiGe alloy or pure Ge.
- 9. The method of claim 8 wherein said Ge-containing layer is a SiGe alloy comprising up to 99.99 atomic percent Ge.
- 10. The method of claim 9 wherein said SiGe layer comprises from about 10 to about 35 atomic percent Ge.
- 11. The method of claim 1 wherein said Ge-containing layer is formed by an epitaxial growth process selected from the group consisting of low-pressure chemical vapor deposition, atmospheric pressure chemical vapor deposition, ultra-high vacuum chemical vapor deposition, molecular beam epitaxy, and plasma-enhanced chemical vapor deposition.
- 12. The method of claim 1 further comprising forming a Si cap layer atop said Ge-containing layer prior to heating.
- 13. The method of claim 12 wherein said Si cap layer comprises epi-Si, a:Si, single or polycrystalline Si or any combination and multilayer thereof.
- 14. The method of claim 13 wherein said Si cap layer comprises epi-Si.
- 15. The method of claim 1 further comprising performing an implantation step prior to heating, said implantation step includes ions that are capable of forming defects that allow enhanced relaxation at or near an interface between the first single crystal Si layer and the barrier layer.
- 16. The method of claim 12 further comprising performing an implantation step prior to heating, said implantation step includes ions that are capable of forming defects that allow enhanced relaxation at or near an interface between the first single crystal Si layer and the barrier layer.
- 17. The method of claim 15 wherein said ions comprise hydrogen, deuterium, helium, oxygen, neon, or mixtures and isotopes thereof.
- 18. The method of claim 16 wherein said ions comprise hydrogen, deuterium, helium, oxygen, neon, or mixtures and isotopes thereof.
- 19. The method of claim 1 wherein a surface oxide layer forms during said heating step.
- 20. The method of claim 18 further comprising removing said surface oxide layer utilizing a wet chemical etch process.
- 21. The method of claim 1 wherein said forming and heating steps are repeated any number of times.
- 22. The method of claim 1 wherein said heating step is carried out in an oxidizing ambient which comprises at least one oxygen-containing gas.
- 23. The method of claim 1 wherein said heating step is between the range of 1230 to 1350° C.
- 24. The method of claim 22 wherein said at least one oxygen-containing gas comprises O2, NO, N2O, ozone, air or mixtures thereof.
- 25. The method of claim 22 further comprising an inert gas, said inert gas being employed to dilute said at least one oxygen-containing gas.
- 26. The method of claim 1 wherein said temperature is dependent upon the Ge fraction present in the SiGe layer.
- 27. The method of claim 1 wherein said substantially relaxed SiGe layer has a thickness of about 2000 nm or less.
- 28. The method of claim 1 wherein said substantially relaxed SiGe layer has a defect density of about 107 defects/cm2 or less.
- 29. The method of claim 1 wherein said substantially relaxed SiGe layer has a measured lattice relaxation of from about 1 to about 99%.
- 30. The method of claim 1 further comprising growing an additional SiGe layer atop said substantially relaxed SiGe layer.
- 31. The method of claim 30 further comprising forming a strained Si layer atop said additional SiGe layer.
- 32. The method of claim 1 further comprising forming a strained Si layer atop said substantially relaxed SiGe layer.
- 33. The method of claim 1 wherein said heating is performed by an oxidation process in which oxidation is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours.
- 34. The method of claim 33 further comprising performing an implantation step prior to heating, said implantation step includes ions that are capable of forming defects that allow enhanced relaxation at or near an interface between the first single crystal Si layer and the barrier layer.
- 35. The method of claim 34 wherein said ions comprise hydrogen, deuterium, helium, oxygen, flourine, neon, or mixtures and isotopes thereof.
- 36. A method of forming a SiGe-on-insulator substrate material comprising the steps of:
forming a Ge-containing layer on a surface of a first single crystal Si layer, said first single crystal Si layer is present atop a barrier layer that is resistant to Ge diffusion; and heating said layers a temperature at or near the melting point of a selected SiGe alloy which causes a substantial reduction in strain relaxation-induced defects while permitting interdiffusion of Ge throughout said first single crystal Si layer and said Ge-containing layer thereby forming a low-defect, substantially relaxed, single crystal SiGe layer atop said barrier layer, said temperature being at or above that which limits generation of stacking fault defects, said heating including an oxidation process that is performed at a temperature from about 1230° C. to about 1325° C. for a time period of less than about 2 hours.
- 37. The method of claim 36 further comprising performing an implantation step prior to heating, said implantation step includes ions that are capable of forming defects that allow enhanced relaxation at or near an interface between the first single crystal Si layer and the barrier layer.
- 38. The method of claim 37 wherein said ions comprise hydrogen, deuterium, helium, oxygen, flourine, neon, or mixtures and isotopes thereof.
- 39. A substrate material comprising:
a Si-containing substrate; an insulating region that is resistant to Ge diffusion present atop said Si-containing substrate; and a substantially relaxed SiGe layer present atop said insulating region, wherein said substantially relaxed SiGe layer has a thickness of about 2000 nm or less and a defect density of about 107 defects/cm2 or less.
- 40. The substrate material of claim 39 wherein said insulating region is patterned.
- 41. The substrate material of claim 39 wherein said insulating region is unpatterned.
- 42. The substrate material of claim 39 wherein said insulating region comprises crystalline or non-crystalline oxides, or crystalline or non-crystalline nitrides.
- 43. The substrate material of claim 39 wherein said insulating region is a buried oxide region.
- 44. The substrate material of claim 39 wherein said substantially relaxed SiGe layer has a measured lattice relaxation of from about 1 to about 99%.
- 45. The substrate material of claim 39 wherein said substantially relaxed SiGe layer has a surface that has a measured surface roughness of less than about 15 Å RMS.
- 46. The substrate material of claim 39 wherein said substantially relaxed SiGe layer has a stacking fault and/or microtwin defect density of less than about 1×105 defects/cm2.
- 47. The substrate material of claim 45 wherein said relaxed SiGe layer has surface pits that have a depth of less than 30 Å and a width of less than 300 nm.
- 48. A heterostructure comprising:
a Si-containing substrate; an insulating region that is resistant to Ge diffusion present atop the Si-containing substrate; a substantially relaxed SiGe layer present atop the insulating region, wherein the substantially relaxed SiGe layer has a thickness of about 2000 nm or less and a defect density of about 107 defects/cm2 or less; and a strained Si layer formed atop the substantially relaxed SiGe layer.
- 49. The heterostructure of claim 48 wherein said insulating region is patterned
- 50. The heterostructure of claim 48 wherein said insulating region is unpatterned.
- 51. The heterostructure of claim 48 wherein said insulating region comprises crystalline or non-crystalline oxides, or crystalline or non-crystalline nitrides.
- 52. The heterostructure of claim 48 wherein said insulating region barrier layer is a buried oxide region.
- 53. The heterostructure of claim 48 wherein said substantially relaxed SiGe layer has a measured lattice relaxation of from about 1 to about 99%.
- 54. The heterostructure of claim 48 wherein said strained Si layer comprises an epi-Si layer.
- 55. The heterostructure of claim 48 wherein alternating layers of relaxed SiGe and strained Si are located atop said strained Si layer.
- 56. The heterostructure of claim 48 wherein said strained Si layer is replaced with a lattice mismatched compound selected from the group consisting of GaAs and GaP.
- 57. The heterostructure of claim 48 wherein said substantially relaxed SiGe layer has a surface that has a measured surface roughness of less than about 15 Å RMS.
- 58. The substrate material of claim 57 wherein said relaxed SiGe layer has surface pits that have a depth of less than 30 Å and a width of less than 300 nm.
RELATED APPLICATIONS
[0001] This application is a continuation-in-part (CIP) application of U.S. patent application Ser. No. 10/448,948, filed May 30, 2003 and is related to co-pending and co-assigned U.S. patent application Ser. No. 10/055,138, filed Jan. 23, 2002, entitled “Method of Creating High-Quality Relaxed SiGe-On-Insulator for Strained Si CMOS Applications”, as well as co-pending, and co-assigned U.S. patent application Ser. No. 10/196,611, filed Jul. 16, 2002, entitled “Use Of Hydrogen Implantation To Improve Material Properties Of Silicon-Germanium-On-Insulator Material Made By Thermal Diffusion”, the entire contents of each of which are incorporated herein by reference.
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
10448948 |
May 2003 |
US |
Child |
10855915 |
May 2004 |
US |