This application is a divisional of commonly assigned U.S. patent application Ser. No. 07/699,427 entitled "A Family of Multiple Segmented Programmable Logic Blocks Interconnected by a High Speed Centralized Switch Matrix" of Mr. Om Agrawal et al. filed on May 13, 1991, which issued as U.S. Pat. No. 5,225,719 on Jul. 6, 1993, and which is a continuation-in-part of commonly assigned U.S. patent application Ser. No. 07/490,808 entitled "Multiple Array High Performance Programmable Logic Device Family" of Mr. Om Agrawal et al. filed on Mar. 7, 1990, which issued as U.S. Pat. No. 5,015,884 on May 14, 1991 and which was a continuation-in-part of commonly assigned U.S. patent application Ser. No. 07/243,574 entitled "Flexible, Programmable Cell Array Interconnected By A Programmable Switch Matrix," of Mr. Om Agrawal, et al. filed on Sep. 12, 1988, which issued as U.S. pat. No. 4,963,768 on Oct. 16, 1990 and which was a continuation-in-part of U.S. patent application Ser. No. 07/178,707, entitled "Multiple Array Customizable Logic Array," of Mr. Om Agrawal filed on Apr. 7, 1988, which issued as U.S. Pat. No. 4,931,671 on Jun. 5, 1990 and which was a continuation of U.S. patent application Ser. No. 06/717,640, entitled "Multiple Array Customizable Logic Array," of Mr. Om Agrawal, filed on Mar. 29, 1985, which issued as U.S. Pat. No. 4,742,252 on May 3, 1988.
Number | Name | Date | Kind |
---|---|---|---|
3566153 | Spencer | Feb 1971 | |
4034356 | Howley et al. | Jul 1977 | |
4207556 | Sugiyama et al. | Jun 1980 | |
4328565 | Harari | May 1982 | |
4361847 | Harari | Nov 1982 | |
4366393 | Kasuya | Dec 1982 | |
4409723 | Harari | Oct 1983 | |
4415818 | Ogawa et al. | Nov 1983 | |
4446534 | Smith | May 1984 | |
4525641 | Cruz et al. | Jun 1985 | |
4551815 | Moore et al. | Nov 1985 | |
4554640 | Wong et al. | Nov 1985 | |
4609986 | Hartmann et al. | Sep 1986 | |
4617479 | Hartmann et al. | Oct 1986 | |
4639893 | Eitan | Jan 1987 | |
4649520 | Eitan | Mar 1987 | |
4677318 | Veenstra | Jun 1987 | |
4684830 | Tsui et al. | Aug 1987 | |
4689654 | Brockmann | Aug 1987 | |
4691161 | Kant et al. | Sep 1987 | |
4703206 | Cavlan | Oct 1987 | |
4713792 | Hartmann et al. | Dec 1987 | |
4717912 | Harvey et al. | Jan 1988 | |
4742252 | Agrawal | May 1988 | |
4758746 | Birkner et al. | Jun 1988 | |
4758747 | Young et al. | Jul 1988 | |
4771285 | Agrawal et al. | Sep 1988 | |
4789951 | Birkner et al. | Dec 1988 | |
4871930 | Wong et al. | Oct 1989 | |
4876640 | Shankar et al. | Oct 1989 | |
4878200 | Asghar et al. | Oct 1989 | |
4903223 | Norman et al. | Feb 1990 | |
4912342 | Wong et al. | Mar 1990 | |
4933577 | Wong et al. | Jun 1990 | |
5015884 | Agrawal et al. | May 1991 |
Entry |
---|
Cole, Bernard, "Programmable Logic Devices: The Second Generation," Electronics, May 12, 1988, pp. 61-63. |
Cole, Bernard, "Altera Pushes EPLDs to 5,000 Gates and 60 MHz," Electronics, May 12, 1988, pp. 66-67. |
"TI's Erasable PLDs are Fast but Don't Need Much Power," Electronics, May 12, 1988, pp. 70-71. |
"Advanced Tools Tackle More Complex Chips in the New Generations of PLDs," Electronics, May 12, 1988, p. 111. |
Wirbel, Lorin, "Altera Details Max Scheme, Software," Electronics Engineering Times, May 16, 1988, p. 82. |
"Mentor Adds 80960 Simulation To Tool, Kit," Electronics, May 12, 1988. |
"Design Kit Handles One-Chip Modems," Electronics, May 12, 1988. |
Lytle, Craig, "Max+Plus Eases High-Density EPLD Design Entry," Altera Corporation, no date, pp. 1-4. |
Altera Product Specification "Multiple Array Matrix High Density EPLDs," no date, pp. 1-16. |
Faria, Donald F., et al., "`MAX` EPLDs Provide Solutions to Both `Gate Intensive` and `Register Intensive` Applications," Altera Corporation, no date, pp. 1-8. |
Altera Databook, Jan. 1988, pp. 2-1 through 2-29. |
PAL Device Data Book AMD/MMI, 1988, pp. i to 6-41. |
"FPGA 2010, Field Programmable Gate Array," Plus Logic, San Jose, Calif., no date, pp. 1-4. |
"FPGA 2020, Field Programmable Gate Array," Plus Logic, San Jose, Calif. no date pp. 1-37. |
"FPGA 2040, Field Programmable Gate Array", Plus Logic, San Jose, Calif., no date pp. 1-4. |
"FPGA 5110, Intelligent Data Buffer," Plus Logic, San Jose, Calif., no date pp. 1-6. |
S. Kassinidis, "Use FPGAs to Match A CPU to its Memory Subsystem," Electtronic Design, 7 pages, Feb. 8, 1990. |
"The Maximalist Handbook," Altera Corporation, San Jose, Calif., Jan. 1990, pp. 23-82. |
"Programmable Logic Device ATV5000," Atmel Corporation, San Jose, Calif., Feb. 1990, pp. 1-3. |
"Programmable Logic," Intel Corporation, Mt. Prospect, Il., (1990), pp. 2-43 to 2-49, 2-60 to 2-69. |
Pal Device Handbook, 1988 AMD/MMI. |
Number | Date | Country | |
---|---|---|---|
Parent | 699427 | May 1991 |
Number | Date | Country | |
---|---|---|---|
Parent | 717640 | Mar 1985 |
Number | Date | Country | |
---|---|---|---|
Parent | 490808 | Mar 1990 | |
Parent | 243574 | Sep 1988 | |
Parent | 178707 | Apr 1988 |