Claims
- 1. Apparatus for testing a node of a circuit under test comprising
- a high-speed formatter including means for generating a high-speed test signal for application to a driver connected to said node in response to test pattern information received from a pattern generator, means for receiving a high-speed detected test signal from a detector connected to said node, and means for generating two half-speed detected test signals that contain alternate cycles of said high-speed detected test signal,
- first and second fail processor means connected to said high-speed formatter to receive respective half-speed detected signals for generating and outputting failure information based upon the states of cycles of said half-speed detected test signals,
- said failure information outputted by a particular fail processor means relating to specific, but not necessarily all, cycles of its respective half-speed detected test signal,
- first and second fail memory means connected to respective said first and second fail processor means for receiving said failure information from respective said fail processor means and for storing said failure information for specific cycles received from said fail processor means in successive memory locations, and
- sequence means for storing information indicating the sequence in which failure information is stored in said first and second fail memory means.
- 2. The apparatus of claim 1 wherein said sequence means stores said information indicating the sequence as said first and second fail memory means store said failure information.
- 3. The apparatus of claim 1 wherein said sequence means comprises first and second sequence memory means associated with respective said first and second memory means, said sequence means storing sequence bits in said sequence memory means associated with said failure information for specific cycles, said sequence bits indicating whether the previously stored failure information is stored in the same fail memory means or not.
- 4. The apparatus of claim 3 wherein said sequence means stores a single sequence bit for failure information for a specific cycle.
Parent Case Info
This application is a continuation of application Ser. No. 861,758, filed Apr. 1, 1992 now abandoned, which is a continuation of application Ser. No. 494,601, filed Mar. 16, 1990.
US Referenced Citations (4)
Continuations (2)
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Number |
Date |
Country |
Parent |
861758 |
Apr 1992 |
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Parent |
494601 |
Mar 1990 |
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