Burford et al., "An 180 MHz 16 bit Multiplier Using Asynchronous Logic Design Techniques", IEEE 1994 Custom Integrated Circuits Conf., pp. 10.4-10.4.4. |
Ji-Ren et al., "A True Single-Phase-Clock Dynamic CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, vol. SC-22, No. 5, Oct. 1987, pp. 899-900. |
Lu and Samueli, "200-MHz CMOS Pipelined Multiplier-Accumulator Using a Quasi-Domino Dynamic Full-Adder Cell Design", IEEE Journal of Solid-State Circuits, vol. 28, No. 2, Feb. 1993, pp. 123-132. |
Song and DeMicheli, "Circuit and Architecture Trade-Offs for High-Speed Multiplication", IEEE Journal of Solid-State Circuits, vol. 26, No. 9, Sep. 1991, pp. 1184-1198. |
Ji-Ren, Yuan and Svensson, "High-Speed CMOS Circuit Technique", IEEE Journal of Solid-State Circuits, vol. 24, No. 1, Feb. 1989, pp. 62-70. |