The present disclosure relates generally to memory devices, and more particularly to circuits that access and sense data values from memory cells within memory devices.
High speed memory devices can play an important role in high speed applications, including but not limited to circuits for communication systems and networks. Conventionally, static random access memories (SRAM) fulfill high speed access roles. SRAMs can store data in a static fashion (i.e., do not have to be refreshed), typically with a latching structure.
A conventional SRAM sensing operation typically includes: discharging one bit line of a bit line pair (to thereby generate a small differential signal across a bit line pair); amplifying the small signal with sense amplifier circuits; and equalizing the bit lines and sense amplifier circuits for a next sensing operation.
At very high speeds of operation (e.g., 3 GHz clock speed or faster), it can be very difficult to accomplish the above sensing operation tasks within a single clock period.
Various conventional approaches to improving sensing operation speeds are known. The speed at which a bit line can discharge can be limited by a capacitance of the bit line. Reducing the number of memory cells per bit line can reduce bit line capacitance, but at an undesirable increase in device size. The speed at which a bit line can discharge can also be limited by a memory cell current (i.e., current drawn by memory cell when connected to the bit line). However, even the smallest increases in memory cell can greatly impact a device (as there can be millions of such cells in the memory device). Reducing the number of memory cells per bit line can reduce bit line capacitance, but at an undesirable increase in device size.
A sensing speed for a sense amplifier can be increased by reducing a mismatch at differential inputs of a sense amplifier (SA). However, reductions in mismatch can require increased circuit area, again undesirably increasing device size. Further, increasing SA input area can also increase capacitance, working against sensing speed.
At about time to, a memory cell can be connected to a bit line pair. One bit line can discharge through the memory cell, resulting in the bit lines “splitting” (developing a very small differential voltage). After time t0, first switch circuits 1105 can connect the bit line pair to pre-amplifier 1107.
At about time t1, pre-amplifier 1107 can be activated providing a fast, but small amplification of the differential signal PA_OUT. Also, about this time, the memory cell can be disconnected from the bit line pair, and the bit line pair can be equalized.
At about time t2, second switch circuits 1113 can connect sense amplifier 1109 to an output of pre-amplifier 1107, and sense amplifier 1109 can be activated, amplifying the small signal to generate a larger output signal SA_OUT.
The conventional memory device 1100 can provide needed access speeds. However, the use of two sensing circuits (1107 and 1109) can adversely contribute to increased device size.
Various embodiments will now be described that include memory devices, circuits, and methods that can enable high speed data accesses by incorporating time-interleaved sensing circuits. In the various embodiments shown, like sections are referred to by the same reference character but with the leading digit(s) corresponding to the figure number.
Referring now to
Memory cell and access circuits 102 can connect memory cells to bit lines 104 to generate signals on the bit lines. In particular embodiments, memory cell access circuits can include access devices (e.g., transistors) within such memory cells that are enabled to connect the memory cells to bit lines 104. In some embodiments, memory cells can have differential connections to bit lines. That is, each memory cell can be connected to a bit line pair (e.g., BL1/BL1B, BL0/BLB) in a read operation. However, in other embodiments, memory cells can have single-ended connections to bit lines. That is, each memory cell can be connected to one bit line in a read operation. It is understood that while two bit line pairs are shown (BL0/BL0B, BL1/BL1B), many such bit line pairs can be a part of memory cell and access circuits 102.
In one particular embodiment, memory cell and access circuits 102 can include static random access memory (SRAM) cells having complementary data storage nodes between cross-coupled transistors. The complementary data nodes can be connected to bit line pairs by driving word lines.
In some embodiments, memory cell and access circuits 102 can also include bit line equalization circuits, for “equalizing” the bit lines. It is understood that such equalization can include coupling bit line pairs to one another and/or connecting bit lines to an equalization voltage.
A column multiplexer (MUX) circuit 106 can selectively connect bit lines 104 to column MUX outputs 112-0/1 in response to address data ADD. In the embodiment shown, based on received address data (ADD), column MUX circuit 106 can connect one bit line pair to one column MUX output 112-0 and another bit line pair to the other column MUX output 112-1.
Sense amplifier sections 108-0/1 can each include interleave switches 114-0/1 and a sense amplifier (SA) 116-0/1. Interleave switches 114-0/1 can connect bit line lines (via column MUX circuit 106) to their respective sense amplifiers in response to select signals SA_SEL0/1. As will be described in more detail below, interleave switches 114-0/1 can connect bit lines to SAs 116-0/1 in a time interleaved fashion. That is, while one interleave switch (e.g., 114-0) connects one bit line (or bit line pair, e.g., BL0/BL0B) to one sense amplifier (e.g., 116-0), the other interleave switch (e.g., 114-1) can isolate its sense amplifier (e.g., 116-1) from the bit lines. Subsequently, interleave switch (e.g., 114-1) can connect another bit line (or bit line pair, e.g., BL1/BL1B) to its sense amplifier (e.g., 116-1), while the other interleave switch (e.g., 114-0) isolates its sense amplifier (e.g., 116-0) from the bit lines.
SAs 116-0/1 can amplify bit line signals to generate output values. In the embodiment shown, SAs 116-0/1 can be activated by corresponding sense amplifier enable signals SAEN0 and SAEN1. As in the case of interleave switches 114-0/1, while one sense amplifier (e.g., 116-0) is amplifying a signal, the other sense amplifier (e.g., 116-1) can be acquiring a signal. Subsequently, sense amplifier (e.g., 116-1) can be activated to amplify its acquired signal, while the other sense amplifier (e.g., 116-0) acquires a new signal.
In some embodiments, SAs 116-0/1 can also include SA equalization circuits. SA equalization circuits can drive inputs to SAs to an equalization voltage. In some embodiments, outputs nodes of SAs 116-0/1 can also be the input nodes of the SA. Thus, a sense amplifier equalization operation can drive an output of the SA to an equalization voltage.
A control circuit 110 can generate timing and control signals described above. In the particular embodiment shown, a control circuit 110 can generate signals according to a timing clock CLK, and can output additional control signals CTRL for controlling other operations of a memory device 100.
At about time t0, a memory cell can be connected to a bit line to generate a signal to be sensed (e.g., amplified). In the very particular embodiment shown, a memory cell can be connected to a bit line pair (BL0/BL0B). According to a data value stored by the memory cell, one bit line can remain at substantially at a bit line precharge voltage Vbleq, while the other bit line can begin to drop in voltage (i.e., the bit lines can start to “split”). It is understood that while
At about time t1, the bit lines connected to a memory cell (BL0/BL0B) can be connected to an SA (the SA corresponding to SA_OUT0). In the very particular embodiment of
It is understood that starting at time t1, inputs to a sense amplifier can also start to “split”.
In particular embodiment shown, also at time t1, the bit line pair (BL0/BL0B) can be disconnected from the sense amplifier and equalized, driving both bit lines toward Vbleq. Also at this time (or prior to), the memory cell can be disconnected from the bit lines.
Some time after time t1 (i.e., after the bit lines have been disconnected from the sense amplifier), the SA previously connected to BL0/BL0B can be activated, amplifying any differential voltage developed at its inputs. In one very particular embodiment, such amplification can result in sense amplifier output (and input) nodes being driven to different power supply voltages. In the very particular embodiment of
At time t2, another memory cell can be connected to a bit line to generate a signal to be sensed (e.g., amplified). In the very particular embodiment shown, a memory cell can be connected to bit line pair (BL1/BL1B), and such bit lines can start to split. It is noted that BL1/BL1B can be the same pair as BL0/BL0B. Thus, in the embodiment shown, a bit line pair can be connected to one of multiple sense amplifiers each cycle, in a time multiplexed fashion. At the same time, sense amplifier operations can occur over more than one cycle.
Some time after t2, the sense amplifier corresponding to SA_OUT0 can equalize its input (and output) nodes, driving them back toward Vsaeq. It is understood that while a sense amplifier equalization operation is shown at time t3, such an operation can occur later or earlier in time.
At about time t3, bit lines BL1/BL1B can be connected to an SA (the SA corresponding to SA_OUT1). In the very particular embodiment of
Also at about time t3, bit line pair BL1/BL1B can be equalized.
It is noted that while
Referring still to
As also shown in
At about time t0, a memory cell can be connected to one bit line to generate a signal to be sensed. According to a data value stored by the memory cell, the bit line can fall (i.e., discharge) or rise (i.e., charge).
At about time t1, the bit line BL0 can be connected to one input of an SA (the SA corresponding to SA_OUT0). The other input of the SA can be connected to a reference voltage (which can be Vsaeq, in some embodiments). In the particular embodiment shown, also at time t1, the bit line BL0 can be equalized (driven to Vbleq).
At about time t2, another memory cell can be connected to a bit line BL1 (or BL0).
From the embodiments above, is it understood that use of time interleaved sensing can enable relatively large signal development times at the inputs of sense amplifiers. More particularly, referring to
Examples of sense amplifiers circuits that can be included in embodiments will now be described.
In operation, signals SAEN0/1 can be activated, and sense amplifier SA 516 can drive one of sense nodes to one power supply voltage (e.g., Vpwr1), and the other sense node to the other power supply voltage (e.g., Vpwr0), based on a differential voltage between the sense nodes 520-0/1 (formed during a signal development time, as noted above).
It is understood that while particular sense amplifiers are shown in
While embodiments shown herein can allow for compact sense amplifier designs, and hence reductions the area needed for sense amplifiers, other embodiments can provide for reduced sense amplifier area by multiplexing sense amplifiers. One such embodiment is shown in
The embodiment of
The embodiment of
In operation, during a first clock cycle period, one interleave switch (e.g., 814-0) can connect one column MUX output (e.g., 812-0) to its corresponding sense amplifier 816-0. Over two or more clock cycle periods, sense amplifier 816-0 can develop a differential across its inputs, amplify the differential and then equalize its inputs. During a second clock cycle period (that follows the first clock cycle period, and overlaps with the activation of sense amplifier 816-0), the other interleave switch (e.g., 814-1) can connect the other column MUX output (e.g., 812-1) to its sense amplifier 816-1. Over two or more clock cycle periods, sense amplifier 816-1 can develop a differential across its inputs, amplify the differential and then equalize its inputs.
In other operations, the order of operations can also be reversed. For example, interleave switch 814-0 can connect to column MUX output 812-1, followed by interleave switch 814-1 connecting to column MUX output 812-0.
In other operations, access to sense amplifiers 816-0/1 can be reversed. For example, in one clock period, interleave switch 814-1 can connect column MUX output 812-0, while in a preceding or subsequent clock period, interleave switch 814-0 can connect column MUX output 812-1.
The embodiment of
The embodiment of
Referring to
Subsequently, signal SA_SEL01 can be activated (driven high), connecting sense amplifier 916-0 to bit line pair BL0/BL0B. As a result, inputs of the sense amplifier (shown as SA_OUT0) can begin to split. Word line WL1 can be deactivated (return low), disconnecting the memory cell from bit line pair BL0/BL0B.
Signal SA_ENO can be activated, and amplifier section 936-0 can amplify the differential voltage at the input of sense amplifier section 916-0, resulting a large output signal SA_OUT0.
Subsequently, signal SA_EQ0 can be activated (driven high), and inputs (outputs) of sense amplifier section 934-0 can be equalized.
It is noted that while sense amplifier section 916-0 is amplifying, word line WL0 can be activated, and the same sense operation can occur, but with sense amplifier section 908-1. Such an operation can connect a memory cell to the same bit line or a different bit line as the previous operation. That is, while
As noted for
In
As noted above, while some embodiments show differential memory cell connections, alternate embodiments can include single ended connections. As but one very particular example, an embodiment like that of
It should be appreciated that in the foregoing description of exemplary embodiments, various features are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.
Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.
This application claims the benefit of U.S. provisional patent application Ser. No. 61/602,270 filed on Feb. 23, 2012, the contents of which are incorporated by reference herein.
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Number | Date | Country | |
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61602270 | Feb 2012 | US |