BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing aspects and many of the attendant advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:
FIG. 1A and FIG. 1B shows the conventional trench Schottky diode devices with a trench termination structure.
FIG. 2 is a cross-sectional view of forming an oxide layer on an n− epi-layer and an n layer beneath the n− epi-layer of an n+ semiconductor substrate in accordance with the present invention.
FIG. 3 is a cross-sectional view of forming hard mask pattern layer on the oxide layer and forming a dual implant region into n-epi layer in accordance with the present invention.
FIG. 4 is a cross-sectional view of performing thermal oxidation to form LOCOS structure in accordance with the present invention.
FIG. 5 is a cross-sectional view of forming polycrystalline silicon layer on all areas.
FIG. 6 is a cross-sectional view of performing an etch back step to remove excess polycrystalline silicon layer over the epi-layer in accordance with the present invention.
FIG. 7 is a cross-sectional view of Schottky power rectifier structure with a Schottky barrier silicide layer and a top metal on the front surface and a metal layer on the rear surface in accordance with the present invention.
FIG. 8 is a cross-sectional view of forming an n doped region beneath the first oxide layer in accordance with the second preferred embodiment of the present invention.
FIG. 9 is a cross-sectional view of Schottky power rectifier structure with an n doped region beneath silicide layer to reduce the resistance in accordance with the second preferred embodiment of the present invention.
FIG. 10 is a cross-sectional view of forming a p doped region beneath the LOCOS in accordance with the third preferred embodiment of the present invention.
FIG. 11 is a cross-sectional view of Schottky power rectifier structure with a p doped region beneath the LOCOS in accordance with the third preferred embodiment of the present invention.
FIGS. 12A and 12B are synoptic layouts to show the cells and the termination region; only two masks are demanded.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
As depicted in the forgoing background of the invention, the conventional techniques requires at least three photo masks to form a power rectifier device and its termination structure. The present invention can simplify the processes and reduce the photo mask requirement to two. In addition, the structure of the invention proposed contains LOCOS at the bottom of the trenches, and hence, the structure is capable of tolerating high reverse biased voltage. The detailed descriptions are as follows:
Referring to FIG. 2, a cross-sectional view shows an n+ doped semiconductor substrate 100 thereof formed successively with an n− epi-layer 105, a first oxide layer 110, a first nitride layer (Nit 1) 115, and a second oxide layer 120. The first oxide layer 110 is formed of about 5-200 nm by a thermal oxidation or by a chemical vapor deposition (CVD). The nitride layer 115, and the second oxide layer 120 are formed by CVD to about 50-500 nm and 40-1000 nm, respectively, in thickness.
Referring to FIG. 3, to define an active region, a photoresist pattern (not shown) is then formed on the second oxide layer 120. Next, a hard mask formed of the second oxide layer 120/the nitride layer 115/the first nitride layer 110 is patterned by an etching step using the photoresist pattern as a mask.
After a removal of the photoresist layer, another etching process to recess the substrate is performed to form first trenches 130 and second trench (hereinafter called termination trench) 130A, which have a depth of about 0.5-10 μm. A thermal oxidation to grow a third oxide layer 135 of about 2-200 nm on the bottoms and the sidewalls except surfaces of the dielectric layers (110, 115 and 120) of the trenches 130,130A is then performed. Next, a second thin nitride layer (Nit2) 140 of about 5-100 nm in thickness is then deposited. An anisotropic etch-back process is then carried out to form thin Nit2 spacers 140 on the trench sidewalls.
Still referring to FIG. 4, a thermal oxidation is then followed to grow a thick field oxide layer 150, 150A by consuming the silicon layer inside the trench bottom. The thick field oxide layer 150, 150A has a thickness of about 0.2 μm-2 μm.
Referring to FIG. 5, a polycrystalline silicon layer 160 deposited on entire surfaces and filled the trenches 130 and 130A is then conducted. The polycrystalline silicon layer 160 can be either an n− impurity doped or p+ doped or even undoped silicon layer. Subsequently, an anisotropic etching process is then performed to remove the excess polycrystalline silicon layer 160 by using the second oxide layer 120 and/or the nitrogen layer 115 as an etch stop layer. A spacer-like polygate 160A formed on the sidewall of the termination trench 130A is resulted. Thereafter, the second oxide layer 120 and the nitrogen layer 115, and first oxide layer 110 are then removed sequentially. The results are shown in FIG. 6.
Referring to FIG. 7, a barrier metal layer 165 deposited by sputtering on the front surfaces of the n epi-layer 105 is performed, as shown. The material of the barrier metal layer, for instance, Ti, Ni, Cr, Mo, Pt, Zr, W etc., can be served as candidates. A thermal anneal is then done to form metal silicide 170 layer in nitrogen ambient. Worthwhile, the silicide layer 170 is extended to cover all areas of the active region except the exposed portion of the field oxide region 150A of the termination trench 130A. In the active region, since both the nitride spacer 140 and the oxide spacer 135 are thin, the upper surface of them is found to be formed with the silicide layer 170 due to the bridge effect. The un-reacted metal layer on the termination field oxide region 150A is then removed. Afterward, a top metal layer 180 is deposited on the entire surfaces. The material of the top metal layer 180 is chosen from a TiNiAg layer or a TiW/Al layer or a Al layer. Subsequently, a backside layer grinding is performed to remove all of the layers formed on the backside surface of the substrate 100 during aforementioned processes and then a metal layer 190 function as a cathode is formed on the grinded surface.
The forging description is presented to enable one of ordinary skill in the art to make and use the invention and is provided in the context of a patent application and its requirement. The preferred embodiment is not intended to be limited to the embodiment shown but is to be accorded the widest scope consistent with the principles and features described herein. For example, as is shown in FIG. 8 and FIG. 9, the second preferred embodiment, shows an example of the modification. FIG. 9 shows a cross-sectional view of the resultant structure. It shows an extra n doped layer 195 beneath the metal silicide layer 170 comparing with the first preferred embodiment. The n doped layer 195 can be doped before forming first nitride layer, please see FIG. 8.
The third preferred embodiment is shown in FIG. 10, and FIG. 11. FIG. 10 shows a p type doping region 138 is formed beneath the trench bottom by an ion implant before performing oxidation process to form field oxide region 150. The remnant fabricating steps are the same as those mentioned in the first preferred embodiment. FIG. 11 shows a resultant structure, which shows a p region 138 formed beneath each field oxide region 135 that will further minimizing the current leakage and enhance the breakdown voltage when the device undergoes a reverse biased.
FIG. 12A shows a synoptic layout of the devices in accordance with the present invention. It shows more first trenches 130 formed than forgoing cross-sectional view. Preferably, the size of each first trench 130 in the active region is about 2 μm×2 μm and spaced each other is between 2-20 μm. Other than the first trenches 130 distributed in a form of holes, they can be distributed in a form of long strips, as is shown in FIG. 12B. Typically, the size of each strip is 0.6 μm×20 μm and the spacing (meas width) between two strip is between about 2-20 μm. Thereafter, as is shown in the figure, the total area of the first trench 130 occupied are only a small fraction. More importantly, only two photo masks are required—one is to define the hard mask, the other one is to define the anode.
The benefits of this invention are:
- (1) Only two masks are used and thus the manufacturing processes are much simpler than conventional processes.
- (2) The LOCOS structure 150 at the bottom of the first trenches 130 and termination trench 130A can enhance the capability of inhibiting breakdown premature when the device is under a reverse biased. More importantly, the LOCOS structure formation in the trench bottom is by means of thin nitride spacer 140 and thus the width of each trench 130 does not demand to be as wide as the conventional devices due to slim effect.
- (3) The forward current is almost composed of majority carriers and thus the switching speed performance of the device is superior to those of the conventional devices.
- (4) The termination field oxide regions 150A are broad and flatted and thus the bending regions of the depletion boundary are anticipated to be far away from the active region than the conventional device.
As is understood by a person skilled in the art, the foregoing preferred embodiment of the present invention is an illustration of the present invention rather than limiting thereon. It is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims, the scope of which should be accorded the broadest interpretation so as to encompass all such modifications and similar structure.
Patent Application
20070290234
