High voltage charge pump regulation system with fine step adjustment

Abstract

A regulator system for a charge pump system divides the binary decoding into two branches. One controls a set of parallel connected resistors for fine output voltage steps. The other branch controls a serial resistor to provide the large step size. For example, a 9-bit digital input signal is split into 2 least significant for the fine adjustment and the other 7 bits for the larger adjustments. In the example of a 50 mV step size, in one current path 2 bits of the binary input then control two parallel resistors for 50 mV and 100 mV step size, and in the other current path 7 bits are used for one-hot-decode control serial resistors to provide a 200 mV step size. A unity gain operational amplifier and a high voltage device are added in between the two branches to decouple the parasitic capacitance of large parallel resistors from the other elements.

Description

FIELD OF THE INVENTION

This invention pertains generally to the field of charge pumps and more particularly to the regulation of charge pumps.

BACKGROUND

Charge pumps use a switching process to provide a DC output voltage larger than its DC input voltage. In general, a charge pump will have a capacitor coupled to switches between an input and an output. During one clock half cycle, the charging half cycle, the capacitor couples in parallel to the input so as to charge up to the input voltage. During a second clock half cycle, the transfer half cycle, the charged capacitor couples in series with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated in FIGS. 1a and 1b. In FIG. 1a, the capacitor 5 is arranged in parallel with the input voltage V_IN to illustrate the charging half cycle. In FIG. 1b, the charged capacitor 5 is arranged in series with the input voltage to illustrate the transfer half cycle. As seen in FIG. 1b, the positive terminal of the charged capacitor 5 will thus be 2*V_IN with respect to ground.

FIG. 2 is a top-level block diagram of a typical charge pump arrangement. A pump 201 has as inputs a clock signal and a voltage Vreg and provides an output Vout. The high (Vdd) and low (ground) connections are not explicitly shown. The voltage Vreg is provided by the regulator 203, which has as inputs a reference voltage Vref from an external voltage source and the output voltage Vout. The regulator block 203 regulates the value of Vreg such that the desired value of Vout can be obtained. (A charge pump is typically taken to refer to both the pump portion 201 and the regulator 203, when a regulator is included, although in some usages “charge pump” refers to just the pump section 201.)

Charge pumps are used in many contexts. For example, they are used as peripheral circuits on EEPROM, flash EEPROM and other non-volatile memories to generate many of the needed operating voltages, such as programming or erase voltages, from a lower power supply voltage. For many of these uses, it important that the output is accurately regulated to the desired output level. A number of charge pump designs are know in the art, but given the common reliance upon charge pumps, there is an on going need for improvements in charge pump system design, including the regulation elements.

SUMMARY OF THE INVENTION

According to a first set of aspects, a charge pump system includes a charge pump circuit connected to receive a control signal and, in response to the control signal, provide an output voltage at an output node and regulation circuitry responsive a multi-hit digital value. The regulation circuitry includes a first comparator, having as output the control signal, a first input connected to receive a first reference voltage, and a second input connected to a first node; a first current branch connected between the output node and ground; and a second current branch connected between the output node and ground in parallel with the first current branch. The first current branch has a first variable resistance connected between the output node and the first node and a first fixed resistance connected between the first node and ground, where the value of the first variable resistance is determined by a first set of bits of the digital value. The second current branch includes a second variable resistance connected between the output node and ground, including a fixed portion and an adjustable portion having a value determined by a second set of bits of the digital value, the bits of the second set being of lesser significance than the bits of the first set of bits in the digital value. The second current branch also includes a unity gain op-amp section having a first transistor connected between the output node and the second variable resistance and a second comparator having an output connected to the control gate of the first transistor, a first input connected to receive a second reference voltage, and a second input connected to a node between the first transistor and the second variable resistance.

Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.

BRIEF DESCRIPTION OF THE DRAWINGS

The various aspects and features of the present invention may be better understood by examining the following figures, in which:

FIG. 1 a is a simplified circuit diagram of the charging half cycle in a generic charge pump.

FIG. 1 b is a simplified circuit diagram of the transfer half cycle in a generic charge pump.

FIG. 2 is a top-level block diagram for a regulated charge pump.

FIG. 3 shows more detail on the regulation circuitry.

FIG. 4 is an example of regulation circuitry response to a multi-bit binary input.

FIG. 5 is an exemplary embodiment of a charge pump system with fine step adjustment.

DETAILED DESCRIPTION

The main aspects considered here related to charge pump systems and particularly to the regulation process for such systems. Conventional voltage regulation circuitry, such as the high voltage regulation system used for a charge pump to supply programming voltages VPGM for a non-volatile memory, uses resistor chains as voltage divider to control the VPGM level and step size. As technology scale down, and VPGM step size required finer increments, conventional VPGM regulator requires a larger resistor chain. The parasitic capacitance of this large resistor chain becomes dominant, increasing VPGM ripple. The regulator system use approach described below can reduce regulator resistors chains, minimize parasitic capacitance, and thus reduce VPGM ripple.

FIG. 3 illustrates a conventional regulator system. The charge pump 301 has a clock signal CLK as input and is responsive to the enable signal ENA to generate the output voltage Vout. The regulation circuit uses a voltage divider of R1305 and R2307 connected in series between Vout and ground to generate voltage VMON that is compared to compare with a reference voltage, VREF, in the comparator 303 to generate a FLAG. The clock CLK can then be gated with this FLAG signal to produce a charge pump clock. The reference value is based on a reliably know value, such as from a band gap generator and the rations of R1 and R2 are then taken to set the desired Vout value in terms of VREF.

Charge pumps are typically used as peripheral elements are a circuit that needs higher voltages than the supply level. An example is a non-volatile memory, such as flash memory, where charge pumps are used to provide the high voltages used in programming and erasing memory cells, and also for the various voltages used in sensing and verifying the memory cells. In such arrangements, a number of different, accurately determined values may be needed, such the programming voltages of each of the steps in a programming staircase type waveform, or the many voltages levels used for sensing in multi-state NAND arrays. (More detail on such memory systems can be found in US patent publication US-2009-0296488-A1, for example.) The arrangement shown in FIG. 3 is limited to provide a single regulated value as the ratio of resistances in the regulation circuit is fixed. Multiple regulated outputs, such as needed for a programming voltage VPGM, can be provided by use of a variable resistive divider to provide the voltage compared to the reference value.

To control the VPGM level and step size, a binary input signal can be provided of, say, 9 bits can be used to vary the level. The 9 bits can be decoded into the 3 least significant bits, for the finer adjustments, and the 6 most significant bits, where the 6 bits of larger steps can be implemented as a single variable resistance connected in parallel below the VMON node with 3 smaller resistances for the finer increments. If one large resistor is turned on, this means less current and therefore VPGM level is regulated at a lower level. If many resistors in parallel are on, a larger current results and therefore a higher VPGM level. As VPGM step size requires smaller increments (50 mV, for example), more parallel resistors are added to create a finer step. Thus, a large resistor chain is required and more parasitic capacitance is added to VMON. Large parasitic capacitance at the VMON node makes it harder to detect small movement at VPGM, resulting in large VPGM ripple.

FIG. 4 shows this sort of largely conventional high voltage regulation circuit. The pump 401 and comparator 403 can be more or less as before. To draw low current levels, the VREF can be taken as, say, 0.4V. The resistor Rb405 above the VMON node is again fixed, but the variable resistance below the VMON node is as described in the last paragraph. In this example, the step size is taken as 50 mV. The variable resistance R₄₀₀ 407 will be adjustable in 400 mV steps, being controlled by the 6 most significant bits of the digital input. For example, R₄₀₀ 407 could be implement as a string of resistance connected in series that can be tapped at various points based on the decode value of these 6 bits (that is, a thermometer-coded DAC, or thermo decode, resistance). The three least significant bits are 50 mV, 100 mV, and 200 mV steps respectively effected by R₅₀ 413, R₁₀₀ 411, and R₂₀₀ 409. By using 6 bits decoded for R₄₀₀ 407 and 3 bits for R₅₀ 413, R₁₀₀ 411, and R₂₀₀ 409, the arrangement of FIG. 4 can cover a range of 8.0V-33.5V in steps of 50 mV.

To provide a regulated output voltage range of 3.0V-28.5V with step size of 50 mV for use in erase operation, the resistor R_offs 415 can be selectively connected between the VMON node and ground to offset the output range, lowering it by 5V. When R_offs 415 is connected, the current out of Rb 405 is split into I1 though the adjustable resistances to provide the steps size and I2 though R_offs 415 to lower the range to start at 3V for erase operations.

Although this arrangement can provide the desired step size over the desired range, the resistances connected in parallel must be taken quite large to avoid drawing excessive current. An actual example would use something like a total of ˜56M ohm due to the DAC resistors in arranged parallel. Such a large resistor chain will add a large amount of parasitic capacitance to VMON, making it harder to pick up small variation in the output at VPGM, resulting in large amount of output ripple. Consequently, it would quite useful to find a way to use smaller resistance values, thereby decreasing this parasitic capacitance and also needed area for resistors, while still drawing a relatively small amount of current.

The main discussion here is related to the regulation circuitry of the charge pump system and how the output voltage is compared with the reference level in order to generate the control signals used for regulation. With respect to the charge pump itself, any of the various designs (voltage doubler, Dickson type, and so on) can be used. Similarly, there are many ways for how the output is regulated based upon the control signal, such as varying the frequency of the input clock signal, the amplitude of the input voltage, the number of stages, and so on. More details on these aspects, which can be applied to the exemplary embodiments below as well as to the examples above can be found, for example, in “Charge Pump Circuit Design” by Pan and Samaddar, McGraw-Hill, 2006, or “Charge Pumps: An Overview”, Pylarinos and Rogers, Department of Electrical and Computer Engineering University of Toronto, available on the webpage “www.eecg.toronto.edu/˜kphang/ece1371/chargepumps.pdf”. Further information on various other charge pump aspects and designs can be found in U.S. Pat. Nos. 5,436,587; 6,370,075; 6,556,465; 6,760,262; 6,922,096; 7,030,683; 7,554,311; 7,368,979; 7,795,952; 7,135,910; 7,973,592; and 7,969,235; US Patent Publication numbers 2009-0153230-A1; 2009-0153232-A1; 2009-0315616-A1; 2009-0322413-A1; 2009-0058506-A1; US-2011-0148509-A1; 2007-0126494-A1; 2007-0139099-A1; 2008-0307342 A1; and 2009-0058507 A1; and applications Nos. 12/973,641 and 12/973,493, both filed Dec. 20, 2010. In addition, two specific examples of charge pump systems where the regulation circuitry described here can employed can be found in U.S. patent application Ser. No. 13/228,605, filed Sep. 9, 2011, and a U.S. patent application Ser. No. 13/240,664, entitled “Dynamic Switching Approach to Reduce Area and Power Consumption of High Voltage Charge Pumps” by Qui Vi Nguyen, Khin Htoo, and Jonathan Huynh, that is being filed concurrently herewith.

To overcome the imitations described above, a main aspect of the charge pump system presented here uses a regulator system that divides the binary decoding into two branches. One controls a set of parallel connected resistors for fine the VPGM step. The other controls a serial resistor to provide large step size. The exemplary embodiment, discussed with respect to FIG. 5, will a 9-bit digital input signal, split into 2 least significant for the fine adjustment and the other 7 bits for the larger adjustments, and a 50 mV step size, although the discussion readily extends to other numbers of bits, a different splitting of these bits, a different step size, or any combination of these. In the example, in one current path 2 bits of the binary input control two parallel resistors for 50 mV and 100 mV step size, and in the other current path 7 bits are used for one-hot-decode control serial resistors to provide a 200 mV step size. A unity gain operational amplifier and a high voltage (HV) device are added in between the two branches to decouple the parasitic capacitance of large parallel resistors from the other elements. Thus, the sensing node VMON consequently has less parasitic capacitance and is more sensitive to VPGM movement, resulting in less ripple at the output node VPGM.

Referring now to FIG. 5, a pump 501 again receives the inputs of an enable signal ENA, a clock signal CLK, and the control signal FLAG and produces the output voltages Vout, such as a programming voltage VPGM. The comparator 503 of the control circuitry supplies the FLAG signal by comparing a reference voltage VREF to the voltage at the node TAP, which is derived from Vout. Here the reference voltage VREF higher than described above with respect to FIG. 4 as the amount of current drawn in this design is less and a higher values, such as VREF=˜1.2V, is used to reduce bounce. A fixed resistance Rstep 505 is connected to the output of the node, after which the circuit splits into a first branch, with current I1, and a second branch, with current I2, connected in parallel.

The comparison node TAP is taken from an internal node of the second branch above a fixed resistance R_base 517. The resistance R₂₀₀ 507 is adjustable in increments of 200 mV, response to the 7 most significant bits of the binary input signal. (This can again be a chain of series connected resistors that can be tapped at a point based on the input signal.) The 9-bit (in this example) binary signal can be provided from the state machine (not shown) on the memory chip or other control circuitry, where, depending on the program and erase levels needed, the 9-bits will generated accordingly. To allow for the offset in output voltage when used for erase operations, a resistor R_offs 515 is connected in series with R_base 517. (Here, R_offs 515 is connected above R_base 517, but that could be switched or otherwise arranged, depending on the embodiment.) R_offs 515 can selectively be bypassed to shift the levels of Vout to start at a lower value, here to start Vout at 3V for erase levels.

The second branch, with current I2, uses two binary bits for the fine 50 mV and 100 mV steps. The current I2 flows through the transistor 523 to the parallel connected resistors R₀ 509, R₁₀₀ 511, and R₅₀ 513 and on to ground. The fixed portion R₀ 509 of these resistors is included to provide a constant resistance path for I2 to ground. The resistors R₁₀₀ 511 and R₅₀ 513 respectively selectively connectable to supply 100 mV and 50 mV steps for Vout when under regulation. The gate of the transistor 523 is connected controller by the output of operational amplifier 521, which has one input connected to receive a reference voltage VREF (here the same reference value as used for 503, ˜1.2V in this example) and the other input connected to take feedback from the node X below the transistor 523. The comparator 521 and transistor 523 work together as a unity gain op-amp to set the node X to VREF (here ˜1.2V). As the system here is for use with high voltages, a transistor 525 is placed above the transistor 523, although in other applications this may not be needed. For the exemplary embodiment, the gate of transistor 525 can be set at about the ˜4v level. More generally, when such a protective device is needed, its gate setting level should be such as to pass about 4v to source side of the high voltage NMOS 525. This is to protect NMOS 523, since it should not see a level higher than 5v. Alternately, in other high voltage situations, the circuit can use a high voltage NMOS for 523 and remove the NMOS 535, but the use of low voltage transistor at 523 is selected here for better gain and process variation.

This arrangement can provide the desired small step size in Vout, such as needed in VPGM values, with small amounts of ripple. For the exemplary embodiment, the step size is again 50 mV with the same range as for FIG. 4, with 2 binary bits used for the 50 mV and 100 mV steps (by R₅₀ 513 and R₁₀₀ 511, respectively) and the 7 most significant bits in one hot decode with a 200 mV step size. The use of the unity gain arrangement of 521 and 523 provides for a constant current flow of 12 through the set of resistors below node X, where the current I2 will be equal to the VREF divided by selected resistors, with the same current through Rstep 505 to determine the fine step size. The fine step size from R₅₀ 513 is then (VREF/R₅₀)*R_step=1.2*(R_step/R₅₀), with R₁₀₀ 511 providing an increment determined by 1.2*(R_step/R₁₀₀). Similarly, the voltage increment provided by R₂₀₀ 507 is 1.2*(R₂₀₀/Rbase).

The arrangement of FIG. 5 divides the binary decoding for Vout into two branches, one of the parallel resistances for the fine Vout steps and the other of serial resistors to provide the larger step size. This subdivision of the resistance ladder into two branches, one parallel and one serial, and separating of them by an operational amplifier, minimizes the capacitive load at the TAP input of the comparator 503. As a result, the regulator system responds faster to changes in the Vout level. The exemplary embodiment uses 2 bits to control 2 parallel resistors for 50 mV and 100 mV step size, and 7 other bits for one-hot-decode control serial resistors to provide 200 mV step size, but other values can be used as appropriate for the application. Additionally, although the regulation circuitry is here connected between Vout and ground (or, more generally, the low voltage level on the chip), the arrangement could be modified for use with negative charge pumps.

Consequently, the exemplary embodiment of FIG. 5 has the advantages of a regulator area is smaller when compared to a conventional scheme, less output ripple, and better DAC linearity. The unity gain operational amplifier and (optional) HV device are added in between the two branches to decouple the parasitic capacitance of the large parallel resistors from the other leg, where the comparison is made with the reference level to generate the FLAG signal. Thus, sensing node (TAP) has less parasitic capacitance, and it is therefore more sensitive to VPGM movement, resulting in a decrease in ripple at VPGM.

Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. Consequently, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as encompassed by the following claims.

Claims

1. A charge pump system, comprising: a charge pump circuit, connected to receive a control signal and in response thereto, provide an output voltage at an output node; andregulation circuitry responsive a multi-bit digital value, including: a first comparator, having as output the control signal, a first input connected to receive a first reference voltage, and a second input connected to a first node;a first current branch connected between the output node and ground, comprising: a first variable resistance connected between the output node and the first node, the value of the first variable resistance is determined by a first set of bits of the digital value;a first fixed resistance connected between the first node and ground;a second current branch connected between the output node and ground in parallel with the first current branch, the second current branch comprising: a second variable resistance connected between the output node and ground, including a fixed portion and an adjustable portion having a value determined by a second set of bits of the digital value, the bits of the second set being of lesser significance than the bits of the first set of bits in the digital value; anda unity gain op-amp section, including: a first transistor connected between the output node and the second variable resistance; anda second comparator having an output connected to the control gate of the first transistor, a first input connected to receive a second reference voltage, and a second input connected to a node between the first transistor and the second variable resistance.

2. The charge pump system of claim 1, where the digital value is of N bits with the bits of the first set being the M most significant bits of the digital value and the second set being the (N-M) least significant bits of the digital value, where M and N are positive integers, N being greater than M.

3. The charge pump system of claim 1, wherein the second variable resistance comprises: N resistances selectively connectable between the output node and ground in parallel with a second fixed resistance in response to the N least significant bits of the digital value.

4. The charge pump system of claim 1, wherein the first and second reference voltages are of the same value.

5. The charge pump system of claim 1, wherein the second current branch further comprises: a second transistor connected as a high-voltage protection element in series with the first transistor between the output node and the first transistor.

6. The charge pump system of claim 1, wherein the first current branch further comprises: an offset resistance selectively connectable between the output node and the first node in series with the first variable resistance.

7. The charge pump system of claim 1, wherein the regulation circuitry further comprising: a second fixed resistance, wherein the first and second current branches are both connected to the output node through the second fixed resistance.