HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF

Abstract

A high voltage device includes a semiconductor substrate and a gate. The semiconductor substrate includes a first doped region having a first conductive type, a second doped region having a second conductive type, a third doped region having the second conductive type, a fourth doped region surrounding the third doped region and having the second conductive type, and a fifth doped region surrounding the third doped region and having the second conductive type. The gate is disposed between two spacers to separate the second doped region from the third doped region, so as to control the conduction of the second doped region and the third doped region. In the high voltage device, the fifth doped region surrounds the third doped region, so as to strengthen the coverage for the third doped region and improve the ion concentration uniformity on the bottom of the third doped region to reduce leakage current.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

The invention will be described according to the appended drawings.

FIG. 1 shows a schematic view of a conventional ESD protection circuit.

FIG. 2 is a schematic sectional view of the structure of the HVNMOS transistor applied in the ESD protection circuit in FIG. 1.

FIG. 3( a) is a characteristic curve diagram of I_ds and VDS of the HVNMOS transistor in FIG. 2.

FIG. 3( b) is a characteristic curve diagram of the substrate current I_sub and the gate voltage VG of the HVNMOS transistor in FIG. 2.

FIG. 4 is a schematic sectional view of the structure of the high voltage device according to the present invention.

FIGS. 5( a)-5(d) are schematic views of manufacturing the high voltage device according to the present invention.

FIG. 6( a) is a characteristic curve diagram of I_dS and VDS of the high voltage device according to the present invention.

FIG. 6( b) is a characteristic curve diagram of the substrate current I_sub and the gate voltage VG of the high voltage device according to the present invention.

FIG. 7 is a characteristic curve diagram of the substrate current and VDS when the high voltage device is turned off.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 4 is a schematic sectional view of the structure of the high voltage device 2 according to the present invention. The high voltage device 2 includes a semiconductor substrate 27 and a gate 20 closely disposed between two spacers 21. The semiconductor substrate 27 includes a P-type well region 26, an N-type second doped region 22, an N-type third doped region 23, an N-type fourth doped region 24 surrounding the N-type third doped region 23, and an N-type fifth doped region 25 surrounding the N-type third doped region 23. The gate 20 is used to control the conduction between the N-type second doped region 22 and the N-type third doped region 23. The length L2 of the N-type fourth doped region 24 is larger than the length L1 of the N-type fifth doped region 25, and the depth D1 of the N-type fifth doped region 25 is larger than the depth D2 of the N-type fourth doped region 24. Therefore, the N-type fifth doped region 25 completely covers the N-type third doped region 23, but does not cover the interfacial region of the N-type fourth doped region 24 and the bottom of the adjacent gate 20. Furthermore, the N-type third doped region 23 and the N-type fourth doped region 24 form a double diffusion drain.

FIGS. 5( a)-5(d) are schematic views of the flow of manufacturing the high voltage device 2 in FIG. 4 according to the present invention. First, a P-type well region 26 is formed on the semiconductor substrate 27, as shown in FIG. 5(a). Then, an N-type fifth doped region 25 is formed in the P-type well region 26, as shown in FIG. 5(b). A predetermined ion implantation region for the N-type fifth doped region 25 is defined by a photomask, and then an ion implantation process and a thermal diffusion process are performed, thereby forming the N-type fifth doped region 25. Next, the gate 20 and two spacers disposed on both sides of the gate 20 are formed on the surface of the P-type well region 26. After that, the N-type fourth doped region 24 is formed through a self-aligned process by using the gate 20 and the spacers 21 as an ion implant mask, as shown in FIG. 5(C). The N-type fourth doped region 24 and the N-type fifth doped region 25 have the same doping concentration. Thereafter, the N-type second doped region 22 and the N-type third doped region 23 are formed through another doping process, as shown in FIG. 5(d). The N-type second doped region 22 and the N-type third doped region 23 have the same doping concentration (about 10¹⁵/cm²), which is larger than the doping concentration (10¹²/cm²) of the N-type fourth doped region 24. As for the method of forming the high voltage device of the present invention, the step of forming the N-type fifth doped region 25 is before the step of forming the gate 20, as shown in FIGS. 5(b) and 5(c); therefore, the channel of the gate 20 is efficiently controlled to achieve the electrical characteristics predetermined when designing the high voltage device 2.

FIG. 6( a) is a characteristic curve diagram of I_ds and VDS of the high voltage device 2 according to the present invention under different gate voltages (VG), wherein the curves C1-C7 are I_ds-VDS characteristic curves when the gate voltage (VG) is 0 V, 2 V, 4 V, 6 V, 8 V, 10 V, and 12 V, respectively. Compared with FIG. 3(a), it can be known that I_ds in the curves C6 and C7 in FIG. 6(a) is not obviously increased when VDS is larger than 12 V. FIG. 6(b) is a characteristic curve diagram of the substrate current I_sub and the gate voltage (VG) of the high voltage device 2 in FIG. 4 under different VDS, wherein the curves D1-D6 are I_sub-VG characteristic curves when the VDS is 0 V, 16 V, 17 V, 18 V, 19 V, and 20 V, respectively. Compared with the curves B1-B6 in FIG. 3(b), the curves D1-D6 in FIG. 6(b) only have one hump, i.e., no substrate current I_sub is generated after VG is larger than 7 V. It should be noted that the data in FIGS. 6(a) and 6(b) is measured by using a HVMOS transistor having a gate length of 1.8 μm and a gate width of 50 μm.

FIG. 7 is a characteristic curve diagram of the substrate current I_sub and VDS when the high voltage device is turned off (VG=0 V), wherein the curves E and F represent the characteristic curves of the substrate current I_sub and VDS of the high voltage device 2 of the present invention and the conventional HVNMOS transistor 1, respectively. It can be known from FIG. 7 that when the high voltage device of the present invention is under VDS larger than 12 V, it nearly causes the substrate current I_sub not to increase. Even though VDS is increased to be 24 V, the substrate current I_sub is merely increased to be 80 nA. However, when the conventional HVNMOS transistor 1 is under VDS larger than 12 V, the substrate current I_sub is obviously increased, and when VDS is increased to be 24 V, the substrate current I_sub is greatly increased to 480 nA.

In view of the above, compared with the conventional high voltage device, the high voltage device provided by the present invention has the following advantages. When being turned off (VG=0 V), the high voltage device may bear high VDS and generate a tiny leakage current (or substrate current), and the substrate current does not cause a double hump, as shown in FIGS. 3(b) and 6(b). Under high voltage operation (VG is larger than 8 V), the high voltage device does not cause a high substrate current and has a flat saturation current I_ds, as shown in FIGS. 3(a) and 6(a). It is mainly because the fifth doped region in the present invention has a preferred coverage on the third doped region, and at the same time, the ion concentration uniformity on the bottom of the third doped region is improved, thus reducing the leakage current efficiently. Furthermore, the method of manufacturing the high voltage device of the present invention does not involve any additional processes or steps and does not increase the number of the photomasks, so as not to increase the cost. Due to the aforementioned advantages of the present invention, when designing the high voltage device, the gate width may be reduced to further reduce the area thereof, and at the same time, the operational voltage and current are increased.

The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.

Claims

1. A high voltage device, comprising: a semiconductor substrate, comprising: a first doped region with a first conductive type;a second doped region with a second conductive type;a third doped region with said second conductive type;a fourth doped region with said second conductive type; anda fifth doped region with said second conductive type and being partially overlapped by said fourth doped region, wherein the overlapped region surrounds said third doped region; anda gate disposed on a surface of said semiconductor substrate between said second doped region and said third doped region so as to control conductivity between said second doped region and said third doped region.

2. The high voltage device of claim 1, wherein length of said fourth doped region is larger than length of said fifth doped region.

3. The high voltage device of claim 1, wherein depth of said fifth doped region is larger than depth of said fourth doped region.

4. The high voltage device of claim 1, wherein the third and fourth doped regions form a double diffusion drain.

5. The high voltage device of claim 1, wherein the fourth and fifth doped regions have the same doping concentration.

6. The high voltage device of claim 1, wherein the second and third doped regions have the same doping concentration.

7. The high voltage device of claim 1, wherein doping concentration is larger for said third doped region than for said fourth doped region.

8. A method of manufacturing a high voltage device, said method comprising the steps of: forming a first doped region with a first conductive type on a semiconductor substrate;forming a fifth doped region with a second conductive type in said first doped region;forming a gate on a surface of said first doped region;forming a fourth doped region with said second conductive type, wherein said fourth doped region is partially overlapped by said fifth doped region; andforming a second doped region the said second conductive type and a third doped region with said second conductive type on both sides of a gate, wherein the said third doped region is surrounded by the overlapped region of the fourth and fifth doped regions.

9. The method of manufacturing a high voltage device of claim 8, wherein the fifth doped region is formed through an ion implantation process and a thermal diffusion process.

10. The method of manufacturing a high voltage device of claim 8, wherein said gate is closed adjacent to said fourth doped region.

11. The method of manufacturing a high voltage device of claim 8, wherein the fourth doped region is formed through a self-aligned ion implantation process by using a gate as a photomask.

12. The method of manufacturing a high voltage device of claim 8, wherein said fourth doped region is longer than said fifth doped region.

13. The method of manufacturing a high voltage device of claim 8, wherein said fourth doped region is shallower than said fifth doped region.

14. The method of manufacturing a high voltage device of claim 8, wherein the third and fourth doped regions form a double diffusion drain.

15. The method of manufacturing a high voltage device of claim 8, wherein the fourth and fifth doped regions have the same doping concentration.

16. The method of manufacturing a high voltage device of claim 8, wherein the second and third doped regions have the same doping concentration.

17. The method of manufacturing a high voltage device of claim 8, wherein doping concentration is larger for said third doped region than for said fourth doped region.