Claims
- 1. An interconnect suitable for use in a semiconductor device, comprising:a first layer of a conductive material forming an ohmic contact with a conductive region through an interconnect hole in an interlayer dielectric overlying the conductive region; a second layer of material comprising oxidized TiN overlying and in ohmic contact with said first layer of material, said second layer of material being more resistive than said first layer of material; and a third layer of a material overlying and in ohmic contact with said second layer of material, said third layer of material being more conductive than said second layer of material.
- 2. The interconnect of claim 1, wherein the second layer of material increases the resistance of said interconnect to from about 10 kΩ to 10 GΩ.
- 3. The interconnect of claim 1, wherein the second layer of material increases the resistance of said interconnect to from about 1 GΩ to 10 GΩ.
- 4. The interconnect of claim 1, wherein said conductive region comprises doped silicon, and said interconnect provides a contact between the doped silicon region and a metal region separated by said interlayer dielectric.
- 5. The interconnect of claim 4, wherein said doped silicon region is a source/drain region of a NMOS transistor.
- 6. The interconnect of claim 1, wherein said conductive region comprises metal, and said interconnect provides a via between the metal region and a second metal region separated by said interlayer dielectric.
- 7. The interconnect of claim 1, wherein said first layer comprises tungsten and said third layer comprises TiN.
- 8. A static random access memory cell formed on a semiconductor substrate, comprising:a first vertically-integrated interconnect formed on said substrate, comprising, a first layer of a conductive material forming an ohmic contact with a conductive region through an interconnect hole in an interlayer dielectric overlying the conductive region, a second layer of material comprising oxidized TiN overlying and in ohmic contact with said first layer of material, said second layer of material being more resistive than said first layer of material, and a third layer of a material overlying and in ohmic contact with said second layer of material, said third layer of material being more conductive than said second layer of material; and a second interconnect in said layer of said static random access memory, said second interconnect having a lower resistance value than said first interconnect.
- 9. The SRAM of claim 8, wherein the second layer of material increases the resistance of said higher resistor value interconnect to from about 10 kΩ to 10 GΩ.
- 10. The SRAM of claim 8, wherein the second layer of material increases the resistance of said higher resistor value interconnect to from about 1 GΩ to 10 GΩ.
- 11. The SRAM of claim 8, wherein said conductive region comprises doped silicon, and said interconnect provides a contact between the doped silicon region and a metal region separated by said interlayer dielectric.
- 12. The SRAM of claim 11, wherein said doped silicon region is a source/drain region of a NMOS pull down transistor.
- 13. The SRAM of claim 8, wherein said first layer comprises tungsten and said third layer comprises TiN.
- 14. The SRAM of claim 8, wherein said SRAM further comprises a VCC bus, a polysilicon gate electrode, and a VSS bus.
- 15. The SRAM of claim 14, wherein said VCC bus is connected to said polysilicon gate electrode via said higher resistor value vertically integrated interconnect, and said VSS bus is connected to said polysilicon gate electrode via said lower resistor value interconnect.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of the filing date of Provisional Application Ser. No. 60/087,108 , entitled HIGHLY RESISTIVE CONTACTS, filed May 28, 1998. This application is related to patent application Ser. No. 09/227,992 filed on Jan. 8, 1999, and entitled METHOD OF FORMING HIGHLY RESISTIVE INTERCONNECTS, and which is now U.S. Pat. No. 6,127,217.
US Referenced Citations (16)
Non-Patent Literature Citations (3)
Entry |
F. Whitwer et al. “Influence of titanium capped aluminum on . . . ” VLSI Multilevel Interconnection Conf. 1988 Ch-2624 p. 484-90.* |
R. Joshi et al. in Applied Phys. Letters Collimated sputtering of Tin/ti liners . . . vol. 61 Nov. 23, 1992.* |
R. Uttecht et al. in VMIC Conference IEEE A four level-metal fully planarized interconnection . . . TH-0359-0/91/0000-0020 Jun. 11-12, 1991. |
Provisional Applications (1)
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Number |
Date |
Country |
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60/087108 |
May 1998 |
US |