Patent Application
20240395873
The invention relates to a III-N silicon semiconductor wafer.
Silicon semiconductor wafers with a nitride layer resting thereon are known from DE 10 2006 030 305 and DE 102 569 11.
From U.S. Pat. No. 2,022,367 188 A1, a method is known for joining two silicon substrate wafers with different crystal orientation and a silicon dioxide intermediate layer, wherein the three layers each have the same diameter. Each upper Si wafer has an orientation of <100>, the lower Si wafer has an orientation of <111>. Each oxide layer has a thickness of more than 1 μm. The object of the method or of the arrangement is to suppress a warping during the production of a nitride layer on the upper Si wafer with a thickness of more than 1.0 μm.
From U.S. Pat. No. 2,007,069 335 A1, a method is known for producing an SOI wafer, wherein the upper silicon layer is designed as an active layer for producing components and has a thickness of less than 10 μm. The object of the method is to reduce the disadvantages caused as a result of the CMP process such as, e.g., the area of the edge region in which the active layer in the edge region has incomplete joining.
A method for rounding the edges of an individual semiconductor wafer is known from CN 1058 142 45 B.
It is therefore an object of the invention to provide a device that advances the state of the art.
According to the subject matter of the invention, a III-N silicon semiconductor wafer is provided, having an upper layer region with a top surface and a lower layer region with a bottom surface.
The upper layer region has a nitride layer with a formed III-N layer. The lower layer region includes a silicon layer or consists of a silicon layer.
The semiconductor wafer has a total thickness of at least 1.2 mm and is disk-shaped in design. In addition, the semiconductor wafer is divided along the total thickness into the upper layer region and the lower layer region. The maximum thickness of the semiconductor wafer is 3 mm.
The upper layer region has a circumferential edge region and a first maximum diameter of at least 145 mm.
The upper layer region has a thickness greater than 30 μm and less than 950 μm. The lower layer region has a second maximum diameter, and a connection region is formed between the upper layer region and the lower layer region.
The connection region has a third diameter, wherein the third diameter is smaller than the first maximum diameter. The third diameter is made smaller than the second maximum diameter or as large as the second maximum diameter.
The first maximum diameter corresponds to the second maximum diameter, or the first maximum diameter is formed differently from the second maximum diameter.
It should be noted that the term “III-N” refers to the column of the Ill-valued elements of the periodic table, such as, in particular, boron, aluminum, gallium, and indium in combination with nitrogen. In other words, in addition to silicon, the semiconductor wafer has, in particular in the nitride layer, at least the element nitrogen in a compound with one of the elements from column III of the periodic table. In particular, the term “III-N” also includes layers such as AlGaN or GaN.
Preferably, a layer including or consisting of GaN is formed at the top surface of the nitride layer.
An advantage of the large thickness of the semiconductor wafer is that the semiconductor wafer formed predominantly of silicon is not or is only slightly deformed in tension or compression during a production of the nitride layer. In other words, the semiconductor wafer formed predominantly of silicon is only slightly or is not warped during production of the nitride layer at the top surface. In one improvement, the bending of the semiconductor wafer is less than 300 μm or less than 100 μm or less than 30 μm.
Another advantage is that, with the large thickness of at least 1.2 mm, preferably two silicon semiconductor wafers of thicknesses that are typically used can be joined in an economical manner in order to achieve the desired total thickness.
The thicknesses of semiconductor wafers that are typically used, also often referred to as SEMI standard thicknesses, are listed in Table 1 as a function of the diameter of the semiconductor wafer. In addition, the minimum thickness according to the invention as a function of the diameter, as well as the typical thicknesses according to the present invention, are listed for purposes of comparison.
It is a matter of course that the diameters listed in Table 1 can have a tolerance, generally of up to +/−200 μm. In addition, it should be noted that the respective tolerances for the diameters can also made larger or smaller. It should also be noted that, in another improvement, the semiconductor wafers also have different diameters, wherein the minimum thickness for all diameters is larger than 1.0 mm, however.
The upper layer region can include a silicon layer or consists of a silicon layer, wherein the nitride layer rests on the silicon layer and forms the top surface of the semiconductor wafer. The upper layer region can include a silicon semiconductor wafer in accordance with the SEMI standard thickness.
The thickness of the upper layer region can be between 100 μm and 900 μm or between 500 μm and 800 μm.
The silicon layer of the upper layer region can have a thickness between 30 μm and 950 μm or between 100 μm and 900 μm or between 500 μm and 800 μm.
The thickness D2 of the lower layer region USB can be greater than 10 μm and less than 950 μm.
The semiconductor wafer can be formed of more than 40% or more than 60% or more than 80% and at most 90% or at most 98% or at most 99% silicon.
The semiconductor wafer can be formed monolithically along the total thickness. In other words, the entire semiconductor wafer is made as a single piece.
The semiconductor wafer can have a bonding surface in the connection region, which is to say in the region between the upper layer region and the lower layer region. In other words, the semiconductor wafer has a two-piece construction. The semiconductor wafer is joined at the bonding surface. It is a matter of course that, in some examples, aids such as adhesive or metal layers or a combination of multiple materials are used in joining.
A semiconductor bond can be formed at the bonding surface. It should be noted that the term semiconductor bond is used synonymously with the term wafer bond. The upper region can be integrally joined directly to the lower region, preferably without the formation of intermediate layers. Intermediate layers are understood in this context as layers that have a different chemical composition from the chemical composition of the two semiconductor wafers that are joined.
The semiconductor bond can include a silicon dioxide layer, wherein the silicon dioxide layer has a thickness between a monolayer and a thickness less than 10 μm or less than 1 μm or less than 100 nm.
The first maximum diameter can differ by at most 10 mm or by at most 2 mm from the second maximum diameter. In an example, the second maximum diameter is at most 5 mm smaller than or at most 2 mm larger than the first maximum diameter.
The first maximum diameter can be the same size as the second maximum diameter or the first maximum diameter corresponds to the second maximum diameter.
The circumferential edge region of the upper layer region may be angular or not angular in design. The circumferential edge region of the upper layer region iscan be rounded or the circumferential edge region of the upper layer region is designed according to the JEITA standard or the SEMI standard.
The lower layer region can have a circumferential, rounded edge region. The lower layer region can have an increasing diameter and/or a decreasing diameter along the thickness D2 of the semiconductor wafer.
The nitride layer can include one layer or multiple III-N and/or metal nitride layers. In particular, single or multiple layers including or consisting of AlGaN, GaN, AlN, InN, and TiN are formed in the nitride layer.
In an example, multiple nitride layers are formed.
The nitride layer can have a thickness of at least 1 μm or of at least 4 μm and at most a thickness of 30 μm. The GaN layer at the top surface of the upper layer region can have a thickness between 0.5 μm and 10 μm or between 1.0 μm and 5 μm.
The upper circumferential edge region may not include a right-angled edge. The upper circumferential edge region and the lower circumferential edge region can each be edge-rounded.
It should be noted that the total thickness GD is formed as a sum of the thickness D1 of the upper layer region and the thickness D2 of the lower layer region and the thickness D3 of the nitride layer.
Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes, combinations, and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus, are not limitive of the present invention, and wherein:
The illustration in
The upper layer region OSB has a silicon layer SIS, wherein the nitride layer NSB rests on the silicon layer SIS and forms the top surface NS. The silicon layer SIS of the upper layer region OSB is between 100 μm and 950 μm.
The nitride layer NSB includes at least one III-N and/or one metal nitride layer.
In the depicted example, a thin III-N layer is formed on the surface NS of the nitride layer NSB. Preferably, the III-N layer includes or consists of GaN.
It is a matter of course that the III-N layer is additionally or alternatively formed at a different location on the nitride layer NSB in an example that is not shown.
The nitride layer NSB has a thickness of at least 1 μm or of at least 4 μm and at most a thickness of 30 μm.
The thickness D1 of the upper layer region OSB is less than 950 μm. The thickness D2 of the lower layer region USB is greater than 10 μm and less than 950 μm.
The lower layer region USB includes or consists of a silicon layer SIS.
The semiconductor wafer 10 has a total thickness GD of at least 1.2 mm and is disk-shaped in design. The maximum thickness of the semiconductor wafer 10 is 3 mm.
As explained above, the semiconductor wafer 10 is divided along the total thickness GD into the upper layer region OSB and the lower layer region USB. The upper layer region OSB has a circumferential edge region RB, wherein the upper edge region RB does not have a right-angled edge, but instead has a rounded edge. In addition, the upper layer region OSB has a first maximum diameter DM1 of at least 145 mm.
The lower layer region USB has a second maximum diameter DM2, wherein the lower edge region URB does not have a right-angled edge, but instead has a rounded edge. Formed between the upper layer region OSB and the lower layer region USB is a connection region ASB, wherein the connection region ASB has a third diameter DU. In this case, the first maximum diameter DM1 corresponds to the second maximum diameter DM2.
The third diameter DÜ is made smaller than the first maximum diameter DM1 and smaller than the second maximum diameter DM2.
Between the upper layer region OSB and the lower layer region USB, a semiconductor bond is formed at the connection region ASB.
The first maximum diameter DM1 differs by at most 2 mm from the second maximum diameter DM2. The circumferential edge region RB of the upper layer region OSB preferably is rounded in design or formed in a shape according to the JEITA standard or the SEMI standard.
The lower layer region USB has a circumferential, rounded edge region URB. The lower layer region USB includes silicon, wherein an oxide layer is formed at the bottom surface US in an example.
Shown in the illustration in
The lower layer region USB has a constant diameter DM2 along the thickness D2 starting from the connection region ASB toward the bottom surface US.
Shown in the illustration in
The lower layer region USB has a decreasing diameter DM2 along the thickness D2 starting from the connection region ASB toward the bottom surface US.
Shown in the illustration in
The lower layer region USB has an increasing diameter DM2 along the thickness D2 starting from the connection region ASB toward the bottom surface US.
The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are to be included within the scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2022 000 425.9 | Feb 2022 | DE | national |
This nonprovisional application is a continuation of International Application PCT/EP2022/000113, which was filed on Dec. 19, 2022, and which claims priority to German Patent Application No. 10 2022 000 425.9 which was filed in Germany on Feb. 3, 2022, and which are all herein incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/EP2022/000113 | Dec 2022 | WO |
| Child | 18794638 | US |
