Patent Application
20110169991
This disclosure relates generally to image sensors, and in particular but not exclusively, relates to CMOS image sensors.
Image sensors are widely used in digital still cameras, cellular phones, security cameras, as well as in, medical, automobile, and other applications. Complementary metal-oxide-semiconductor (“CMOS”) technology is used to manufacture lower cost image sensors on silicon substrates. In a large number of image sensors, a photodiode structure called a pinned photodiode is used because of its low noise performance. In these conventional photodiode structures, a P+ type doped layer is ion implanted at or just below the silicon surface adjacent to a transfer gate. An N type doped layer is ion implanted deeper into the P type doped silicon substrate also adjacent to the transfer gate. The N type layer is the buried layer that stores charge away from the surface region where defects typically reside. The purpose of the P+ type doped layer is to passivate the defects on the photodiode surface. The relative location of the edges of the P+ type doped pinning layer, the N type doped photodiode region, and the adjacent transfer gate should be carefully engineered to improve photodiode charge transfer through the transfer gate. This becomes increasingly important as CMOS image sensors (“CIS”) continue to be miniaturized.
As CIS continue to miniaturize, the area of their pixels and principally their photodiode regions shrink, which results in less capacity to intercept light and hold photogenerated charge. Additionally, as backside illuminated (“BSI”) image sensors are introduced their thinned substrates put further constraints on photogenerated charge especially for longer wavelength light, which can pass through a silicon substrate without being fully absorbed. Although the advance of manufacturing technology facilitates the decrease in minimum allowable CMOS sizes, the reduction of variability of shape placement (i.e. alignment tolerance) has progressed at a slower rate. Image lag often depends on consistent alignment tolerances between the N type doped photodiode and its adjacent transfer gate edge.
Exemplary embodiments are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.
Embodiments of a pixel, an image sensor, an imaging system, and methods of fabrication of a pixel, image sensor, and imaging system having improved image lag, noise, and long wavelength sensitivity characteristics are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects. For example, although not illustrated, it should be appreciated that image sensor pixels may include a number of material layers disposed on the front side or backside (e.g., pixel circuitry, dielectric layers, metal stacks, color filters, microlenses, etc.), as well as other conventional layers (e.g., antireflective films, etc.) used for fabricating CIS pixels. Furthermore, the illustrated cross sections of image sensor pixels illustrated herein do not necessarily illustrate the pixel circuitry associated with each pixel. However, it should be appreciated that each pixel may include pixel circuitry coupled to its collection region for performing a variety of functions, such as commencing image acquisition, resetting accumulated image charge, transferring out acquired image data, or otherwise.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
For a front side illuminated image sensor the metal layers (e.g., metal layer 160 and 165) may be patterned in such a manner as to create an optical passage through which light incident on the front side of CIS pixel 100 can reach PD region 130. To implement a color CIS, the front side of CIS pixel 100 further includes a color filter layer 170 disposed under a microlens 175. Microlens 175 aids in focusing the light onto PD region 130. For a back side illuminated image sensor the light is incident on the backside and accordingly the color filter and microlens are positioned over the backside.
In operation, during an integration period (also referred to as an exposure or accumulation period), PD region 130 stores a level of charge proportional to the light intensity at its location in the array. After the integration period, transfer gate 120 is turned on to transfer the charge held in PD region 130 to floating diode 145. After the signal has been transferred to floating diffusion 145, transfer gate 120 is turned off again in preparation for a subsequent integration period. The signal on floating diffusion 145 may then be used to modulate an amplification or source follower transistor (not shown).
As illustrated in
Following the PD removal etch, as show in
In one embodiment, a Silicon Germanium alloy may be used for fabricating PD region 230. Silicon Germanium is effective in absorbing near infrared photons. The energy band gap of silicon is reduced as it is alloyed with increasing amounts of germanium, substantially increasing the absorption coefficients, especially at longer wavelengths. By using a Silicon Germanium alloy the absorption coefficients in the visible spectrum are also increased. The Silicon Germanium alloy may be doped as it is being grown by the addition of well known dopant sources for P or N type dopants during the growth process. The doping profile, i.e. its concentration as a function of growth thickness, may be controlled and varied.
Following formation of the self-aligned epitaxial grown PD region 230, pinning layer 235 is formed over the surface of PD region 230, as shown in
It can be appreciated by those of ordinary skill of the art that other methods may be utilized for forming an epitaxy photodiode. Thus, the present application contemplates and is meant to encompass all methods of forming such an epitaxy diode. Embodiments of epitaxially self-aligned photodiode pixel 200 provide significant benefits over past implementations. Firstly, the required overlap of PD region 230 and transfer gate 120 (e.g., extension region 236) is formed in a repeatable and compact way which allows further miniaturization of image sensor pixels. Secondly, the overlap is formed without the use of angled ion implants which may leave residual defects causing increased dark current and degrade transfer poly gate oxide integrity. Thirdly, the epitaxially grown PD region 230 may be formed with a silicon germanium alloy which has increased photon absorption properties and may extend the image sensor range further into the infrared spectrum while increasing absorption in the visible spectrum. Fourthly, the epitaxially grown PD region may be formed to extend above the original substrate surface to provide a thicker PD region to further enhance the absorption of longer wavelength radiation.
In the disclosed embodiment, substrate 105 may be P type doped, epi layer 104 may be P type doped, doped wells 140 and 141 may be P type doped, floating diffusion 145 may be N type doped, PD region 230 may be N type doped, pinning layer 235 may be P type doped, and transfer gate 120 may be N type doped. It should be appreciated that the conductivity types of all the elements can be swapped such that, for example, substrate 105 may be N+ doped, epi layer 104 may be N− doped, well regions 140 and 141 may be N doped, and PD region 230 may be P doped.
After each pixel has acquired its image data or image charge, the image data is readout by readout circuitry 410 and transferred to function logic 415. Readout circuitry 410 may include amplification circuitry, analog-to-digital (“ADC”) conversion circuitry, or otherwise. Function logic 415 may simply store the image data or even manipulate the image data by applying post image effects (e.g., crop, rotate, remove red eye, adjust brightness, adjust contrast, or otherwise). In one embodiment, readout circuitry 410 may readout a row of image data at a time along readout column lines (illustrated) or may readout the image data using a variety of other techniques (not illustrated), such as a column/row readout, a serial readout, or a full parallel readout of all pixels simultaneously. Control circuitry 420 is connected with pixel array 405 to control operational characteristic of pixel array 405. For example, control circuitry 420 may generate a shutter signal for controlling image acquisition.
In
Reset transistor T2 is coupled between a power rail VDD and the floating diffusion node FD to reset the pixel (e.g., discharge or charge the FD and the PD to a preset voltage) under control of a reset signal RST. The floating diffusion node FD is coupled to control the gate of SF transistor T3. SF transistor T3 is coupled between the power rail VDD and select transistor T4. SF transistor T3 operates as a source-follower providing a high impedance connection to the floating diffusion FD. Finally, select transistor T4 selectively couples the output of pixel circuitry 500 to the readout column line under control of a select signal SEL.
The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the embodiments to the precise forms disclosed. While specific embodiments are described herein for illustrative purposes, various modifications are possible within the scope, as those skilled in the relevant art will recognize. These modifications can be made in light of the above detailed description. Examples of some such modifications include dopant concentration, layer thicknesses, and the like. Further, although the embodiments illustrated herein refer to CMOS sensors using frontside illumination, it will be appreciated that they may also be applicable to CMOS sensors using backside illumination.
The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation.
