Patent Application
20230411422
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0075716, filed on Jun. 21, 2022, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference.
The present inventive concepts relate to image sensors.
An image sensor is a semiconductor device for converting an optical image into electrical signals. Image sensors may be categorized as any one of charge coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. CIS is short for the CMOS image sensor. The CIS may include a plurality of pixels two-dimensionally arranged. Each of the pixels may include a photodiode (PD). The photodiode may convert incident light into an electrical signal.
Some example embodiments of the inventive concepts may provide an image sensor capable of realizing clear (e.g., improved) image quality.
In some example embodiments, an image sensor may include a substrate having a first surface and a second surface opposite to the first surface, the substrate including first to third unit pixels arranged in a first direction, the first direction extending parallel to the second surface of the substrate, a first pixel separation portion in the substrate and between the first unit pixel and the second unit pixel to separate the first and second unit pixels from each other, and a second pixel separation portion in the substrate and between the second unit pixel and the third unit pixel to separate the second and third unit pixels from each other. The first pixel separation portion may include a first conductive pattern, and a first separation insulating pattern covering a sidewall of the first conductive pattern. The second pixel separation portion may include a second conductive pattern, and a second separation insulating pattern covering a sidewall of the second conductive pattern. The first conductive pattern may have a first width in the first direction, and the second conductive pattern may have a second width in the first direction, which is less than the first width.
In some example embodiments, an image sensor may include a substrate having a first surface and a second surface opposite to the first surface, the substrate including first to third unit pixels arranged in a first direction, the first direction extending parallel to the second surface of the substrate, a first pixel separation portion disposed in the substrate and disposed between the first unit pixel and the second unit pixel to separate the first and second unit pixels from each other, and a second pixel separation portion in the substrate and between the second unit pixel and the third unit pixel to separate the second and third unit pixels from each other. The first pixel separation portion may include a first conductive pattern, and a first separation insulating pattern covering a sidewall of the first conductive pattern. The second pixel separation portion may include a second separation insulating pattern and may exclude the first conductive pattern. The first pixel separation portion may have a first width in the first direction, and the second pixel separation portion may have a second width in the first direction, which is less than the first width.
In some example embodiments, an image sensor may include a substrate having a first surface and a second surface opposite to the first surface, the substrate including first to third unit pixels arranged in a first direction, the first direction extending parallel to the second surface of the substrate, a transfer gate on the first surface of the substrate in each of the first to third unit pixels, a first interlayer insulating layer covering the first surface of the substrate, a first pixel separation portion disposed in the substrate and disposed between the first unit pixel and the second unit pixel to separate the first and second unit pixels from each other, a second pixel separation portion disposed in the substrate and disposed between the second unit pixel and the third unit pixel to separate the second and third unit pixels from each other, a first light blocking pattern disposed on the second surface of the substrate and overlapping the first pixel separation portion, and a second light blocking pattern disposed on the second surface of the substrate and overlapping the second pixel separation portion. The first pixel separation portion may include a first conductive pattern, a first separation insulating pattern covering a sidewall of the first conductive pattern, and a first filling insulation pattern between the first conductive pattern and the first interlayer insulating layer. The second pixel separation portion may include a second conductive pattern, a second separation insulating pattern covering a sidewall of the second conductive pattern, and a second filling insulation pattern between the second conductive pattern and the first interlayer insulating layer. The first pixel separation portion may have a first width in the first direction, and the second pixel separation portion may have a second width in the first direction, which is less than the first width. The first light blocking pattern may have a third width in the first direction, and the second light blocking pattern may have a fourth width in the first direction, which is less than the third width.
Hereinafter, to describe the inventive concepts in more detail, some example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings. In this specification, terms indicating an order such as first, and second, are used to distinguish components having the same/similar functions as/to each other, and the first and second may be changed depending on an order in which they are mentioned.
It will be understood that when an element is referred to as being “on” another element, it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present. It will further be understood that when an element is referred to as being “on” another element, it may be above or beneath or adjacent (e.g., horizontally adjacent) to the other element.
It will be understood that elements and/or properties thereof (e.g., structures, surfaces, directions, or the like), which may be referred to as being “perpendicular,” “parallel,” “coplanar,” or the like with regard to other elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) may be “perpendicular,” “parallel,” “coplanar,” or the like or may be “substantially perpendicular,” “substantially parallel,” “substantially coplanar,” respectively, with regard to the other elements and/or properties thereof.
Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially perpendicular” with regard to other elements and/or properties thereof will be understood to be “perpendicular” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “perpendicular,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%).
Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially parallel” with regard to other elements and/or properties thereof will be understood to be “parallel” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “parallel,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%).
Elements and/or properties thereof (e.g., structures, surfaces, directions, or the like) that are “substantially coplanar” with regard to other elements and/or properties thereof will be understood to be “coplanar” with regard to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances and/or have a deviation in magnitude and/or angle from “coplanar,” or the like with regard to the other elements and/or properties thereof that is equal to or less than 10% (e.g., a. tolerance of ±10%)).
It will be understood that elements and/or properties thereof may be recited herein as being “the same” or “equal” as other elements, and it will be further understood that elements and/or properties thereof recited herein as being “identical” to, “the same” as, or “equal” to other elements may be “identical” to, “the same” as, or “equal” to or “substantially identical” to, “substantially the same” as or “substantially equal” to the other elements and/or properties thereof. Elements and/or properties thereof that are “substantially identical” to, “substantially the same” as or “substantially equal” to other elements and/or properties thereof will be understood to include elements and/or properties thereof that are identical to, the same as, or equal to the other elements and/or properties thereof within manufacturing tolerances and/or material tolerances. Elements and/or properties thereof that are identical or substantially identical to and/or the same or substantially the same as other elements and/or properties thereof may be structurally the same or substantially the same, functionally the same or substantially the same, and/or compositionally the same or substantially the same.
It will be understood that elements and/or properties thereof described herein as being “substantially” the same and/or identical encompasses elements and/or properties thereof that have a relative difference in magnitude that is equal to or less than 10%. Further, regardless of whether elements and/or properties thereof are modified as “substantially,” it will be understood that these elements and/or properties thereof should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated elements and/or properties thereof.
When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value include a tolerance of ±10% around the stated numerical value. When ranges are specified, the range includes all values therebetween such as increments of 0.1%.
While the term “same,” “equal” or “identical” may be used in description of some example embodiments, it should be understood that some imprecisions may exist. Thus, when one element is referred to as being the same as another element, it should be understood that an element or a value is the same as another element within a desired manufacturing or operational tolerance range (e.g., ±10%).
When the terms “about” or “substantially” are used in this specification in connection with a numerical value, it is intended that the associated numerical value includes a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical value. Moreover, when the words “about” and “substantially” are used in connection with geometric shapes, it is intended that precision of the geometric shape is not required but that latitude for the shape is within the scope of the disclosure. Further, regardless of whether numerical values or shapes are modified as “about” or “substantially,” it will be understood that these values and shapes should be construed as including a manufacturing or operational tolerance (e.g., ±10%) around the stated numerical values or shapes. When ranges are specified, the range includes all values therebetween such as increments of 0.1%.
As described herein, when an operation is described to be performed, or an effect such as a structure is described to be established “by” or “through” performing additional operations, it will be understood that the operation may be performed and/or the effect/structure may be established “based on” the additional operations, which may include performing said additional operations alone or in combination with other further additional operations.
As described herein, an element that is described to be “spaced apart” from another element, in general and/or in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and/or described to be “separated from” the other element, may be understood to be isolated from direct contact with the other element, in general and/or in the particular direction (e.g., isolated from direct contact with the other element in a vertical direction, isolated from direct contact with the other element in a lateral or horizontal direction, etc.). Similarly, elements that are described to be “spaced apart” from each other, in general and/or in a particular direction (e.g., vertically spaced apart, laterally spaced apart, etc.) and/or are described to be “separated” from each other, may be understood to be isolated from direct contact with each other, in general and/or in the particular direction (e.g., isolated from direct contact with each other in a vertical direction, isolated from direct contact with each other in a lateral or horizontal direction, etc.). Similarly, a structure described herein to be between two other structures to separate the two other structures from each other may be understood to be configured to isolate the two other structures from direct contact with each other.
Referring to
The active pixel sensor array 1001 may include a plurality of unit pixels two-dimensionally arranged and may convert optical signals into electrical signals. The active pixel sensor array 1001 may be driven by a plurality of driving signals (e.g., a pixel selection signal, a reset signal, and a charge transfer signal) provided from the row driver 1003. In addition, the converted electrical signals may be provided to the correlated double sampler 1006.
The row driver 1003 may provide a plurality of driving signals for driving a plurality of the unit pixels to the active pixel sensor array 1001 in response to signals decoded in the row decoder 1002. When the unit pixels are arranged in a matrix form, the driving signals may be provided in the unit of row of the matrix.
The timing generator 1005 may provide timing signals and control signals to the row decoder 1002 and the column decoder 1004.
The correlated double sampler 1006 may receive electrical signals generated from the active pixel sensor array 1001 and may hold and sample the received electrical signals. The correlated double sampler 1006 may doubly sample a specific noise level and a signal level of the electrical signal to output a difference level corresponding to a difference between the noise level and the signal level.
The analog-to-digital converter 1007 may convert an analog signal, which corresponds to the difference level outputted from the correlated double sampler 1006, into a digital signal and may output the digital signal.
The I/O buffer 1008 may latch the digital signals, and the latched signals may be sequentially outputted to an image signal processing unit (not shown) in response to signals decoded in the column decoder 1004.
As described herein, any devices, electronic devices, modules, units, circuits, and/or portions thereof according to any of the example embodiments, and/or any portions thereof (including, without limitation, the image sensor shown in
Any of the memories described herein may be a non-transitory computer readable medium and may store a program of instructions. Any of the memories described herein may be a nonvolatile memory, such as a flash memory, a phase-change random access memory (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), or a ferro-electric RAM (FRAM), or a volatile memory, such as a static RAM (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM).
Referring to
The photoelectric conversion portion PD may generate and accumulate photocharges in proportion to the amount of light incident from the outside. The photoelectric conversion portion PD may include a photodiode, a photo transistor, a photo gate, a pinned photodiode, or a combination thereof. The transfer transistor TX may transfer charges generated in the photoelectric conversion portion PD to the floating diffusion region FD. The floating diffusion region FD may receive the charges generated in the photoelectric conversion portion PD and may cumulatively store the received charges. The source follower transistor DX may be controlled according to the amount of the photocharges accumulated in the floating diffusion region FD.
The reset transistor RX may periodically reset the charges accumulated in the floating diffusion region FD. A drain electrode of the reset transistor RX may be connected to the floating diffusion region FD, and a source electrode of the reset transistor RX may be connected to a power voltage VDD. When the reset transistor RX is turned-on, the power voltage VDD connected to the source electrode of the reset transistor RX may be applied to the floating diffusion region FD. Thus, when the reset transistor RX is turned-on, the charges accumulated in the floating diffusion region FD may be discharged to reset the floating diffusion region FD.
The source follower transistor DX including a source follower gate electrode SF may function as a source follower buffer amplifier. The source follower transistor DX may amplify a potential change in the floating diffusion region FD and may output the amplified potential change to an output line VOUT.
The selection transistor SX including a selection gate electrode SEL may select the unit pixels UP to be sensed in the unit of row. When the selection transistor SX is turned-on, the power voltage VDD may be applied to a drain electrode of the source follower transistor DX.
Referring to
Pixel separation portions DTI1 and DTI2 may be disposed in the first substrate 1 (e.g., at least partially or entirely within an interior of the first substrate 1 between the first and second surfaces 1a and 1b of the first substrate 1) to separate/define (e.g., isolate) the unit pixels UP from each other (e.g., isolate separate unit pixels UP from direct contact with each other in the first direction X and/or the second direction Y) in the pixel array region APS. As shown in at least
As shown, the first direction X may be understood to extend parallel to (e.g., extend in parallel with) at least one of die first surface 1a or the second surface 1b of the first substrate 1 and in some example embodiments may be referred to as extending parallel to the first substrate 1 based on extending parallel to at least one of the first surface 1a or the second surface 1b of the first substrate 1. As further shows, the second direction Y may be understood to extend parallel to (e.g., extend in parallel with) at least one of the first surface 1a or the second surface 1b of the first substrate 1 (in addition to intersecting the first direction X, which may include extending perpendicular to the first direction X), and in some example embodiments be referred to as extending parallel to the first substrate 1 based on extending parallel to at least one of the first surface 1a or the second surface 1b of the first substrate 1.
The pixel separation portions DTI1. and DTI2 may include first and second pixel separation portions DTI1. and DTI2. The first pixel separation portions DTI1. may surround each of the first to fourth pixel groups GP(1) to GP(4) when viewed in a plan view. For example, the first pixel separation portions DTI1. may partially or completely surround each of the first to fourth pixel groups GP(1) to GP(4) in a horizontal plane that extends in the first and second directions X and Y (e.g., in an XY plane). The first pixel separation portions DTI1. may have a mesh shape when viewed in a plan view. For example, as illustrated in
The second pixel separation portions DTI2 may protrude from sidewalls of the first pixel separation portions DTI1 and may be disposed between the first to fourth unit pixels UP(1) to UP(4) of a given pixel group GP. The second pixel separation portions DTI2 may have a cross shape when viewed in a plan view.
A photoelectric conversion portion PD may be disposed in the first substrate 1 of each of the unit pixels UP. The photoelectric conversion portions PD may be doped with dopants having a second conductivity type opposite to the first conductivity type. For example, the second conductivity type may be an N-type. The N-type dopants included in the photoelectric conversion portion PD may form a PN junction with the P-type dopants included in the first substrate 1 around the photoelectric conversion portion PD, and thus a photodiode may be provided.
Device separation portions STI adjacent to the first surface 1a may be disposed in the first substrate 1. The first and second pixel separation portions DTI1 and DTI2 may penetrate the device separation portions STI. The device separation portion STI may define active regions ACT adjacent to the first surface 1a in each of the unit pixels UP. The active regions ACT may be provided for the transistors TX, RX, DX and SX of
A transfer gate TG may be disposed on the first surface 1a of the first substrate 1 of each of the unit pixels UP. A portion of the transfer gate TG may extend into the first substrate 1. The transfer gate TG may be a vertical type gate. In some example embodiments, the transfer gate TG may not extend into the first substrate 1 but may be a planar type gate having a flat shape. A gate insulating layer Gox may be disposed between the transfer gate TG and the first substrate 1. A floating diffusion region FD may be disposed in the first substrate 1 at a side of the transfer gate TG. For example, the floating diffusion region FD may be doped with dopants having the second conductivity type.
The image sensor 500 may be a backside illuminated image sensor. Light may be incident into the first substrate 1 through the second surface 1b of the first substrate 1. Electron-hole pairs (EHPs) may be generated in a depletion region of the PN junction by the incident light. The generated electrons may move into the photoelectric conversion portion PD. When a voltage is applied to the transfer gate TG, the electrons may be moved into the floating diffusion region FD.
In one unit pixel UP(3) or UP(4), a reset gate RG may be disposed on the first surface 1a and may be adjacent to the transfer gate TG. In another unit pixel UP(1) or UP(2), a source follower gate SF and a selection gate SEL may be disposed on the first surface 1a and may be adjacent to the transfer gate TG. The gates TG, RG, SF and SEL may correspond to gates of the transistors TX, RX, DX and SX of
The first surface 1a may be covered with first interlayer insulating layers IL. Each of the first interlayer insulating layers IL may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous low-k dielectric layer. First interconnection lines 15 may be disposed between or in the first interlayer insulating layers IL. The floating diffusion region FD may be connected to a corresponding one of the first interconnection lines 15 through a first contact plug 17. The first contact plug 17 may penetrate a first interlayer insulating layer IL, closest to the first surface 1a, of the first interlayer insulating layers IL in the pixel array region APS.
The first pixel separation portion DTI1 may be located in a first trench 22a formed from the first surface 1a toward the second surface 1b (e.g., at least partially defined by one or more inner surfaces of the first substrate 1 which extend from the first surface 1a toward the second surface 1b). The second pixel separation portion DTI2 may be located in a second trench 22b formed from the first surface 1a toward the second surface 1b (e.g., at least partially defined by one or more inner surface of the first substrate which extend from the first surface 1a toward the second surface 1b). In the cross-sectional view of
The first pixel separation portion DTI1 may include a first filling insulation pattern 12a, a first separation insulating pattern 14a, and a first conductive pattern 16a. The first filling insulation pattern 12a may be disposed between (e.g., between in the third direction Z) the first conductive pattern 16a and the first interlayer insulating layer IL. The first separation insulating pattern 14a may be disposed between (e.g., between in the first direction X and/or the second direction Y) the first conductive pattern 16a and the first substrate 1 and between (e.g., between in the first direction X and/or the second direction Y) the first filling insulation pattern 12a and the first substrate 1.
The second pixel separation portion DTI2 may include a second filling insulation pattern 12b, a second separation insulating pattern 14b, and a second conductive pattern 16b. The second filling insulation pattern 12b may be disposed between (e.g., between in the third direction Z) the second conductive pattern 16b and the first interlayer insulating layer IL. The second separation insulating pattern 14b may be disposed between (e.g., between in the first direction X and/or the second direction Y) the second conductive pattern 16b and the first substrate 1 and between (e.g., between in the first direction X and/or the second direction Y) the second filling insulation pattern 12b and the first substrate 1.
In some example embodiments, the first and second pixel separation portions DTI′ and DTI2 may include separate portions of one or more unitary pieces of material, where the second pixel separation portions DTI2 include portions of the one or more unitary pieces of material that are located between at least two unit pixels UP of a given (e.g., same) pixel group GP in the first and/or second directions X and/or Y and where the first pixel separation portions DTI1 include portions of the one or more unitary pieces of material that are located between at least two unit pixels UP of separate (e.g., different) pixel groups GP in the first and/or second directions X and/or Y, where the one or more unitary pieces of material each extend continuously between the first and second pixel separation portions DTI1 and DTI2. For example, the first and second filling insulation patterns 12a and 12b may be separate portions of a filling insulation pattern 12x that is a single unitary piece of material extending continuously at least partially between separate unit pixels UP of pixel groups GP and between separate unit pixels UP of a same pixel group GP, where the first filling insulation pattern 12a is a first portion of the single unitary piece of material of the filling insulation pattern 12x that is located between at least two unit pixels UP of a given (e.g., same) pixel group GP in the first and/or second directions X and/or Y and where the second filling insulation pattern 12b is a second portion of the single unitary piece of material of the filling insulation pattern 12x that is located between at least two unit pixels UP of separate (e.g., different) pixel groups GP in the first and/or second directions X and/or Y). In another example, the first and second separation insulating patterns 14a and 14b may be separate portions of a separation insulating pattern 14x that is a single unitary piece of material extending continuously at least partially between separate unit pixels UP of pixel groups GP and between separate unit pixels UP of a same pixel group GP, where the first separation insulating pattern 14a is a first portion of the single unitary piece of material of the separation insulating pattern 14x that is located between at least two unit pixels UP of a given (e.g., same) pixel group GP in the first and/or second directions X and/or Y and where the second separation insulating pattern 14b is a second portion of the single unitary piece of material of the separation insulating pattern 14x that is located between at least two unit pixels UP of separate (e.g., different) pixel groups GP in the first and/or second directions X and/or Y). In another example, the first and second conductive patterns 16a and 16b may be separate portions of a conductive pattern 16x that is a single unitary piece of material extending continuously at least partially between separate unit pixels UP of pixel groups GP and between separate unit pixels UP of a same pixel group GP, where the first conductive pattern 16a is a first portion of the single unitary piece of material of the conductive pattern 16x that is located between at least two unit pixels UP of a given (e.g., same) pixel group GP in the first and/or second directions X and/or Y and where the second conductive pattern 16b is a second portion of the single unitary piece of material of the conductive pattern 16x that is located between at least two unit pixels UP of separate (e.g., different) pixel groups GP in the first and/or second directions X and/or Y).
For example, referring to
In some example embodiments, the first and second filling insulation patterns 12a and 12b may be included in separate, respective (e.g., different) pieces of material. In some example embodiments, the first and second separation insulating patterns 14a and 14b may be included in separate, respective (e.g., different) pieces of material. In some example embodiments, the first and second conductive patterns 16a and 16b may be included in separate, respective (e.g., different) pieces of material.
The first filling insulation pattern 12a, the first separation insulating pattern 14a, the second filling insulation pattern 12b and the second separation insulating pattern 14b may each be formed of (e.g., may each at least partially comprise) an insulating material having a refractive index different from that of the first substrate 1. For example, the first filling insulation pattern 12a, the first separation insulating pattern 14a, the second filling insulation pattern 12b and the second separation insulating pattern 14b may each include silicon oxide. The first conductive pattern 16a and the second conductive pattern 16b may be spaced apart from (e.g., isolated from direct contact with) the first substrate 1. The first conductive pattern 16a and the second conductive pattern 16b may each include a poly-silicon layer or silicon-germanium layer, which is doped with dopants. The dopants doped in the poly-silicon layer or silicon-germanium layer may be, for example, boron, phosphorus, or arsenic. In some example embodiments, the first conductive pattern 16a and the second conductive pattern 16b (e.g., the conductive pattern 16x) may include a metal layer.
In the cross-sectional view of
The first conductive pattern 16a may have a third width W3 in the first direction X. The second conductive pattern 16b may have a fourth width W4 in the first direction X. The fourth width W4 may be smaller than the third width W3. In a case in which the first conductive pattern 16a and the second conductive pattern 16b are formed of poly-silicon, the poly-silicon may absorb light. In some example embodiments of the inventive concepts, the second conductive pattern 16b having the fourth width W4 which is relatively small may be disposed between the first to fourth unit pixels UP(1) to UP(4) constituting one pixel group GP to prevent/minimize/reduce absorption of incident light in the one pixel group GP. Thus, the amount of light received in the image sensor may be increased, quantum efficiency (QE) may be increased, and photosensitivity may be improved, thereby improving the image-sensing performance of the image sensor 500. In addition as a result, an auto-focus function may be improved, thereby improving the image-sensing performance of the image sensor 500. As a result, clear image quality of the image sensor may be realized, thereby improving the image-sensing performance of the image sensor 500.
The first filling insulation pattern 12a may have the third width W3 in the first direction X. The second filling insulation pattern 12b may have the fourth width W4 in the first direction X.
In the plan view of
As shown, the third direction Z may be understood to extend perpendicular to at least one of the first surface 1a or the second surface 1b of the first substrate and in some example embodiments ma be referred to as extending perpendicular to the first substrate 1 based on extending perpendicular to at least one of the first surface 1a or the second surface 1b of the first substrate 1. Accordingly, the third direction Z may be referred to interchangeably as a vertical direction. As further noted above, the third direction Z may understood to extend perpendicular to one or both of the first direction X and/or the second direction Y.
A first fixed charge layer 24 may be disposed on the second surface 1b of the first substrate 1. The first fixed charge layer 24 may be in contact with the second surface 1b of the first substrate 1. The first fixed charge layer 24 may be formed of a single layer or multi-layer including at least one of a metal oxide layer containing insufficient oxygen in terms of a stoichiometric ratio or a metal fluoride layer containing insufficient fluorine in terms of a stoichiometric ratio. Thus, the first fixed charge layer 24 may have negative fixed charges. The first fixed charge layer 24 may be formed of a single layer or multi-layer including a metal oxide layer and/or metal fluoride layer including at least one of hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), titanium (T1), yttrium (Y), or a lanthanoid. For example, the first fixed charge layer 24 may include a hafnium oxide layer and/or an aluminum oxide layer. A dark current and a white spot may be reduced, minimized, or prevented by the first fixed charge layer 24.
A second fixed charge layer 42 and a first protective layer 44 may be sequentially stacked on the first fixed charge layer 24. The second fixed charge layer 42 may include a single layer or multi-layer including at least one of a metal oxide layer or a metal fluoride layer. For example, the second fixed charge layer 42 may include a hafnium oxide layer and/or an aluminum oxide layer. The second fixed charge layer 42 may reinforce the first fixed charge layer 24 or may function as an adhesive layer. For example, the first protective layer 44 may include at least one of PETEOS, SiOC, SiO2, or SiN. The first protective layer 44 may function as an anti-reflection layer and/or a planarization layer.
Referring to
In the pixel array region APS, first and second light blocking patterns 48a and 48b may be disposed on the first protective layer 44. First and second low-refractive patterns 50a and 50b may be disposed on the first and second light blocking patterns 48a and 48b, respectively. The first light blocking pattern 48a and the first low-refractive pattern 50a may overlap with the first pixel separation portion DTI1 and may have the same shape as the first pixel separation portion DTI1 when viewed in a plan view. In other words, the first light blocking pattern 48a and the first low-refractive pattern 50a may surround each of the pixel groups GP(1) to GP(4) when viewed in a plan view. The second light blocking pattern 48b and the second low-refractive pattern 50b may overlap with the second pixel separation portion DTI2 and may have the same shape as the second pixel separation portion DTI2 when viewed in a plan view. The second light blocking pattern 48b and the second low-refractive pattern 50b may be disposed between the first to fourth unit pixels UP(1) to UP(4) in each of the pixel groups GP(1) to GP(4) when viewed in a plan view.
Sidewalls of the first light blocking pattern 48a and the first low-refractive pattern 50a may be aligned with each other. Each of the first light blocking pattern 48a and the first low-refractive pattern 50a may have a fifth width W5 in the first direction X. Sidewalls of the second light blocking pattern 48b and the second low-refractive pattern 50b may be aligned with each other. Each of the second light blocking pattern 48b and the second low-refractive pattern 50b may have a sixth width W6 in the first direction X. The sixth width W6 may be equal to or less than the fifth width W5. When the sixth width W6 is less than the fifth width W5, the amount of light incident into the first to fourth unit pixels UP(1) to UP(4) constituting one pixel group GP may be relatively increased. Thus, the amount of light received in the image sensor may be increased, quantum efficiency (QE) may be increased, and photosensitivity may be improved, thereby improving the image sensing performance of the image sensor 500.
The first light blocking pattern 48a and the second light blocking pattern 48b may have the same material and the same thickness as the first diffusion barrier pattern 48g. The first light blocking pattern 48a and the second light blocking pattern 48b may include, for example, titanium.
The first low-refractive pattern 50a and the second low-refractive pattern 50b may have the same thickness and may include the same organic material. The first low-refractive pattern 50a and the second low-refractive pattern 50b may have a refractive index that is less (e.g., smaller) than that of color filters CF1 and CF2. For example, the first low-refractive pattern 50a and the second low-refractive pattern 50b may have a refractive index of about 1.3 or less (e.g., about 0.01 to about 1.3, about 0.1 to about 1.3, about 0.5 to about 1.3, etc.). The first and second light blocking patterns 48a and 48b and the first and second low-refractive patterns 50a and 50b may reduce, minimize, or prevent cross-talk between the unit pixels UP adjacent to each other.
A second protective layer 56 may be stacked on the first protective layer 44. The second protective layer 56 may conformally cover the first and second light blocking patterns 48a and 48b, the first and second low-refractive patterns 50a and 50b, and the connection contact BCA. In the pixel array region APS, color filters CF1 and CF2 may be disposed between the first and second low-refractive patterns 50a and 50b. Each of the color filters CF1 and CF2 may have (e.g., may be configured to selectively transmit light of) a blue color, a green color, or a red color. In some example embodiments, each of the color filters CF1 and CF2 may have (e.g., may be configured to selectively transmit light of) another color such as a cyan color, a magenta color, or a yellow color.
In some example embodiments, one color filter may be disposed on one pixel group GP. In the image sensor according to some example embodiments, the color filters CF1 and CF2 may be arranged in the form of a 2×2 tetra pattern. In other words, a first color filter CF1 may be disposed on the second pixel group GP(2). A second color filter CF2 may be disposed on the first, third or fourth pixel group GP(1), GP(3) or GP(4).
In the edge region EG, a first optical black pattern CFB may be disposed on the second protective layer 56. For example, the first optical black pattern CFB may include the same material as the blue color filter.
In the pixel array region APS, micro lenses ML may be disposed on the color filters CF1 and CF2. Edges of the micro lenses ML may be in contact with each other and may be connected to each other. In some example embodiments, one micro lens ML may be disposed on one pixel group GP. In other words, the one micro lens ML may cover the first to fourth unit pixels UP(1) to UP(4) adjacent to each other. In the plan view of
In the edge region EG, a lens residual layer MLR may be disposed on the first optical black pattern CFB. The lens residual layer MLR may include the same material as the micro lenses ML. The image sensor 500 may be an auto-focus image sensor.
A negative bias voltage may be applied to the first and second conductive patterns 16a and 16b through the connection contact BCA. The first and second conductive patterns 16a and 16b may function as a common bias line. As a result, it is possible to capture holes existing on a surface of the first substrate 1 which is in contact with the first and second pixel separation portions DTI1 and DTI2, and thus a dark current may be reduced or minimized.
Referring to
In the image sensor 501 of
Referring to
The second pixel separation portion DTI2 may further include a third filling insulation pattern 12p on the third conductive pattern 16p. The third filling insulation pattern 12p may include the same material as the first filling insulation pattern 12a. The third filling insulation pattern 12p may have a rhombus shape when viewed in a plan view. The third filling insulation pattern 12p may have the eighth width W8. Other structures and components may be the same/similar as described with reference to
In the image sensor 502 of
Referring to
A separation insulating layer 14 with a first thickness T1 may be conformally formed on the first surface 1a of the first substrate 1. Thus, the separation insulating layer 14 may have the first thickness T1 in the first and second trenches 22a and 22b. The first thickness T1 may be less than ½ of the second width W2. A conductive layer 16 may be formed on the separation insulating layer 14 to fill the first and second trenches 22a and 22b. The conductive layer 16 may have a third width W3 in the first trench 22a. The conductive layer 16 may have a fourth width W4 in the second trench 22b.
Referring to
Subsequently, other components of
In some example embodiments, in the step of
Poly-silicon of a conductive pattern may absorb light, and thus as the amount of poly-silicon is increased, a loss of incident light may be increased by absorption of poly-silicon to deteriorate sensitivity of an image sensor. If both first and second pixel separation portions are replaced with insulating structures to reduce, minimize, or prevent this, a negative voltage may not be applied to a conductive pattern, and thus it may be difficult to reduce or minimize a dark current.
However, according to some example embodiments of the inventive concepts, the widths of the first and second pixel separation portions DTI1 and DTI2 may be different from each other, and thus the structures/composition ratios of the first and second pixel separation portions DTI1 and DTI2 may be different from each other. In other words, the second pixel separation portion DTI2 overlapping one micro lens may have a small amount of poly-silicon or exclude poly-silicon to improve photosensitivity of the image sensor including same, and the first pixel separation portion DTI1 located at a boundary of the micro lenses may include relatively wide poly-silicon (i.e., the first conductive pattern 16a) to reduce or minimize the dark current by applying a negative voltage thereto, thereby improving image-generating performance of the image sensor.
Referring to
Referring to
Referring to
Referring to
The third unit pixel UP(3) of the first pixel group GP(1) and the fourth unit pixel UP(4) of the second pixel group GP(2) adjacent thereto, which are covered with the super micro lens SML, may be used as auto-focus (AF) pixels for an auto-focus function. Other first to fourth unit pixels UP(1) to UP(4) may be used as image pixels for sensing an image. Other components may be the same/similar as described above.
In some example embodiments, referring to
Referring to
The second sub-chip CH2 may include a second substrate 100, a plurality of transistors TR disposed on the second substrate 100, a second interlayer insulating layer 110 covering the second substrate 100, and second interconnection lines 112 disposed in the second interlayer insulating layer 110. The second interlayer insulating layer 110 may have a single-layered or multi-layered structure including at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a porous insulating layer. The first sub-chip CH1 and the second sub-chip CH2 may be bonded to each other. Thus, a first interlayer insulating layer IL of the first sub-chip CH1 may be in contact with the second interlayer insulating layer 110.
The first sub-chip CH1 may include a first substrate 1 including a pad region PAD, a connection region CNR, an optical black region OB, and a pixel array region APS. The first sub-chip CH1 in the pixel array region APS and a portion of the connection region CNR may have the same/similar structure as described with reference to
Light may not be incident into the first substrate 1 of the optical black region OB. The first and second pixel separation portions DTI1 and DTI2 may extend into the optical black region OB to separate a first black pixel UPO1 and a second black pixel UPO2 from each other. The photoelectric conversion portion PD may be disposed in the first substrate 1 of the first black pixel UPO1. The photoelectric conversion portion PD may not exist in the first substrate 1 of the second black pixel UPO2. A transfer gate TG and a floating diffusion region FD may be disposed in each of the first and second black pixels UPO1 and UPO2. The first black pixel UPO1 may sense the amount of charges generated from the photoelectric conversion portion PD into which light is not incident, and thus the first black pixel UPO1 may provide a first reference charge amount. The first reference charge amount may be used as a relative reference value when the amounts of charges generated from the unit pixels UP are calculated. The second black pixel UPO2 may sense the amount of charges generated in a state in which the photoelectric conversion portion PD does not exist, and thus the second black pixel UPO2 may provide a second reference charge amount. The second reference charge amount may be used as data for removing process noise.
A first fixed charge layer 24, a second fixed charge layer 42, a first protective layer 44 and a second protective layer 56 may extend onto a second surface 1b of the optical black region OB, the connection region CNR and the pad region PAD. The edge region EG described with reference to
In the connection region CNR, a connection contact BCA may penetrate the first protective layer 44, the second fixed charge layer 42, the first fixed charge layer 24 and a portion of the first substrate 1 so as to be in contact with the first conductive pattern 16a of the first pixel separation portion DTI1. The connection contact BCA may be disposed in a third trench 46. The connection contact BCA may include a first diffusion barrier pattern 48g conformally covering an inner sidewall and a bottom surface of the third trench 46, a first metal pattern 52 on the first diffusion barrier pattern 48g, and a second metal pattern 54 filling the third trench 46.
A portion of the first diffusion barrier pattern 48g may extend onto the first protective layer 44 of the optical black region OB to provide a third optical black pattern 48c. A portion of the first metal pattern 52 may extend onto the third optical black pattern 48c of the optical black region OB to provide a second optical black pattern 52a. A second protective layer 56 may cover the second optical black pattern 52a and the connection contact BCA. A first optical black pattern CFB may be located on the second protective layer 56 in the optical black region OB and the connection region CNR.
In the connection region CNR, a first via V1 may be disposed at a side of the connection contact BCA. The first via V1 may be referred to as a back bias stack via. The first via V1 may penetrate the first protective layer 44, the second fixed charge layer 42, the first fixed charge layer 24, the first substrate 1, the first interlayer insulating layers IL and a portion of the second interlayer insulating layer 110 so as to be in contact with both at least one of the first interconnection lines 15 and at least one of the second interconnection lines 112.
The first via V1 may be disposed in a first via hole H1. The first via V1 may include a second diffusion barrier pattern 48d and a first via pattern 52b on the second diffusion barrier pattern 48d. The second diffusion barrier pattern 48d may be connected to the first diffusion barrier pattern 48g. The first via pattern 52b may be connected to the first metal pattern 52. The connection contact BCA may be connected to at least one of the first interconnection lines 15 and at least one of the second interconnection lines 112 through the first via V1.
Each of the second diffusion barrier pattern 48d and the first via pattern 52b may conformally cover an inner surface of the first via hole H1. The second diffusion barrier pattern 48d and the first via pattern 52b may not completely fill the first via hole H1. A first low-refractive index residual layer 50g may fill the first via hole H1. A color filter residual layer CFR may be disposed on the first low-refractive index residual layer 50g.
An external connection pad 62 and a second via V2 which are connected to each other may be disposed in the pad region PAD. The external connection pad 62 may penetrate the first protective layer 44, the second fixed charge layer 42, the first fixed charge layer 24, and a portion of the first substrate 1. The external connection pad 62 may be disposed in a fourth trench 60. The external connection pad 62 may include a third diffusion barrier pattern 48e and a first pad pattern 52c which sequentially and conformally cover an inner sidewall and a bottom surface of the fourth trench 60, and a second pad pattern 54a filling the fourth trench 60.
The second via V2 may penetrate the first protective layer 44, the second fixed charge layer 42, the first fixed charge layer 24, the first substrate 1, the first interlayer insulating layers IL and a portion of the second interlayer insulating layer 110 so as to be in contact with at least one of the second interconnection lines 112. The external connection pad 62 may be connected to at least one of the second interconnection lines 112 through the second via V2. The second via V2 may be disposed in a second via hole H2. The second via V2 may include a fourth diffusion barrier pattern 48f and a second via pattern 52d which sequentially and conformally cover an inner sidewall and a bottom surface of the second via hole H2. The fourth diffusion barrier pattern 48f and the second via pattern 52d may not completely fill the second via hole H2. A second low-refractive index residual layer 50c may fill the second via hole H2. A color filter residual layer CFR may be disposed on the second low-refractive index residual layer 50c.
The first and second light blocking patterns 48a and 48b, the first diffusion barrier pattern 48g, the third optical black pattern 48c and the second to fourth diffusion barrier patterns 48d to 48f may have the same thickness and the same material (e.g., titanium). The first metal pattern 52, the second optical black pattern 52a, the first via pattern 52b, the first pad pattern 52c and the second via pattern 52d may have the same thickness and the same material (e.g., tungsten). The second metal pattern 54 and the second pad pattern 54a may have the same material (e.g., aluminum).
The first and second low-refractive patterns 50a and 50b, the first low-refractive index residual layer 50g and the second low-refractive index residual layer 50c may have the same material. The color filter residual layer CFR may have the same color and material as one of the color filters CF1 and CF2.
The second protective layer 56 may extend into the pad region PAD and may have an opening exposing the second pad pattern 54a. A lens residual layer MLR may cover the optical black region OB, the connection region CNR and the pad region PAD. The lens residual layer MLR may have (e.g., may include one or more inner surfaces at least partially defining) an opening 35 exposing the second pad pattern 54a in the pad region PAD.
Referring to
The second sub-chip CH2 may include a second substrate 200; selection gates SEL, source follower gates SF and reset gates (not shown) which are disposed on the second substrate 200; and second interlayer insulating layers IL2 covering them. A second device separation portion STI2 may be disposed in the second substrate 200 to define active regions. Second contacts 217 and second interconnection lines 215 may be disposed in the second interlayer insulating layers IL2. A second conductive pad CP2 may be disposed in an uppermost second interlayer insulating layer IL2. The second conductive pad CP2 may include copper. The second conductive pad CP2 may be in contact with the first conductive pad CP1. The source follower gates SF may be connected to floating diffusion regions FD of the first sub-chip CH1, respectively.
The third sub-chip CH3 may include a third substrate 300, peripheral transistors PTR disposed on the third substrate 300, and third interlayer insulating layers IL3 covering the peripheral transistors PTR. A third device separation portion STI3 may be disposed in the third substrate 300 to define active regions. Third contacts 317 and third interconnection lines 315 may be disposed in the third interlayer insulating layers IL3. An uppermost third interlayer insulating layer IL3 may be in contact with the second substrate 200. A through-electrode TSV may penetrate the second interlayer insulating layer IL2, the second device separation portion STI2, the second substrate 200 and the third interlayer insulating layer IL3 to connect the second interconnection line 215 to the third interconnection line 315. A sidewall of the through-electrode TSV may be surrounded by a via insulating layer TVL. The third sub-chip CH3 may include circuits for driving the first sub-chip CH1 and/or the second sub-chip CH2 and/or for storing electrical signals generated from the first sub-chip CH1 and/or the second sub-chip CH2.
Referring to
Each of the first pixel separation portion DTI1 and the first trench 22a may have a first width W1 in the first direction X. Each of the second pixel separation portion DTI2 and the second trench 22b may have a second width W2 in the first direction X. The second width W2 may be less than the first width W1. The sixth width W6 may be equal to or different from the second width W2. The sixth width W6 may be greater than the second width W2. Other structures and components may be the same as described with reference to
Referring to
Referring to
In the image sensor according to some example embodiments of the inventive concepts, the second pixel separation portion between the unit pixels constituting each of the pixel groups may include the conductive pattern of which the amount of poly-silicon (capable of absorbing light) is less than that (e.g., the amount of poly-silicon) of the first pixel separation portion between the pixel groups or may exclude the conductive pattern, and thus it is possible to reduce, minimize, or prevent a loss of incident light absorbed in poly-silicon (e.g., in a given pixel group that includes the unit pixels and the second pixel separation portion between at least two unit pixels of the given pixel group). As a result, the amount of received light and photosensitivity of the image sensor may be increased to realize clear image quality, thereby improving the image-generation performance of the image sensor. In addition, the second pixel separation portion provided between the unit pixels may have a relatively narrow width, and thus a total size of the image sensor may be reduced to increase an integration density of the image sensor.
In the image sensor according to some example embodiments of the inventive concepts, the width of the second light blocking pattern disposed on the second pixel separation portion between the unit pixels constituting each of the pixel groups may be less than the width of the first light blocking pattern disposed on the first pixel separation portion between the pixel groups, and thus it is possible to relatively increase the amount of light incident to the unit pixels constituting each of the pixel groups. As a result, the amount of light received in the image sensor may be increased to realize the clear image quality, thereby improving the image-generation performance of the image sensor.
While some example embodiments of the inventive concepts have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims. Features of image sensors according to various example embodiments, including the example embodiments shown in
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0075716 | Jun 2022 | KR | national |
