Patent Grant
10692699
Variable capacitors are used in many applications, such as matching networks and variable filters. They allow for the precise tuning, after assembly, of frequency and/or impedance in applications needing a dynamic system response, such as in plasma processes. The ability to dynamically change impedance and frequency response provides more flexibility for the applications variable capacitors are used in, and can compensate for variations from unit-to-unit. Some examples of variable capacitors are vacuum variable capacitors (VVCs) and electronically variable capacitors (EVCs).
In electronic circuits, matching networks are used to match the source impedance to the load impedance and vice versa. That is, the source, being of some impedance with a resistive part and a reactive part, will be terminated into the complex conjugate impedance, and the load impedance will be driven by the complex conjugate of its impedance. The complex conjugate is used to eliminate the reactive part of the impedance, leaving only the resistive part, and the resistive part is made equal. This is done so that maximum power transfer can be achieved at the load.
In plasma applications, the load impedance can vary depending on several factors, such as time, power level, pressure, gas flow, chemistry of the gasses, and whether the plasma has been struck. Accordingly, the matching network must be able to automatically vary itself to ensure that the maximum power transfer is achieved. This helps with repeatability in both the depositing and etching.
EVCs use switches to add or remove fixed capacitors, such as an MLCC (multi-layer ceramic capacitor), in a circuit. The capacitor and switch are placed in series. This circuit is then placed in parallel with other capacitor/switch circuits. The parallel circuits allow the capacitors to be simply added or subtracted in the circuit, depending on how many switches are opened or closed. In the case where all the switches are open, the EVC will be at its lowest capacitance value. In the case where they are all closed, the EVC will be at its highest capacitance value.
There are different approaches for arranging and choosing the capacitors of the EVC such that the EVC can provide progressively increasing capacitance values. There is need for an arrangement of capacitors for an EVC that provides the needed capacitance values while avoiding overlap in solutions, and while using a lower number of capacitors, switches, and associated hardware, and thus taking up less space.
In one aspect, an impedance matching network includes an input configured to operably couple to a radio frequency (RF) source; an output configured to operably couple to a plasma chamber for manufacturing a semiconductor; a variable capacitor comprising a plurality of capacitors operably coupled in parallel, the plurality of capacitors comprising coarse capacitors comprising (a) first coarse capacitors each having a substantially similar first coarse capacitance; and (b) second coarse capacitors each having a substantially similar second coarse capacitance; and fine capacitors having different capacitances that increase in value, wherein at least one of the fine capacitors has a capacitance greater than the first coarse capacitance; a plurality of switches, wherein each switch of the plurality of switches is operably coupled in series with a corresponding capacitor of the plurality of capacitors and configured to switch in and out the corresponding capacitor; wherein each capacitor of the plurality of capacitors provides a change to a total capacitance of the variable capacitor when the capacitor is switched in; a control circuit operably coupled to the variable capacitor, the control circuit configured to (a) determine which of the coarse capacitors and the fine capacitors to have switched in to achieve an impedance match and (b) cause the determined coarse and fine capacitors to be switched in; wherein the control circuit is further configured to cause a gradual increase in the total capacitance of the variable capacitor by switching in, in a predetermined order, each of the first coarse capacitors, followed by each of the second coarse capacitors; and only switching in the fine capacitors whose capacitance is less than a capacitance of a next coarse capacitor of the coarse capacitors predetermined to be switched in next.
In another aspect, a method of matching an impedance includes operably coupling an input of a matching network to an RF source; operably coupling an output of the matching network to a plasma chamber for manufacturing a semiconductor, the matching network comprising a variable capacitor comprising a plurality of capacitors operably coupled in parallel, the plurality of capacitors comprising coarse capacitors comprising (a) first coarse capacitors each having a substantially similar first coarse capacitance; and (b) second coarse capacitors each having a substantially similar second coarse capacitance; and fine capacitors having different capacitances that increase in value, wherein at least one of the fine capacitors has a capacitance greater than the first coarse capacitance; a plurality of switches, wherein each switch of the plurality of switches is operably coupled in series with a corresponding capacitor of the plurality of capacitors and configured to switch in and out the corresponding capacitor; wherein each capacitor of the plurality of capacitors provides a change to a total capacitance of the variable capacitor when the capacitor is switched in; and a control circuit; determining, by the control circuit, which of the coarse capacitors and the fine capacitors to have switched in to achieve an impedance match; and causing, by the control circuit, the determined coarse and fine capacitors to be switched in; wherein the control circuit is further configured to cause a gradual increase in the total capacitance of the variable capacitor by switching in, in a predetermined order, each of the first coarse capacitors, followed by each of the second coarse capacitors; and only switching in the fine capacitors whose capacitance is less than a capacitance of a next coarse capacitor of the coarse capacitors predetermined to be switched in next.
In another aspect, a method of manufacturing a semiconductor includes operably coupling an input of a matching network to an RF source; operably coupling an output of the matching network to a plasma chamber, plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate, the matching network comprising a variable capacitor comprising a plurality of capacitors operably coupled in parallel, the plurality of capacitors comprising coarse capacitors comprising (a) first coarse capacitors each having a substantially similar first coarse capacitance; and (b) second coarse capacitors each having a substantially similar second coarse capacitance; and fine capacitors having different capacitances that increase in value, wherein at least one of the fine capacitors has a capacitance greater than the first coarse capacitance; a plurality of switches, wherein each switch of the plurality of switches is operably coupled in series with a corresponding capacitor of the plurality of capacitors and configured to switch in and out the corresponding capacitor; wherein each capacitor of the plurality of capacitors provides a change to a total capacitance of the variable capacitor when the capacitor is switched in; and a control circuit; placing a substrate in the plasma chamber; energizing plasma within the plasma chamber by coupling RF power from the RF source into the plasma chamber to perform a deposition or etching; and determining, by the control circuit, which of the coarse capacitors and the fine capacitors to have switched in to achieve an impedance match; and causing, by the control circuit, the determined coarse and fine capacitors to be switched in; wherein the control circuit is further configured to cause a gradual increase in the total capacitance of the variable capacitor by switching in, in a predetermined order, each of the first coarse capacitors, followed by each of the second coarse capacitors; and only switching in the fine capacitors whose capacitance is less than a capacitance of a next coarse capacitor of the coarse capacitors predetermined to be switched in next.
In another aspect, a semiconductor processing tool includes a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising an input configured to operably couple to an RF source; an output configured to operably couple to the plasma chamber for manufacturing a semiconductor; a variable capacitor comprising a plurality of capacitors operably coupled in parallel, the plurality of capacitors comprising coarse capacitors comprising (a) first coarse capacitors each having a substantially similar first coarse capacitance; and (b) second coarse capacitors each having a substantially similar second coarse capacitance; and fine capacitors having different capacitances that increase in value, wherein at least one of the fine capacitors has a capacitance greater than the first coarse capacitance; a plurality of switches, wherein each switch of the plurality of switches is operably coupled in series with a corresponding capacitor of the plurality of capacitors and configured to switch in and out the corresponding capacitor; wherein each capacitor of the plurality of capacitors provides a change to a total capacitance of the variable capacitor when the capacitor is switched in; a control circuit operably coupled to the variable capacitor, the control circuit configured to (a) determine which of the coarse capacitors and the fine capacitors to have switched in to achieve an impedance match and (b) cause the determined coarse and fine capacitors to be switched in; wherein the control circuit is further configured to cause a gradual increase in the total capacitance of the variable capacitor by switching in, in a predetermined order, each of the first coarse capacitors, followed by each of the second coarse capacitors; and only switching in the fine capacitors whose capacitance is less than a capacitance of a next coarse capacitor of the coarse capacitors predetermined to be switched in next.
The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:
The following description of the preferred embodiment(s) is merely exemplary in nature and is in no way intended to limit the invention or inventions. The description of illustrative embodiments is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description of the exemplary embodiments disclosed herein, any reference to direction or orientation is merely intended for convenience of description and is not intended in any way to limit the scope of the present invention. The discussion herein describes and illustrates some possible non-limiting combinations of features that may exist alone or in other combinations of features. Furthermore, as used herein, the term “or” is to be interpreted as a logical operator that results in true whenever one or more of its operands are true. Furthermore, as used herein, the phrase “based on” is to be interpreted as meaning “based at least in part on,” and therefore is not limited to an interpretation of “based entirely on.”
Features of the present invention may be implemented in software, hardware, firmware, or combinations thereof. The computer programs described herein are not limited to any particular embodiment, and may be implemented in an operating system, application program, foreground or background processes, driver, or any combination thereof. The computer programs may be executed on a single computer or server processor or multiple computer or server processors.
Processors described herein may be any central processing unit (CPU), microprocessor, micro-controller, computational, or programmable device or circuit configured for executing computer program instructions (e.g., code). Various processors may be embodied in computer and/or server hardware of any suitable type (e.g., desktop, laptop, notebook, tablets, cellular phones, etc.) and may include all the usual ancillary components necessary to form a functional data processing device including without limitation a bus, software and data storage such as volatile and non-volatile memory, input/output devices, graphical user interfaces (GUIs), removable data storage, and wired and/or wireless communication interface devices including Wi-Fi, Bluetooth, LAN, etc.
Computer-executable instructions or programs (e.g., software or code) and data described herein may be programmed into and tangibly embodied in a non-transitory computer-readable medium that is accessible to and retrievable by a respective processor as described herein which configures and directs the processor to perform the desired functions and processes by executing the instructions encoded in the medium. A device embodying a programmable processor configured to such non-transitory computer-executable instructions or programs may be referred to as a “programmable device”, or “device”, and multiple programmable devices in mutual communication may be referred to as a “programmable system.” It should be noted that non-transitory “computer-readable medium” as described herein may include, without limitation, any suitable volatile or non-volatile memory including random access memory (RAM) and various types thereof, read-only memory (ROM) and various types thereof, USB flash memory, and magnetic or optical data storage devices (e.g., internal/external hard disks, floppy discs, magnetic tape CD-ROM, DVD-ROM, optical disk, ZIP™ drive, Blu-ray disk, and others), which may be written to and/or read by a processor operably connected to the medium.
In certain embodiments, the present invention may be embodied in the form of computer-implemented processes and apparatuses such as processor-based data processing and communication systems or computer systems for practicing those processes. The present invention may also be embodied in the form of software or computer program code embodied in a non-transitory computer-readable storage medium, which when loaded into and executed by the data processing and communications systems or computer systems, the computer program code segments configure the processor to create specific logic circuits configured for implementing the processes.
Ranges are used as shorthand for describing each and every value that is within the range. Any value within the range can be selected as the terminus of the range. In addition, all references cited herein are hereby incorporated by referenced in their entireties. In the event of a conflict in a definition in the present disclosure and that of a cited reference, the present disclosure controls.
In the following description, where circuits are shown and described, one of skill in the art will recognize that, for the sake of clarity, not all peripheral circuits or components are shown in the figures or described in the description. Further, the terms “couple” and “operably couple” can refer to a direct or indirect coupling of two components of a circuit.
Voltage Reduction Circuit
Referring now to
In the exemplified embodiment, the system 10 includes a radio frequency (RF) source 30 having a substantially fixed output impedance Rsource (e.g., 50 ohms). The RF source 30 generates an RF signal that is received at the input 101 of the matching network 100. The RF source 30 is also operably coupled to chassis ground GND. The RF source 30 may be an RF generator of a type that is well-known in the art to generate an RF signal at an appropriate frequency and power for the process performed within the load 20. The RF source 30 may be electrically connected to the RF input 101 of the impedance matching network 100 using a coaxial cable or similar means, which for impedance matching purposes may have the same fixed (or substantially fixed) impedance as the RF source 30.
The system 10 further includes a load. In the exemplified embodiment, the load is a plasma chamber 20 for manufacturing a semiconductor. The semiconductor device can be a microprocessor, a memory chip, or another type of integrated circuit or device.
As is known in the art, the plasma within a plasma chamber 20 typically undergoes certain fluctuations outside of operational control so that the impedance presented by the plasma chamber 20 is a variable impedance. Since the variable impedance of the plasma chamber 20 cannot be fully controlled, an impedance matching network may be used to create an impedance match between the plasma chamber 20 and the RF source 30. In other embodiments, the load can be any load of variable impedance that can utilize a matching network.
The plasma chamber 20 can include a first electrode 22 and a second electrode 26, and in processes that are well known in the art, the first and second electrodes, in conjunction with appropriate control systems (not shown) and the plasma in the plasma chamber 120, enable one or both of deposition of materials onto a substrate 24 and etching of materials from the substrate 24. The plasma chamber 20 can receive an RF signal from the output 102 of the matching network 100 and thereby receive RF power from the RF source 30 to energize plasma within the plasma chamber 20 to perform the deposition or etching.
The matching network 100 can consist of a single module within a single housing designed for electrical connection to the RF source 30 and plasma chamber 20. In other embodiments, the components of the matching network 100 can be located in different housings, some components can be outside of the housing, and/or some components can share a housing with a component outside the matching network 100.
The matching network 100 provides impedance matching for the RF source 30 and the plasma chamber 20. The matching network 100 is operably coupled between the RF source 30 and the plasma chamber 20. The matching network 100 includes an input 101 configured to operably couple to the RF source 30, and an output 102 configured to operably couple to the plasma chamber 20. The matching network 100 further includes a first variable capacitor C1 and a second variable capacitor C2. In a preferred embodiment, the variable capacitors C1, C2 are EVCs, though in other embodiments, other types of variable capacitors can be used, such as VVCs.
In this first embodiment, the matching network 100 is a pi network. The first variable capacitor C1 forms part of a first shunt S1 parallel to the RF source 30, and the second variable capacitor C2 forms part of a second shunt S2 separate from the first shunt S1. Put differently, the first variable capacitor C1 is parallel to the input 101, and the second variable capacitor C2 is parallel to the output 102. Further, a first inductor L1 is located between the first shunt S1 and the second shunt S2. In other embodiments, a second inductor L2 can be located between the second shunt S2 and the output 102.
The first variable capacitor C1 has a first capacitance, and the second variable capacitor C2 has a second capacitance. The first capacitance and the second capacitance are configured to be altered to create an impedance match at the input. As will be discussed further herein, however, the invention is not limited to pi matching networks, as other types of matching networks can be utilized.
To reduce a voltage on the second variable capacitor C2, the matching network 100 further includes a third capacitor C3 in series with the second variable capacitor C2. Components or nodes are said to be “in series” if the same current flows through each. In the exemplified embodiment, the third capacitor C3 forms part of the second shunt S2, though the invention is not so limited. In other embodiments, the third capacitor C3 can be at different locations, provided the third capacitor C3 is positioned to reduce a voltage on the second variable capacitor C2 (the reduced voltage being, for example, an alternating current or radio frequency voltage). For example, the positions of C2 and C3 in
In the exemplified embodiment, a fourth capacitor C4 is included. The fourth capacitor C4 is parallel to the second shunt S2 and helps to offset the total capacitance. In other embodiments, the fourth capacitor C4 can be omitted.
In the embodiment discussed below, the values of the additional fixed capacitor C3 and variable capacitors C2 (see
The voltage drop VDrop across the variable capacitor C2 (see
If C2Max=C3, then the formula can be simplified as below, where C2Max=C3=C.
As a result, VDrop is equal to half of the voltage that was originally capacitor C2 (VC2) when C3 was not included.
Continuing with this example, the next step is to find the maximum capacitance required for the variable and fixed capacitors. In this case, the total series capacitance CVar is equal to the maximum capacitance of the original variable capacitor C2. The capacitance CVar can be calculated by the following equation:
If C2Max=C3=C, the equation can be modified as follows:
C is then solved for as follows:
C=2*CVarMax
The minimum value for variable capacitor C2, C2Min, can be found by using the previously calculated value for C3 and replacing the CVarMax with the minimum capacitance, CVarMin, as in the following equations:
It can also be seen, however, that the first (usable) region 702 has gaps representing areas where a perfect impedance match is not provided. This can be a result of adding capacitor C3 to reduce the voltage, which increases the gap between the quantized states of the variable capacitor when approaching C2Min and decreased the spacing when approaching C2Max.
The addition of a third variable or non-variable capacitor, to help further reduce VDrop, can change the capacitor range of the variable capacitor combination C2. To address this, a variable capacitor such as an EVC can be easily modified to adjust the capacitor range. The third capacitor can also change the step sizes and make them nonlinear. In certain embodiments, a more uniform distribution can be provided by using a nonlinear variable capacitor or multiple variable capacitors in series.
In other embodiments, transmission lines (which can comprise microstrips, coaxial cable, a wave guide, or any other conductive medium) can be used to rotate the impedance of the matching network on the Smith chart. The length of the transmission line at a certain frequency determines the amount of rotation. The longer the transmission line, the more rotation there will be on the Smith chart. A quarter wavelength (λ/4) transmission line (which can be calculated using the operating frequency and the property of the dielectric material) will have a 180° clockwise rotation on the Smith chart, a half wavelength (λ/2) transmission line will have a 360° clockwise rotation on the Smith chart, an eighth wavelength (λ/8) would be equal to 45°, and so on.
If the matching network 1000 uses only quarter wave lines, or something that would ultimately give a 90° phase shift [(λ/4)+N*(λ/2)], and there are the three capacitors C101, C102, C103 in shunt (together with transmission lines TL1 and TL2), as shown in
The foregoing embodiments provide several advantages. The embodiments disclose a matching network that can more effectively handle high voltages generated in a network. Further, the embodiments avoid or minimize the need for increased component sizes (as typically required for a VVC) or increased numbers of peripheral components (as typically required with an EVC). Further, the embodiments provide a solution that has a lower cost than previous methods of addressing high voltages in a matching network. As shown herein, the embodiments can increase the usable range of a matching network without sacrificing the impedance range, using a more expensive, larger, higher voltage component, or adding more peripheral components to meet the voltage requirements.
Capacitance Variation
As discussed above, an EVC is a type of variable capacitor that can use multiple switches, each used to create an open or short circuit, with individual series capacitors to change the capacitance of the variable capacitor. The switches can be mechanical (such as relays) or solid state (such as PIN diodes, transistors, or other switching devices). The following is a discussion of various methods for setting up an EVC or other variable capacitor to provide varying capacitances.
In an accumulative setup of an EVC, the approach to linearly increase the capacitor value from the minimum starting point (where all switches are open) is to incrementally increase the number of fine tune capacitors that are switched into the circuit. Once the maximum number of fine tune capacitors is switched into circuit, a coarse tune capacitor is switch in, and the fine tune capacitors are switched out. The process starts over with increasing the number of fine tune capacitors that are switched into circuit, until all fine and coarse tune capacitors are switched in. In this setup, all of the fine tune capacitors have the same or a substantially similar value, and all the coarse tune capacitors have the same or a substantially similar value. Further, the capacitance value of one coarse tune capacitor about equals the combined capacitance value of all fine tune capacitors plus an additional fine tune capacitor into the circuit, thus enabling a linear increase in capacitance.
An example of this in an ideal setting would be if the fine tune capacitors were equal to 1 pF, and the coarse tune capacitors were equal to 10 pF. In this ideal setup, when all switches are open, the capacitance is equal to 0 pF. When the first switch is closed, there is 1 pF in the circuit. When the second switch is closed there is 2 pF in the circuit, and so on, until nine fine tune switches are closed, giving 9 pF. Then, the first 10 pF capacitor is switched into circuit and the nine fine tune switches are opened, giving a total capacitance of 10 pF. The fine tune capacitors are then switched into circuit from 11 pF to 19 pF. Another coarse tune capacitor can then be switched into circuit and all fine tune capacitors can be switched out of circuit giving 20 pF. This process can be repeated until the desired capacitance is reached.
This can also be taken one step further. Using the previous example, having nine 1 pF capacitors and also nine 10 pF capacitors, the variable capacitor circuit can have even larger values, 100 pF, to switch in and out of circuit. This would allow the previous capacitor array to go up to 99 pF, and then the 100 pF capacitor can be used for the next increment. This can be repeated further using larger increments, and can also be used with any counting system.
An alternative capacitor setup is referred to herein as a binary weighted setup. In the binary weighted setup, the capacitor values will all be different. The first value is equal to the minimum desired change in capacitance. Then each successive capacitor value is increased to double the change in capacitance from the previous up until the maximum desired capacitor value, when all capacitors are switched in.
In one example (that assumes there are no parasitic capacitances), the lowest capacitance capacitor would be a 1 pF capacitor, followed by 2 pF, 4 pF, and so on. When all switches are open, the value is 0 pF. When the 1 pF capacitor is switched in, the EVC total capacitance value is 1 pF. Then the 1 pF capacitor is switched out of circuit and the 2 pF capacitor is switched in, causing a total capacitance of 2 pF. When 3 pF is needed, the 1 pF and the 2 pF capacitors are switched in. For 4 pF, the 1 and 2 pF capacitors are switched out of circuit and the 4 pF capacitor is switched into circuit. This can be repeated adding 1 pF, 2 pF, and 4 pF together in different combinations in the circuit, creating values of 5 pF, 6 pF and 7 pF.
In the embodiment of
The binary weighted setup can result in using far less capacitors to switch in and out of circuit to achieve the same or better resolution and range. A potential problem with this setup, however, is that, once the capacitor reaches a certain value, the voltage and/or current on that particular capacitor or the current on the switch can be higher than the specification allows for. This forces the EVC to use multiple capacitors in parallel for each switch of lower value.
Another potential disadvantage of the binary weighted setup is that it is difficult to achieve a consistent step size throughout the range. The above capacitor values for the binary setup give an average step size of 2.32 pF, compared to the accumulative method, which has an average step size of 2.72 pF. But the minimum and maximum step for the binary weighted setup is 1.51 pF and 7.51 pF, respectively, while the accumulative setup's minimum and maximum are only 2.4 pF and 2.75 pF.
With higher value capacitors, this can be further complicated with finding a value that does not overshoot multiple steps. Also, part-to-part tolerances being greater than the minimum step size can further increase the gaps. A 300 pF capacitor with a ±5% tolerance can have up to 15 pF of extra capacitance. The delta capacitance of the three least significant binary weighted capacitors total 15.44 pF. So, these values are completely overstepped, and linearity is lost.
One modification to the binary weighted setup is to have the larger capacitor values rounded down to the next standard value, for example 3.0 pF, 5.1 pF, 9.1 pF, 18 pF, 36 pF, 68 pF, 130 pF, 240 pF. Doing this would create some overlap in capacitor value where there would be a drop in capacitance when switching in the new larger value and switching out the previous smaller values. For example, the values 3 pF through 36 pF would combine to equal 71.2 pF, but the next step is 68 pF, a drop of 3.2 pF. This problem can be avoided, however, because the EVC does not need to go sequentially through each step, but instead can use software to lookup the next known capacitor position to switch to it directly.
The switches 60 can be coupled to switch driver circuits 80 for driving the switches on and off. The variable capacitance system 55 can further include a control unit 85 operably coupled to the driver circuits 80 for instructing the driver circuits 80 to switch one or more of the switches 60, and thereby turn one or more of the capacitors 77 on or off. In one embodiment, the control unit 85 can form part of a control unit that controls variable capacitor, such as a control unit that instruct the variable capacitors of a matching network to change capacitances to achieve an impedance match.
In the exemplified embodiment, the first capacitors 50 are fine tune capacitors using a method similar to the binary method discussed above. Thus, the fine tune capacitors 50 can have capacitances increasing by a factor of about two, where “about two” refers to a value of 1.5 to 2.5. In an ideal example where there are no parasitic capacitances, the fine tune capacitors could increase by a factor of exactly two (e.g., 1 pF, 2 pF, 4 pF, 8 pF).
But in real world applications, parasitic capacitances, such as those provided by the switches 60, are another factor that must be considered in choosing the capacitance values of the fine tune capacitors 50. Thus, while a first capacitor may have a value of 1 pF, and the corresponding capacitor-switch pair may thus provide 1 pF to a total capacitance of the variable capacitor when the capacitor's corresponding switch is closed, when the switch is open, the open switch may have a parasitic capacitance of, for example, 1 pF. Thus, when the switch is open, there are essentially two 1 pF capacitances in series, which is equivalent to 0.5 pF. Thus, when the first fine tune capacitor switch switches from open to close, the change in the capacitance contributed to the variable capacitor by this capacitor-switch pair is from 0.5 pF (open) to 1 pF (closed), for a change of 0.5 pF. These changes in capacitance caused by parasitic capacitances must be taken into consideration in choosing capacitor values to ensure that the target step size (e.g., 0.5 pF) for the total capacitance can be achieved.
Returning to the previous example, if an EVC had four fine capacitors, and each capacitor switch had a parasitic capacitance of 1 pF, and a step size of 0.5 pF was desired, the fine capacitors could be 1 pF, 1.6 pF, 2.7 pF, and 4.7 pF. As discussed, the first fine capacitor (1 pF) would cause a 0.5 pF change to the total capacitance when switched in. The second fine tune capacitor (1.6 pF) and its switch would provide 0.6 pF when open and 1.6 pF when closed, thus causing a change in the total capacitance of about 1 pF when switched in. The third fine tune capacitor (2.7 pF) would cause a change in the total capacitance of about 2 pF when switched in, and the fourth fine tune capacitor (4.8 pF) would cause a change in the total capacitance of about 4 pF when switched in. Thus, the changes to the total capacitance caused by the switching in of each of the four first tune capacitors would be 0.5 pF, 1 pF, 2 pF, and 4 pF, respectively. Thus, the changes caused by the switching in of each of these capacitors increases by a factor of two. It is understood that the invention is not limited to these values. Other capacitor values (or switches with other parasitic capacitances) can be used such that the changes caused increase by a factor of about two. For example, the 4.8 pF capacitor of the above example could be replaced with a standard 4.7 pF capacitor. Further, other capacitance values can be used to achieve other step sizes. The foregoing considerations regarding parasitic capacitances can equally apply to the binary setup discussed above.
The second capacitors 70, by contrast, are coarse tune capacitors using a method similar to the accumulative method discussed above. Thus, the second capacitors can have a substantially similar capacitance. Capacitors are considered to have substantially similar capacitances if, of the capacitors in question, no capacitance is 15 percent (15%) greater than or less than another capacitance. Alternatively, the capacitors can be chosen such that there are no gaps in total capacitance greater than the minimum step size needed for the given application.
The first (fine) capacitors 50 can increase their value (or the value by which they change the total capacitance) in a binary fashion, and thus by a factor of about two, up to the first coarse position. When all of the fine capacitors 50 are switched into circuit, the first coarse capacitor 71 can be switched in, and all the fine capacitors 50 are switched out. Then the fine capacitors 50 can be switched in and out until they are all switched into circuit. The next step would be to add another coarse tune capacitor 72. It is understood, however, that the EVC does not need to go sequentially through each step to achieve a desired total capacitance, but instead can use software to lookup the next known capacitor position to switch to it directly.
In one embodiment, there are four fine capacitors 50. The first fine capacitor 51 has a capacitance of 3.0 pF, the second fine capacitor 52 has a capacitance of 5.1 pF, the third fine capacitor 53 has a capacitance of 9.1 pF, and the fourth fine capacitor has a capacitance of 18 pF. Further, there are four coarse tune capacitors 70 having capacitances of 36 pF each. Thus, in this embodiment, the total combined capacitance of the fine capacitors (35.2 pF) is substantially similar to the individual capacitances of the coarse capacitors (36 pF). It also follows that the capacitance of each of the coarse capacitors is greater than a greatest individual capacitance (18 pF) of the fine capacitors.
In this embodiment, there will be 208 unique capacitor values. With parasitics, the minimum total capacitance is 10.25 pF and the maximum total capacitance is 467.2 pF. The range is less than 1 pF less than the accumulative method, but with an increase in unique points. The minimum step size is 1.51 pF, the maximum is 2.54 pF and the average is 2.21 pF. Thus, the results of the setups discussed are as follows:
The partial binary method provides multiple advantages. First, the current on each capacitor will not be over its rating. The maximum current and the current rating will be the same for all coarse capacitors, because they will be the same value. With the fine steps, all of the capacitor values have a higher ratio of current rating to maximum current. Therefore, no issues should arise.
Further, the partial binary approach avoids large gaps in capacitance steps. Further, less capacitors are needed to have the same range, while the number of unique values can potentially be increased. With less capacitors, the EVC will need less switches, causing the EVC to take up less area. Further, less capacitors will require less hardware to control the switches.
Binary with overlap can also be implemented in this setup to avoid any issues with part tolerance if required. Thus, the coarse capacitor values could be reduced in capacitance. It is further understood that, while the exemplified embodiment uses four first capacitors 50 and four second capacitors 70, other numbers of capacitors can be used. Also, other capacitor values can be used.
It is understood, however, that the EVC does not need to go sequentially through each step, but instead can use software to lookup the next known capacitor position to switch to it directly. It is further understood that a desired total capacitance can be achieved by having switched on a minimal number of capacitors of the plurality of capacitors.
In another embodiment, the variable capacitor can for part of a method of manufacturing a semiconductor, such as the system displayed shown in
Restricted Partial Binary Capacitor Switching
The switches 60-1 can be coupled to switch driver circuits 80-1 for driving the switches on and off. The variable capacitance system 55-1 can further include a control unit 85-1 operably coupled to the driver circuits 80-1 for instructing the driver circuits 80-1 to switch one or more of the switches 60-1, and thereby turn one or more of the capacitors 77-1 on or off. In one embodiment, the control unit 85-1 can form part of a control unit for a matching network that controls the capacitances of one or more variable capacitors of the matching network to achieve an impedance match. In the exemplified embodiment, the control unit 85-1 (sometimes referred to as “control circuit”) is configured to (a) determine which of the coarse capacitors and the fine capacitors to have switched in to achieve an impedance match and (b) cause the determined coarse and fine capacitors to be switched in. This can be based on a determination, by the control unit or otherwise, of the variable impedance of the plasma chamber. The invention is not so limited, however, as the determination of the capacitors to switch in can be based on other factors, such as an input impedance at the input of the matching network.
In the exemplified embodiment, the fine capacitors 50-1 have capacitances increasing by a factor of about two, where “about two” refers to a value of 1.5 to 2.5, though the invention is not so limited and the fine capacitors can increase in value in another manner. In an ideal example where there are no parasitic capacitances, the fine tune capacitors could increase by a factor of exactly two (e.g., 1 pF, 2 pF, 4 pF, 8 pF, etc.). But as discussed above, in real world applications parasitic capacitances, such as those provided by the switches 60-1, are another factor that must be considered in choosing the capacitance values of the fine tune capacitors 50-1. In the exemplified embodiment, the fine capacitors 50-1 have values of 47 pF, 91 pF, 180 pF, 390 pF, 750 pF, 1500 pF, though the invention is not limited to these values or this number of capacitors.
According to the restricted partial binary setup, the coarse capacitors are made up of first coarse capacitors 70-1 each having a substantially similar first coarse capacitance, and second coarse capacitors 71-1 each having a substantially similar second coarse capacitance. Capacitors are considered to have substantially similar capacitances if, of the capacitors in question, no capacitance is 15 percent (15%) greater than or less than another capacitance. In the exemplified embodiment, there are 6 first coarse capacitors 70-1 each having a capacitance of 1000 pF, and 12 second coarse capacitors 71-1 each having a capacitance of 3000 pF. Thus, in the exemplified embodiment, one of the fine capacitors (the 1500 pF fine capacitor) has a capacitance greater than the first coarse capacitance of 1000 pF. In other embodiments, more than one of the fine capacitors can have a capacitance greater than the first coarse capacitance. Further, in other embodiments other values and other numbers of coarse capacitors can be used.
Each capacitor of the plurality of capacitors 77-1 provides a change to a total capacitance of the variable capacitor 75-1 when the capacitor is switched in. To gradually increase the total capacitance of the variable capacitor 75-1, the control unit 85-1 can successively switch in, in a predetermined order, each of the first coarse capacitors 70-1, followed by each of the second coarse capacitors 71-1. As for the fine capacitors 50-1, the control unit restricts which fine capacitors can be switched in. That is, it only switches in the fine capacitors 50-1 whose capacitance is less than a capacitance of a next coarse capacitor of the coarse capacitors predetermined to be switched in next.
As discussed above, in the exemplified embodiment, the fine capacitors 50-1 have capacitances substantially equal to 47 pF, 91 pF, 180 pF, 390 pF, 750 pF, 1500 pF; the first coarse capacitors 70-1 comprise six capacitors having capacitances substantially equal to 1000 pF; and the second coarse capacitors 71-1 comprise twelve capacitors having capacitances substantially equal to 3000 pF. To gradually increase capacitance, the fine capacitors can be switched into the circuit in a binary fashion as described above except for the 1500 pF fine capacitor, which is restricted from switching in until all the first coarse capacitors are switched in. When all the 1000 pF first coarse capacitors are switched in, the next coarse capacitor to be switched in is a 3000 pF second coarse capacitor. Thus, once all the 1000 pF first coarse capacitors are switched in, the 1500 pF fine capacitor is able to switch in with the rest of the fine capacitors.
Table 3 below shows the first 167 positions (“Pos.”) for a variable capacitor using the restricted partial binary setup. The total capacitance (“Total Cap.”) for each position is shown, along with the fine capacitors (F1-F6) and first coarse capacitors (C1-C6) switched in for a given position. As can be seen, although the fine capacitors switch in in a somewhat typical binary fashion, the 1500 pF fine capacitor is not able to switch in until position 165, when all of the first coarse capacitors have been switched in.
It is understood that the variable capacitor 75-1 does not need to go sequentially through each step to achieve a desired total capacitance, but instead can use software to lookup the desired capacitor position to switch to it directly. It is further understood that while the exemplified embodiment uses two sets of coarse capacitors (first coarse capacitors and second coarse capacitors) in other embodiments more or less sets of coarse capacitors can be used. For example, three sets of course capacitors could be used, each with a different capacitance value. It is further understood that the variable capacitance system 55-1 can form part of any one of the impedance matching networks discussed above. For example, a matching network may include an input configured to operably couple to an RF source, an output configured to operably couple to a plasma chamber for manufacturing a semiconductor, and the variable capacitance system 55-1 of
The restricted partial binary setup described above provides multiple advantages. For example, by restricting one or more fine capacitors from switching in, the setup avoids overlap, that is, instances where there is more than one solution for a given impedance value. Further, the restricted partial binary setup allows the variable capacitor to provide a large range of capacitance values by allowing for the use of a high percentage of coarse capacitors. Further, the setup avoids large gaps in capacitance values. Further, less capacitors are needed, thus requiring less switches and causing the variable capacitor to take up less area.
Heat Pipe Inductor
As discussed earlier, several problems can result from inductors becoming heated in high-power systems such as matching networks. Several methods for cooling high temperature inductors can be used, such as forced convection (e.g., fans), increasing thermal mass (e.g., heat sink, fins), and water cooling. Each of these methods, however, has drawbacks. For example, forced convection is limited to the air velocity and flow rate produced by one or more fans, and by the exposed surface area of the inductor. Heat sinks and fins improve temperatures marginally, but are confined to the outside edges of the inductors due to their helical shape. Consequently, the middle of the inductor remains at high temperatures. Running cool water through a hollow pipe inductor can be effective at reducing temperatures throughout the component, but this method requires a water source, which is not available in many high-power RF applications.
In the exemplified embodiment, an electronic device 160 is positioned between the capacitors 151, 152. The electronic device may comprise the inductor 150 and heat sinks 171, 172. The inductor is formed from a heat pipe 153 that is wound in a three-dimensional shape. The first heat sink 171 may be coupled adjacent to a first end 150A of the heat pipe 153, and the second heat sink 172 may be coupled adjacent to a second end 150B of the heat pipe 153, the second end 150B being opposite to the first end 150A. In a preferred embodiment, liquid in heat pipe is heated to become vapor. This vapor travels to the heat sink, where it cooled and becomes liquid again.
The matching network 155 of claim 1 may further include a fan 181 configured to blow air across the first and second heat sinks to create forced convection and provide further cooling. The fan 181 may also blow air across the inductor 150.
Heat pipes utilize phase transition, in addition to thermal conductivity, to move thermal energy more efficiently than a solid conductor alone. When the ends of the heat pipe inductor are in contact with a heat sink, the resulting maximum temperature is a fraction of a solid pipe or tube inductor, even with minimal air flow.
The simulations were performed inside a 12″×8″×8″ adiabatic box. The box had a 6.5-inch diameter opening where a constant, uniform flow of air moved into the box at 8 m/s. On the other side is a 7″×7″ environmental pressure opening that serves as the outlet condition. The inductor in each simulation received 80 W of power dissipation. The power dissipation is defined as a surface loss, to account for the skin effect. All three inductor variations were given an outer diameter of ⅜ inches. They were wound with three turns at a pitch of 1 inch and center-to-center helical diameter of 3 inches. The ends, or legs, of the inductors had 1.75 inches of extra material where 18 aluminum heat fins (1.5″×0.75″×0.04″) of heat sinks were attached with 0.06-inch spacing between them. This set up can be seen in
Three simulations were conducted using three different types of ⅜-inch OD copper winding. The results from the simulations can be seen in the temperature surface plots of
As is shown, the heat pipe inductor 150 of
Whiles
For a given application, the heat pipe design (e.g., diameter, length, and working fluid) is driven by the specific amount of power that needs to be moved. Generally, larger-diameter pipes can move more heat. High-power application will favor larger-diameter pipes, and inductor shapes that allow larger-diameter pipes, such as the cylinder shape shown in the above discussed embodiments. A shape that required small, thin wire would not be ideal for a high-power application. Further, heat pipes have limits on how much heat they can move. If the power dissipation in the inductor is too great for the selected heat pipe, it will reach a critical point where the gas inside is not able to condense, making the heat pipe non-functional. The type of heat sink used would also be dependent upon the amount of power dissipated through the inductor. For example, as power dissipation increases, fins on the sink may increase in size and/or quantity.
As discussed, a matching network utilizing such a heat pipe inductor can be utilized in a system or method for manufacturing of semiconductors. According to such a method, a matching network may be operably coupled between an RF source and a plasma chamber, the plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate. The matching network may include an input configured to operably couple to the RF source, an output configured to operably couple to the plasma chamber, a first variable capacitor, an inductor formed from a heat pipe that is wound in a three-dimensional shape, a first heat sink coupled adjacent to a first end of the heat pipe, and a second heat sink coupled adjacent to a second, opposite end of the heat pipe. A substrate may be placed in the plasma chamber, and the plasma may be energized within the plasma chamber by coupling RF power from the RF source into the plasma chamber to perform a deposition or etching. The capacitance of the first variable capacitor may be controlled to achieve an impedance match. While the above embodiments discuss using one or more variable capacitors in a matching network to achieve an impedance match, it is noted that any variable reactance element can be used. A variable reactance element can include one or more reactance elements, where a reactance element is a capacitor or inductor or similar reactive device.
The embodiments discussed herein provide many advantages. As shown by the foregoing simulations, the heat pipe inductor provides dramatic cooling improvements. The disclosed embodiments can provide improved cooling performance while saving space, which is valuable in matching networks for semiconductor manufacturing, as well as certain other high-power applications. Further, the heat pipe inductor is particularly useful in cooling the middle portions of the inductor, without requiring other resources such as a regular water source.
As used throughout, ranges are used as shorthand for describing each and every value that is within the range. Any value within the range can be selected as the terminus of the range. In addition, all references cited herein are hereby incorporated by referenced in their entireties. In the event of a conflict in a definition in the present disclosure and that of a cited reference, the present disclosure controls.
While the invention or inventions have been described with respect to specific examples, those skilled in the art will appreciate that there are numerous variations and permutations of the above described invention(s). It is to be understood that other embodiments may be utilized and structural and functional modifications may be made without departing from the scope of the present invention(s). Thus, the spirit and scope should be construed broadly as set forth in the appended claims.
The present application is a continuation in part of U.S. patent application Ser. No. 15/816,351, filed Nov. 17, 2017, which is a continuation in part of U.S. patent application Ser. No. 15/450,495, filed Mar. 6, 2017, which is a continuation in part of U.S. patent application Ser. No. 15/196,821, filed Jun. 29, 2016, which claims the benefit of U.S. Provisional Patent Application No. 62/185,998 filed on Jun. 29, 2015. U.S. patent application Ser. No. 15/450,495 further claims the benefit of U.S. Provisional Patent Application No. 62/303,625, filed Mar. 4, 2016. U.S. patent application Ser. No. 15/816,351 further claims the benefit of U.S. Provisional Patent Application No. 62/424,162, filed Nov. 18, 2016. The disclosures of the aforementioned priority applications are incorporated herein by reference in their entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 3681672 | Strauss | Aug 1972 | A |
| 3828281 | Chambers | Aug 1974 | A |
| 4110700 | Rosen et al. | Aug 1978 | A |
| 4679007 | Reese et al. | Jul 1987 | A |
| 4692643 | Tokunaga et al. | Sep 1987 | A |
| 4751408 | Rambert | Jun 1988 | A |
| 4929855 | Ezzeddine | May 1990 | A |
| 5012123 | Ayasli et al. | Apr 1991 | A |
| 5079507 | Ishida et al. | Jan 1992 | A |
| 5545966 | Ramos et al. | Aug 1996 | A |
| 5654679 | Mavretic et al. | Aug 1997 | A |
| 5815047 | Sorensen et al. | Sep 1998 | A |
| 5849136 | Mintz et al. | Dec 1998 | A |
| 5880921 | Tham et al. | Mar 1999 | A |
| 5889252 | Williams et al. | Mar 1999 | A |
| 5971591 | Vona et al. | Oct 1999 | A |
| 6046641 | Chawla et al. | Apr 2000 | A |
| 6137367 | Ezzedine et al. | Oct 2000 | A |
| 6252354 | Collins et al. | Jun 2001 | B1 |
| 6400012 | Miller et al. | Jun 2002 | B1 |
| 6424232 | Mavretic et al. | Jul 2002 | B1 |
| 6583572 | Veltrop et al. | Jun 2003 | B2 |
| 6621372 | Kondo et al. | Sep 2003 | B2 |
| 6657395 | Windhorn | Dec 2003 | B2 |
| 6677828 | Harnett et al. | Jan 2004 | B1 |
| 6703080 | Reyzelman et al. | Mar 2004 | B2 |
| 6791274 | Hauer et al. | Sep 2004 | B1 |
| 6794951 | Finley | Sep 2004 | B2 |
| 6818562 | Todorow et al. | Nov 2004 | B2 |
| 6888313 | Blackburn et al. | May 2005 | B2 |
| 6888396 | Hajimiri et al. | May 2005 | B2 |
| 6946847 | Nishimori et al. | Sep 2005 | B2 |
| 6967547 | Pellegrini et al. | Nov 2005 | B2 |
| 7004107 | Raoux et al. | Feb 2006 | B1 |
| 7071786 | Inoue et al. | Jul 2006 | B2 |
| 7095178 | Nakano et al. | Aug 2006 | B2 |
| 7113761 | Bickham et al. | Sep 2006 | B2 |
| 7122965 | Goodman | Oct 2006 | B2 |
| 7164236 | Mitrovic et al. | Jan 2007 | B2 |
| 7199678 | Matsuno | Apr 2007 | B2 |
| 7212406 | Kaishian et al. | May 2007 | B2 |
| 7251121 | Bhutta | Jul 2007 | B2 |
| 7298091 | Pickard et al. | Nov 2007 | B2 |
| 7298128 | Bhutta | Nov 2007 | B2 |
| 7304438 | Kishinevsky | Dec 2007 | B2 |
| 7332981 | Matsuno | Feb 2008 | B2 |
| 7439610 | Weigand | Oct 2008 | B2 |
| 7480571 | Howald et al. | Jan 2009 | B2 |
| 7495524 | Omae et al. | Feb 2009 | B2 |
| 7498908 | Gurov | Mar 2009 | B2 |
| 7514935 | Pankratz | Apr 2009 | B2 |
| 7518466 | Sorensen et al. | Apr 2009 | B2 |
| 7535312 | McKinzie, III | May 2009 | B2 |
| 7602127 | Coumou | Oct 2009 | B2 |
| 7642879 | Matsuno | Jan 2010 | B2 |
| 7666464 | Collins et al. | Feb 2010 | B2 |
| 7714676 | McKinzie, III | May 2010 | B2 |
| 7728602 | Valcore et al. | Jun 2010 | B2 |
| 7745955 | Kirchmeier et al. | Jun 2010 | B2 |
| 7755300 | Kishinevsky et al. | Jul 2010 | B2 |
| 7764140 | Nagarkatti et al. | Jul 2010 | B2 |
| 7777567 | Polizze | Aug 2010 | B2 |
| 7852170 | McKinzie, III | Dec 2010 | B2 |
| 7863996 | Cotter et al. | Jan 2011 | B2 |
| 7868556 | Kia | Jan 2011 | B2 |
| 7872523 | Sivakumar et al. | Jan 2011 | B2 |
| 7917104 | Manssen et al. | Mar 2011 | B2 |
| 7969096 | Chen | Jun 2011 | B2 |
| 8008982 | McKinzie, III | Aug 2011 | B2 |
| 8040068 | Coumou et al. | Oct 2011 | B2 |
| 8089026 | Sellers | Jan 2012 | B2 |
| 8102954 | Coumou | Jan 2012 | B2 |
| 8110991 | Coumou | Feb 2012 | B2 |
| 8203859 | Omae et al. | Jun 2012 | B2 |
| 8207798 | Wright | Jun 2012 | B1 |
| 8217731 | McKinzie, III | Jul 2012 | B2 |
| 8217732 | McKinzie, III | Jul 2012 | B2 |
| 8228112 | Reynolds | Jul 2012 | B2 |
| 8237501 | Owen | Aug 2012 | B2 |
| 8264154 | Banner et al. | Sep 2012 | B2 |
| 8278909 | Fletcher | Oct 2012 | B2 |
| 8289029 | Coumou | Oct 2012 | B2 |
| 8299867 | McKinzie, III | Oct 2012 | B2 |
| 8314561 | Fisk et al. | Nov 2012 | B2 |
| 8330432 | Van Zyl et al. | Dec 2012 | B2 |
| 8334657 | Xia | Dec 2012 | B2 |
| 8334700 | Coumou et al. | Dec 2012 | B2 |
| 8335479 | Koya et al. | Dec 2012 | B2 |
| 8344559 | Van Zyl et al. | Jan 2013 | B2 |
| 8344801 | Owen et al. | Jan 2013 | B2 |
| 8368308 | Banna et al. | Feb 2013 | B2 |
| 8368469 | Mohammadi et al. | Feb 2013 | B2 |
| 8395322 | Coumou | Mar 2013 | B2 |
| 8416008 | Van Zyl et al. | Apr 2013 | B2 |
| 8436643 | Mason | May 2013 | B2 |
| 8461842 | Thuringer et al. | Jun 2013 | B2 |
| 8466736 | Reynolds | Jun 2013 | B1 |
| 8487706 | Li et al. | Jul 2013 | B2 |
| 8502689 | Chen et al. | Aug 2013 | B2 |
| 8513889 | Zhang et al. | Aug 2013 | B2 |
| 8520413 | Tran et al. | Aug 2013 | B2 |
| 8536636 | Englekirk | Sep 2013 | B2 |
| 8552665 | Larson et al. | Oct 2013 | B2 |
| 8558633 | McKinzie, III | Oct 2013 | B2 |
| 8559907 | Burgener et al. | Oct 2013 | B2 |
| 8564381 | McKinzie | Oct 2013 | B2 |
| 8569842 | Weis et al. | Oct 2013 | B2 |
| 8576010 | Yanduru | Nov 2013 | B2 |
| 8576013 | Coumou | Nov 2013 | B2 |
| 8587321 | Chen et al. | Nov 2013 | B2 |
| 8620236 | Manssen et al. | Dec 2013 | B2 |
| 8624501 | Nagarkatti et al. | Jan 2014 | B2 |
| 8633782 | Nagarkatti et al. | Jan 2014 | B2 |
| 8638159 | Ranta et al. | Jan 2014 | B2 |
| 8649754 | Burgener et al. | Feb 2014 | B2 |
| 8659335 | Nagarkatti et al. | Feb 2014 | B2 |
| 8674606 | Carter et al. | Mar 2014 | B2 |
| 8680928 | Jeon et al. | Mar 2014 | B2 |
| 8686796 | Presti | Apr 2014 | B2 |
| 8710926 | Nagarkatti et al. | Apr 2014 | B2 |
| 8716984 | Mueller et al. | May 2014 | B2 |
| 8723423 | Hoffman et al. | May 2014 | B2 |
| 8742669 | Carter et al. | Jun 2014 | B2 |
| 8773019 | Coumou et al. | Jul 2014 | B2 |
| 8779859 | Su et al. | Jul 2014 | B2 |
| 8781415 | Coumou et al. | Jul 2014 | B1 |
| 8815329 | Ilic et al. | Aug 2014 | B2 |
| 8847561 | Karlieek et al. | Sep 2014 | B2 |
| 8884180 | Ilic et al. | Nov 2014 | B2 |
| 8884525 | Hoffman et al. | Nov 2014 | B2 |
| 8890537 | Valcore, Jr. et al. | Nov 2014 | B2 |
| 8912835 | Nagarkatti et al. | Dec 2014 | B2 |
| 8928329 | Downing et al. | Jan 2015 | B2 |
| 9083343 | Li | Jul 2015 | B1 |
| 9190993 | Li | Nov 2015 | B1 |
| 9306533 | Anton | Apr 2016 | B1 |
| 9425736 | Kelkar | Aug 2016 | B2 |
| 20020060914 | Porter | May 2002 | A1 |
| 20030007372 | Porter | Jan 2003 | A1 |
| 20030046013 | Gerrish | Mar 2003 | A1 |
| 20060170367 | Bhutta | Aug 2006 | A1 |
| 20060198077 | Bhutta | Sep 2006 | A1 |
| 20060232471 | Coumou | Oct 2006 | A1 |
| 20070075784 | Pettersson et al. | Apr 2007 | A1 |
| 20070139122 | Nagarkatti et al. | Jun 2007 | A1 |
| 20080179948 | Nagarkatti et al. | Jul 2008 | A1 |
| 20080180179 | Polizzo | Jul 2008 | A1 |
| 20080197854 | Valcore et al. | Aug 2008 | A1 |
| 20090207537 | Coumou | Aug 2009 | A1 |
| 20100001796 | Sivakumar et al. | Jan 2010 | A1 |
| 20100039194 | Darabi et al. | Feb 2010 | A1 |
| 20100073104 | Cotter et al. | Mar 2010 | A1 |
| 20100123502 | Bhutta et al. | May 2010 | A1 |
| 20100194195 | Coumou et al. | Aug 2010 | A1 |
| 20100201370 | Coumou et al. | Aug 2010 | A1 |
| 20100231296 | Nagarkatti et al. | Sep 2010 | A1 |
| 20100253442 | Mu | Oct 2010 | A1 |
| 20110025436 | Hadji-Abdolhamid et al. | Feb 2011 | A1 |
| 20110241781 | Owen et al. | Oct 2011 | A1 |
| 20110247696 | Zolock et al. | Oct 2011 | A1 |
| 20120001496 | Yamamoto et al. | Jan 2012 | A1 |
| 20120013253 | Coumou | Jan 2012 | A1 |
| 20120062322 | Owen | Mar 2012 | A1 |
| 20120188007 | Van Zyl et al. | Jul 2012 | A1 |
| 20120262064 | Nagarkatti et al. | Oct 2012 | A1 |
| 20130043854 | Tran et al. | Feb 2013 | A1 |
| 20130169359 | Coumou | Jul 2013 | A1 |
| 20130193867 | Van Zyl et al. | Aug 2013 | A1 |
| 20130207738 | Mason | Aug 2013 | A1 |
| 20130222055 | Coumou et al. | Aug 2013 | A1 |
| 20130257311 | Tran et al. | Oct 2013 | A1 |
| 20130314163 | Costa | Nov 2013 | A1 |
| 20130320853 | Carter et al. | Dec 2013 | A1 |
| 20140009248 | Granger-Jones | Jan 2014 | A1 |
| 20140028389 | Coumou | Jan 2014 | A1 |
| 20140028398 | Owen | Jan 2014 | A1 |
| 20140049250 | Brown et al. | Feb 2014 | A1 |
| 20140055034 | Coumou | Feb 2014 | A1 |
| 20140061156 | Brouk et al. | Mar 2014 | A1 |
| 20140062303 | Hoffman et al. | Mar 2014 | A1 |
| 20140097908 | Fisk, II et al. | Apr 2014 | A1 |
| 20140117861 | Finley et al. | May 2014 | A1 |
| 20140117872 | Finley | May 2014 | A1 |
| 20140118031 | Rughoonundon et al. | May 2014 | A1 |
| 20140210345 | Hoffman | Jul 2014 | A1 |
| 20140210551 | Mueller | Jul 2014 | A1 |
| 20140218076 | Coumou et al. | Aug 2014 | A1 |
| 20140220913 | Coumou et al. | Aug 2014 | A1 |
| 20140231243 | Finley | Aug 2014 | A1 |
| 20140232266 | Finley et al. | Aug 2014 | A1 |
| 20140266492 | Radomski et al. | Sep 2014 | A1 |
| 20140306742 | Menzer et al. | Oct 2014 | A1 |
| 20140320013 | Coumou et al. | Oct 2014 | A1 |
| 20150115289 | Fursin et al. | Apr 2015 | A1 |
| 20170063101 | Sultenfuss et al. | Mar 2017 | A1 |
| Number | Date | Country |
|---|---|---|
| 0840349 | May 1998 | EP |
| 0840350 | May 1998 | EP |
| 2006096589 | Sep 2006 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20190272978 A1 | Sep 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62185998 | Jun 2015 | US | |
| 62303625 | Mar 2016 | US | |
| 62424162 | Nov 2016 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15816351 | Nov 2017 | US |
| Child | 16415764 | US | |
| Parent | 15450495 | Mar 2017 | US |
| Child | 15816351 | US | |
| Parent | 15196821 | Jun 2016 | US |
| Child | 15450495 | US |
