In service programmable logic arrays with low tunnel barrier interpoly insulators

Abstract

Structures and methods for in service programmable logic arrays with low tunnel barrier interpoly insulators are provided. The in-service programmable logic array includes a first logic and a second logic plan having a number of logic cells arranged in rows and columns that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. The logic cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, Nb2O5 and/or a Perovskite oxide tunnel barrier.

Description

FIELD OF THE INVENTION

[0002] The present invention relates generally to integrated circuits, and in particular to in-service programmable logic arrays with low tunnel barrier interpoly insulators.

BACKGROUND OF THE INVENTION

[0003] Logic circuits are an integral part of digital systems, such as computers. Essentially, a logic circuit processes a number of inputs to produce a number of outputs for use by the digital system. The inputs and outputs are generally electronic signals that take on one of two “binary” values, a “high” logic value or a “low” logic value. The logic circuit manipulates the inputs using binary logic which describes, in a mathematical way, a given or desired relationship between the inputs and the outputs of the logic circuit.

[0004] Logic circuits that are tailored to the specific needs of a particular customer can be very expensive to fabricate on a commercial basis. Thus, general purpose very large scale integration (VLSI) circuits are defined. VLSI circuits serve as many logic roles as possible, which helps to consolidate desired logic functions. However, random logic circuits are still required to tie the various elements of a digital system together.

[0005] Several schemes are used to implement these random logic circuits. One solution is standard logic, such as transistor-transistor logic (TTL). TTL integrated circuits are versatile because they integrate only a relatively small number of commonly used logic functions. The drawback is that large numbers of TTL integrated circuits are typically required for a specific application. This increases the consumption of power and board space, and drives up the overall cost of the digital system.

[0006] One alternative to standard logic is fully custom logic integrated circuits. Custom logic circuits are precisely tailored to the needs of a specific application. This allows the implementation of specific circuit architectures that dramatically reduces the number of parts required for a system. However, custom logic devices require significantly greater engineering time and effort, which increases the cost to develop these circuits and may also delay the production of the end system.

[0007] A less expensive alternative to custom logic is the “programmable logic array.” Programmable logic arrays take advantage of the fact that complex combinational logic functions can be reduced and simplified into various standard forms. For example, logical functions can be manipulated and reduced down to traditional Sum of Products (SOP) form. In SOP form, a logical function uses just two types of logic functions that are implemented sequentially. This is referred to as two-level logic and can be implemented with various conventional logic functions, e.g., AND-OR, NAND-NAND, NOR-NOR.

[0008] One benefit of the programmable logic array is that it provides a regular, systematic approach to the design of random, combinational logic circuits. A multitude of logical functions can be created from a common building block, e.g., an array of transistors. The logic array is customized or “programmed” by creating a specific metallization pattern to interconnect the various transistors in the array to implement the desired function.

[0009] Programmable logic arrays are fabricated using photolithographic techniques that allow semiconductor and other materials to be manipulated to form integrated circuits as is known in the art. These photolithographic techniques essentially use light that is focused through lenses and masks to define patterns in the materials with microscopic dimensions. The equipment and techniques that are used to implement this photolithography provide a limit for the size of the circuits that can be formed with the materials. Essentially, at some point, the lithography cannot create a fine enough image with sufficient clarity to decrease the size of the elements of the circuit. In other words, there is a minimum dimension that can be achieved through conventional photolithography. This minimum dimension is referred to as the “critical dimension” (CD) or minimum “feature size” (F) of the photolithographic process. The minimum feature size imposes one constraint on the size of the components of a programmable logic array. In order to keep up with the demands for larger programmable logic arrays, designers search for ways to reduce the size of the components of the array.

[0010] As the density requirements become higher and higher in logic and memories it becomes more and more crucial to minimize device area. The programmable logic array (PLA) circuit in the NOR-NOR configuration is one example of an architecture for implementing logic circuits.

[0011] Flash memory cells are one possible solution for high density memory requirements. Flash memories include a single transistor, and with high densities would have the capability of replacing hard disk drive data storage in computer systems. This would result in delicate mechanical systems being replaced by rugged, small and durable solid-state memory packages, and constitute a significant advantage in computer systems. What is required then is a flash memory with the highest possible density or smallest possible cell area.

[0012] Flash memories have become widely accepted in a variety of applications ranging from personal computers, to digital cameras and wireless phones. Both INTEL and AMD have separately each produced about one billion integrated circuit chips in this technology.

[0013] The original EEPROM or EARPROM and flash memory devices described by Toshiba in 1984 used the interploy dielectric insulator for erase. (See generally, F. Masuoka et al., “A new flash EEPROM cell using triple polysilicon technology,” IEEE Int. Electron Devices Meeting, San Francisco, pp. 464-67, 1984; F. Masuoka et al., “256K flash EEPROM using triple polysilicon technology,” IEEE Solid-State Circuits Conf., Philadelphia, pp. 168-169, 1985). Various combinations of silicon oxide and silicon nitride were tried. (See generally, S. Mori et al., “reliable CVD inter-poly dialectics for advanced E&EEPROM,” Symp. On VLSI Technology, Kobe, Japan, pp. 16-17, 1985). However, the rough top surface of the polysilicon floating gate resulted in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.

[0014] Widespread use of flash memories did not occur until the introduction of the ETOX cell by INTEL in 1988. (See generally, U.S. Pat. No. 4,780,424, “Process for fabricating electrically alterable floating gate memory devices,” Oct. 25, 1988; B. Dipert and L. Hebert, “Flash memory goes mainstream,” IEEE Spectrum, pp. 48-51, October, 1993; R. D. Pashley and S. K. Lai, “Flash memories, the best of two worlds,” IEEE Spectrum, pp. 30-33, December 1989). This extremely simple cell and device structure resulted in high densities, high yield in production and low cost. This enabled the widespread use and application of flash memories anywhere a non-volatile memory function is required. However, in order to enable a reasonable write speed the ETOX cell uses channel hot electron injection, the erase operation which can be slower is achieved by Fowler-Nordhiem tunneling from the floating gate to the source. The large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, result in slow write and erase speeds even at very high electric fields. The combination of very high electric fields and damage by hot electron collisions in the oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase.

[0015] Other approaches to resolve the above described problems include; the use of different floating gate materials, e.g. SiC, SiOC, GaN, and GaAIN, which exhibit a lower work function (see FIG. 1A), the use of structured surfaces which increase the localized electric fields (see FIG. 1B), and amorphous SiC gate insulators with larger electron affinity, X, to increase the tunneling probability and reduce erase time (see FIG. 1C).

[0016] One example of the use of different floating gate (FIG. 1A) materials is provided in U.S. Pat. No. 5,801,401 by L. Forbes, entitled “FLASH MEMORY WITH MICROCRYSTALLINE SILICON CARBIDE AS THE FLOATING GATE STRUCTURE.” Another example is provided in U.S. Pat. No. 5,852,306 by L. Forbes, entitled “FLASH MEMORY WITH NANOCRYSTALLINE SILICON FILM AS THE FLOATING GATE.” Still further examples of this approach are provided in pending applications by L. Forbes and K. Ahn, entitled “DYNAMIC RANDOM ACCESS MEMORY OPERATION OF A FLASH MEMORY DEVICE WITH CHARGE STORAGE ON A LOW ELECTRON AFFINITY GaN OR GaAIN FLOATING GATE,” Ser. No. 08/908,098, and “VARIABLE ELECTRON AFFINITY DIAMOND-LIKE COMPOUNDS FOR GATES IN SILICON CMOS MEMORIES AND IMAGING DEVICES,” Ser. No. 08/903,452.

[0017] An example of the use of the structured surface approach (FIG. 1B) is provided in U.S. Pat. No. 5,981,350 by J. Geusic, L. Forbes, and K. Y. Ahn, entitled “DRAM CELLS WITH A STRUCTURE SURFACE USING A SELF STRUCTURED MASK.” Another example is provided in U.S. Pat. No. 6,025,627 by L. Forbes and J. Geusic, entitled “ATOMIC LAYER EXPITAXY GATE INSULATORS AND TEXTURED SURFACES FOR LOW VOLTAGE FLASH MEMORIES.”

[0018] Finally, an example of the use of amorphous SiC gate insulators (FIG. 1C) is provided in U.S. patent application Ser. No. 08/903,453 by L. Forbes and K. Ahn, entitled “GATE INSULATOR FOR SILICON INTEGRATED CIRCUIT TECHNOLOGY BY THE CARBURIZATION OF SILICON.”

[0019] Additionally, graded composition insulators to increase the tunneling probability and reduce erase time have been described by the same inventors. (See, L. Forbes and J. M. Eldridge, “GRADED COMPOSITION GATE INSULATORS TO REDUCE TUNNELING BARRIERS IN FLASH MEMORY DEVICES,” application serial no. ______.

[0020] However, all of these approaches relate to increasing tunneling between the floating gate and the substrate such as is employed in a conventional ETOX device and do not involve tunneling between the control gate and floating gate through and inter-poly dielectric.

[0021] Therefore, there is a need in the art to provide improved in service programmable logic arrays. The in-service programmable logic arrays should provide improved flash memory densities while avoiding the large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, which result in slow write and erase speeds even at very high electric fields. There is also a need to avoid the combination of very high electric fields and damage by hot electron collisions in the which oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase. Further, when using an interpoly dielectric insulator erase approach, the above mentioned problems of having a rough top surface on the polysilicon floating gate which results in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems must be avoided.

SUMMARY OF THE INVENTION

[0022] The above mentioned problems with in service programmable logic arrays and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Systems and methods are provided for in service programmable logic arrays using logic cells, or non-volatile memory cells with metal oxide and/or low tunnel barrier interpoly insulators.

[0023] In one embodiment of the present invention, in service programmable logic arrays with ultra thin vertical body transistors are provided. The in-service programmable logic array includes a first logic plane that receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. A second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function. Each of the logic cells includes includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposing the channel region and is separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5. The floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator. And, the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

[0024] These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIGS. 1A-1C illustrate a number of previous methods for reducing tunneling barriers in Flash memory.

[0026] FIG. 2 illustrates one embodiment of a floating gate transistor, or nonvolatile memory cell, according to the teachings of the present invention.

[0027] FIG. 3 illustrates another embodiment of a floating gate transistor, or nonvolatile memory cell, according to the teachings of the present invention.

[0028] FIG. 4 is a perspective view illustrating an array of silicon pillars formed on a substrate as used in one embodiment according to the teachings of the present invention.

[0029] FIGS. 5A-5E are cross sectional views taken along cut line 5-5 from FIG. 4 illustrating a number of floating gate and control gate configurations which are included in the scope of the present invention.

[0030] FIGS. 6A-6C illustrate a number of address coincidence schemes can be used together with the present invention.

[0031] FIG. 7A is an energy band diagram illustrating the band structure at vacuum level with the low tunnel barrier interpoly insulator according to the teachings of the present invention.

[0032] FIG. 7B is an energy band diagram illustrating the band structure during an erase operation of electrons from the floating gate to the control gate across the low tunnel barrier interpoly insulator according to the teachings of the present invention.

[0033] FIG. 7C is a graph plotting tunneling currents versus the applied electric fields (reciprocal applied electric field shown) for an number of barrier heights.

[0034] FIG. 8 is a schematic diagram illustrating a conventional NOR-NOR programmable logic array.

[0035] FIG. 9 is a schematic diagram illustrating generally an architecture of one embodiment of a novel in-service programmable logic array (PLA) with floating gate transistors, or logic cells, according to the teachings of the present invention.

[0036] FIG. 10 is a simplified block diagram of a high-level organization of an electronic system according to the teachings of the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0037] In the following detailed description of the invention, reference is made to the accompanying drawings which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. The embodiments are intended to describe aspects of the invention in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and changes may be made without departing from the scope of the present invention. In the following description, the terms wafer and substrate are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. The following detailed description is not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0038] The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizonal as defined above. Prepositions, such as “on”, “side” (as in “sidewall”), “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0039] The present invention, describes the use of metal oxide inter-poly dielectric insulators between the control gate and the floating gate. An example is shown in FIG. 2 for a planar structure, or horizontal non-volatile memory cell. According to the teachings of the present invention. The use of metal oxide films for this purpose offer a number of advantages including:

[0040] (i) Flexibility in selecting a range of smooth metal film surfaces and compositions that can be oxidized to form tunnel barrier insulators.

[0041] (ii) Employing simple “low temperature oxidation” to produce oxide films of highly controlled thickness, composition, purity and uniformity.

[0042] (iii) Avoiding inadvertent inter-diffusion of the metal and silicon as well as silicide formation since the oxidation can be carried out at such low temperatures.

[0043] (iv) Using metal oxides that provide desirably lower tunnel barriers, relative to barriers currently used such as SiO2.

[0044] (v) Providing a wide range of higher dielectric constant oxide films with improved capacitance characteristics.

[0045] (vi) Providing a unique ability to precisely tailor tunnel oxide barrier properties for various device designs and applications.

[0046] (vii) Permitting the use of thicker tunnel barriers, if needed, to enhance device performance and its control along with yield and reliability.

[0047] (viii) Developing layered oxide tunnel barriers by oxidizing layered metal film compositions in order, for example, to enhance device yields and reliability more typical of single insulating layers.

[0048] (ix) Eliminating soft erase errors caused by the current technique of tunnel erase from floating gate to the source.

[0049] FIG. 2 illustrates one embodiment of a floating gate transistor, or nonvolatile memory cell 200, according to the teachings of the present invention. As shown in FIG. 2, the non-volatile memory cell 200 includes a first source/drain region 201 and a second source/drain region 203 separated by a channel region 205 in a substrate 206. A floating gate 209 opposes the channel region 205 and is separated therefrom by a gate oxide 211. A control gate 213 opposes the floating gate 209. According to the teachings of the present invention, the control gate 213 is separated from the floating gate 209 by a low tunnel barrier intergate insulator 215.

[0050] In one embodiment of the present invention, low tunnel barrier intergate insulator 215 includes a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al2O3). In an alternative embodiment of the present invention, the low tunnel barrier intergate insulator 215 includes a transition metal oxide and the transition metal oxide is selected from the group consisting of Ta2O5, TiO2, ZrO2, and Nb2O5. In still another alternative embodiment of the present invention, the low tunnel barrier intergate insulator 215 includes a Perovskite oxide tunnel barrier.

[0051] According to the teachings of the present invention, the floating gate 209 includes a polysilicon floating gate 209 having a metal layer 216 formed thereon in contact with the low tunnel barrier intergate insulator 215. Likewise, the control gate 213 includes a polysilicon control gate 213 having a metal layer 217 formed thereon in contact with the low tunnel barrier intergate insulator 215. In this invention, the metal layers, 216 and 217, are formed of the same metal material used to form the metal oxide interpoly insulator 215.

[0052] FIG. 3 illustrates another embodiment of a floating gate transistor, or nonvolatile memory cell 300, according to the teachings of the present invention. As shown in the embodiment of FIG. 3, the non-volatile memory cell 300 includes a vertical non volatile memory cell 300. In this embodiment, the non-volatile memory cell 300 has a first source/drain region 301 formed on a substrate 306. A body region 307 including a channel region 305 is formed on the first source/drain region 301. A second source/drain region 303 is formed on the body region 307. Methods for forming such a vertical transistor structure are disclosed in U.S. Pat. No. 6,135,175, entitled “Memory Address Decode Array with vertical transistors, which is incorporated herein by reference. A floating gate 309 opposes the channel region 305 and is separated therefrom by a gate oxide 311. A control gate 313 opposes the floating gate 309. According to the teachings of the present invention, the control gate 313 is separated from the floating gate 309 by a low tunnel barrier intergate insulator 315.

[0053] According to the teachings of the present invention, the low tunnel barrier intergate insulator 315 includes a metal oxide insulator 315 selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5. In still another alternative embodiment of the present invention, the low tunnel barrier intergate insulator 315 includes a Perovskite oxide tunnel barrier. The floating gate 309 includes a polysilicon floating gate 309 having a metal layer 316 formed thereon in contact with the low tunnel barrier intergate insulator 315. The control gate 313 includes a polysilicon control gate 313 having a metal layer 317 formed thereon in contact with the low tunnel barrier intergate insulator 315.

[0054] As shown in FIG. 3, the floating gate 309 includes a vertical floating gate 309 formed alongside of the body region 307. In the embodiment shown in FIG. 3, the control gate 313 includes a vertical control gate 313 formed alongside of the vertical floating gate 309.

[0055] As will be explained in more detail below, the floating gate 309 and control gate 313 orientation shown in FIG. 3 is just one embodiment for a vertical non volatile memory cell 300, according to the teachings of the present invention. In other embodiments, explained below, the floating gate includes a horizontally oriented floating gate formed alongside of the body region. In this alternative embodiment, the control gate includes a horizontally oriented control gate formed above the horizontally oriented floating gate.

[0056] FIG. 4 is a perspective view illustrating an array of silicon pillars 400-1, 400-2, 400-3, . . . , 400-N, formed on a substrate 406 as used in one embodiment according to the teachings of the present invention. As will be understood by one of ordinary skill in the art upon reading this disclosure, the substrates can be (i) conventional p-type bulk silicon or p-type epitaxial layers on p+ wafers, (ii) silicon on insulator formed by conventional SIMOX, wafer bonding and etch back or silicon on sapphire, or (iii) small islands of silicon on insulator utilizing techniques such as described in more detail in U.S. Pat. No. 5,691,230, by Leonard Forbes, entitled “Technique for Producing Small Islands of Silicon on Insulator,” issued Nov. 25, 1997, which is incorporated herein by reference.

[0057] As shown in FIG. 4, each pillar in the array of silicon pillars 400-1, 400-2, 400-3, . . . , 400-N, includes a first source/drain region 401 and a second source/drain region 403. The first and the second source/drain regions, 401 and 403, are separated by a body region 407 including channel regions 405. As shown in FIG. 4, a number of trenches 430 separate adjacent pillars in the array of silicon pillars 400-1, 400-2, 400-3, . . . , 400-N. Trenches 430 are referenced in connection with the discussion which follows in connection with FIGS. 5A-5E.

[0058] FIGS. 5A-5E are cross sectional views taken along cut line 5-5 from FIG. 4. As mentioned above in connection with FIG. 3, a number of floating gate and control gate configurations are included in the present invention. FIG. 5A illustrates one such embodiment of the present invention. FIG. 5A illustrates a first source/drain region 501 and second source/drain region 503 for a non-volatile memory cell 500 formed according to the teachings of the present invention. As shown in FIG. 5, the first and second source/drain regions, 501 and 503, are contained in a pillar of semiconductor material, and separated by a body region 507 including channel regions 505. As shown in the embodiments of FIGS. 5A-5E, the first source/drain region 501 is integrally connected to a buried sourceline 525. As one or ordinary skill in the art will understand upon reading this disclosure the buried sourceline 525 is be formed of semiconductor material which has the same doping type as the first source/drain region 501. In one embodiment, the sourceline 525 is formed of semiconductor material of the same doping as the first source/drain region 501, but is more heavily doped than the first source/drain region 501.

[0059] As shown in the embodiment of FIG. 5A, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0060] In this embodiment, a single control gate 513 is shared by the pair of floating gates 509-1 and 509-2 on opposing sides of the trench 530. As one of ordinary skill in the art will understand upon reading this disclosure, the shared single control gate 513 can include an integrally formed control gate line. As shown in FIG. 5A, such an integrally formed control gate line 513 can be one of a plurality of control gate lines which are each independently formed in the trench, such as trench 530, below the top surface of the pillars 500-1 and 500-2 and between the pair of floating gates 509-1 and 509-2. In one embodiment, according to the teachings of the present invention, each floating gate, e.g. 509-1 and 509-2, includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

[0061] As shown in the embodiment of FIG. 5B, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0062] In the embodiment of FIG. 5B, a plurality of control gate lines are again formed in trenches, e.g. trench 530, below the top surface of the pillars, 500-1 and 500-2, and between the pair of floating gates 509-1 and 509-2. However, in this embodiment, each trench, e.g. 530, houses a pair of control gate lines, shown as 513-1 and 513-2. Each one of the pair of control gate lines 513-1 and 513-2 addresses the floating gates, 509-1 and 509-2 respectively, on opposing sides of the trench 530. In this embodiment, the pair of control gate lines, or control gates 513-1 and 513-2 are separated by an insulator layer.

[0063] As shown in the embodiment of FIG. 5C, a pair of floating gates 509-1 and 509-2 are again formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0064] In the embodiment of FIG. 5C, the plurality of control gate lines are disposed vertically above the floating gates. That is, in one embodiment, the control gate lines are located above the pair of floating gates 509-1 and 509-2 and not fully beneath the top surface of the pillars 500-1 and 500-2. In the embodiment of FIG. 5C, each pair of floating gates, e.g. 509-1 and 509-2, in a given trench shares a single control gate line, or control gate 513.

[0065] As shown in the embodiment of FIG. 5D, a pair of floating gates 509-1 and 509-2 are formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. Each one of the pair of floating gates, 509-1 and 509-2, respectively opposes the body regions 507-1 and 507-2 in adjacent pillars 500-1 and 500-2 on opposing sides of the trench 530.

[0066] In the embodiment of FIG. 5D, the plurality of control gate lines are disposed vertically above the floating gates. That is, in one embodiment, the control gate lines are located above the pair of floating gates 509-1 and 509-2 and not fully beneath the top surface of the pillars 500-1 and 500-2. However, in the embodiment of FIG. 5D, each one of the pair of floating gates, e.g. 509-1 and 509-2, is addressed by an independent one of the plurality of control lines or control gates, shown in FIG. 5D as 513-1 and 513-2.

[0067] As shown in the embodiment of FIG. 5E, a single floating gate 509 is formed in each trench 530 between adjacent pillars which form memory cells 500-1 and 500-2. According to the teachings of the present invention, the single floating gate 509 can be either a vertically oriented floating gate 509 or a horizontally oriented floating gate 509 formed by conventional processing techniques, or can be a horizontally oriented floating gate 509 formed by a replacement gate technique such as described in a copending application, entitled “Flash Memory with Ultrathin Vertical Body Transistors,” by Leonard Forbes and Kie Y. Ahn, application Ser. No. 09/780,169. In one embodiment of the present invention, the floating gate 509 has a vertical length facing the body region 505 of less than 100 nm. In another embodiment, the floating gate 509 has a vertical length facing the body region 505 of less than 50 nm. In one embodiment, as shown in FIG. 5E, the floating gate 509 is shared, respectively, with the body regions 507-1 and 507-2, including channel regions 505-1 and 505-2, in adjacent pillars 500-1 and 500-2 located on opposing sides of the trench 530. And, as shown in FIG. 5E, the control gate includes a single horizontally oriented control gate line, or control gate 513 formed above the horizontally oriented floating gate 509.

[0068] As one of ordinary skill in the art will understand upon reading this disclosure, in each of the embodiments described above in connection with FIGS. 5A-5E the floating gates 509 are separated from the control gate lines, or control gates 513 with a low tunnel barrier intergate insulator in accordance with the descriptions given above in connection with FIG. 3. The modifications here are to use tunneling through the interpoly dielectric to realize flash memory devices. The vertical devices include an extra flexibility in that the capacitors, e.g. gate oxide and intergate insulator, are easily fabricated with different areas. This readily allows the use of very high dielectric constant inter-poly dielectric insulators with lower tunneling barriers.

[0069] FIGS. 6A-6C illustrate that a number of address coincidence schemes can be used together with the present invention. FIG. 6A illustrates a NOR flash memory array 610 having a number of non-volatile memory cells 600-1, 600-2, 6003, using a coincidence address array scheme. For purposes of illustration, FIG. 6A shows a sourceline 625 coupled to a first source/drain region 601 in each of the number of non-volatile memory cells 600-1, 600-2, 600-3. The sourceline is shown oriented in a first selected direction in the flash memory array 610. In FIG. 6A, a number of control gate lines 630 are shown oriented in a second selected direction in the flash memory array 610. As shown in FIG. 6A, the number of control gate lines 630 are coupled to, or integrally formed with the control gates 613 for the number of non-volatile memory cells 600-1, 600-2, 600-3. As shown in FIG. 6A, the second selected direction is orthogonal to the first selected direction. Finally, FIG. 6A shows a number of bitlines 635 oriented in a third selected direction in the flash memory array 610. As shown in FIG. 6A, the number of bitlines are coupled to the second source/drain regions in the number of non-volatile memory cells 600-1, 600-2, 600-3. In the embodiment shown in FIG. 6A the third selected direction is parallel to the second selected direction and the number of control gate lines 630 serve as address lines. Also, as shown in FIG. 6A, the flash memory array 610 includes a number of backgate or substrate/well bias address lines 640 coupled to the substrate.

[0070] Using FIG. 6A as a reference point, FIGS. 6B-6C illustrate of top view for three different coincidence address scheme layouts suitable for use with the present invention. First, FIG. 6B provides the top view layout of the coincidence address scheme described in connection with FIG. 6A. This is, FIG. 6B illustrates a number of sourcelines 625 oriented in a first selected direction, a number of control gate lines 630 oriented in a second selected direction, and a number of bitlines 635 oriented in a third selected direction for the flash memory array 600. In the embodiment of FIG. 6B, the first selected direction and the third selected direction are parallel to one another and orthogonal to the second selected direction. In this embodiment, the number of control gate lines 630 serve as address lines. According to the teachings of the present invention the output lines, e.g. bitlines 635 must be perpendicular to the address lines, e.g. in this embodiment control gate lines 630

[0071] FIG. 6C provides the top view layout of yet another coincidence address scheme according to the teachings of the present invention. This is, FIG. 6C illustrates a number of sourcelines 625 oriented in a first selected direction, a number of control gate lines 630 oriented in a second selected direction, and a number of bitlines 635 oriented in a third selected direction for the flash memory array 600. In the embodiment of FIG. 6C, the first selected direction and the second selected direction are parallel to one another and orthogonal to the third selected direction. In this embodiment, the number of bitlines 635 serve as address lines. In an alternative embodiment, the sourcelines 625 can include a uniform ground plane as the same will be known and understood by one of ordinary skill in the art.

[0072] As will be apparent to one of ordinary skill in the art upon reading this disclosure, and as will be described in more detail below, write can still be achieved by hot electron injection and/or, according to the teachings of the present invention, tunneling from the control gate. According to the teachings of the present invention, block erase is accomplished by driving the control gates with a relatively large positive voltage and tunneling from the metal on top of the floating gate to the metal on the bottom of the control gate.

[0073] FIG. 7A is an energy band diagram illustrating the band structure at vacuum level with the low tunnel barrier interpoly insulator according to the teachings of the present invention. FIG. 7A is useful in illustrating the reduced tunnel barrier off of the floating gate to the control gate and for illustrating the respective capacitances of the structure according to the teachings of the present invention.

[0074] FIG. 7A shows the band structure of the silicon substrate, e.g. channel region 701, silicon dioxide gate insulator, e.g. gate oxide 703, polysilicon floating gate 705, the low tunnel barrier interpoly dielectric 707, between metal plates 709 and 711, and then the polysilicon control gate 713, according to the teachings of the present invention.

[0075] The design considerations involved are determined by the dielectric constant, thickness and tunneling barrier height of the interpoly dielectric insulator 707 relative to that of the silicon dioxide gate insulator, e.g. gate oxide 703. The tunneling probability through the interpoly dielectric 707 is an exponential function of both the barrier height and the electric field across this dielectric.

[0076] FIG. 7B is an energy band diagram illustrating the band structure during an erase operation of electrons from the floating gate 705 to the control gate 713 across the low tunnel barrier interpoly insulator 707 according to the teachings of the present invention. FIG. 7B is similarly useful in illustrating the reduced tunnel barrier off of the floating gate to the control gate and for illustrating the respective capacitances of the structure according to the teachings of the present invention.

[0077] As shown in FIG. 7B, the electric field is determined by the total voltage difference across the structure, the ratio of the capacitances (see FIG. 7A), and the thickness of the interpoly dielectric 707. The voltage across the interpoly dielectric 707 will be, ΔV2=V C1/(C1+C2), where V is the total applied voltage. The capacitances, C, of the structures depends on the dielectric constant, ∈r, or the permittivity of free space, eo, and the thickness of the insulating layers, t, and area, A, such that C=∈r ∈o A/t, Farads/cm2, where ∈r represents the low frequency dielectric constant. The electric field across the interpoly dielectric insulator 707, having capacitance, C2, will then be E2=ΔV2/t2, where t2 is the thickness of this layer.

[0078] The tunneling current in erasing charge from the floating gate 705 by tunneling to the control gate 713 will then be as shown in FIG. 7B given by an equation of the form:

J=B exp (−Eo/E)

[0079] where E is the electric field across the interpoly dielectric insulator 707 and Eo depends on the barrier height. Practical values of current densities for aluminum oxide which has a current density of 1 A/cm2 at a field of about E=1V/20A=5×10+6 V/cm are evidenced in a description by Pollack. (See generally, S. R. Pollack and C. E. Morris, “Tunneling through gaseous oxidized films of Al2O3,” Trans. AIME, Vol. 233, p. 497, 1965). Practical current densities for silicon oxide transistor gate insulators which has a current density of 1 A/cm2 at a field of about E=2.3V/23A=1×10+7 V/cm are evidenced in a description by T. P. Ma et al. (See generally, T. P. Ma et al., “Tunneling leakage current in ultrathin (<a4 nm) nitride/oxide stack dielectrics,” IEEE Electron Device Letters, vol. 19, no. 10, pp. 388-390, 1998).

[0080] The lower electric field in the aluminum oxide interpoly insulator 707 for the same current density reflects the lower tunneling barrier of less than 2 eV, shown in FIG. 7B, as opposed to the 3.2 eV tunneling barrier of silicon oxide 703, also illustrated in FIG. 7B.

[0081] FIG. 7C is a graph plotting tunneling currents versus the applied electric fields (reciprocal applied electric field shown) for an number of barrier heights. FIG. 7C illustrates the dependence of the tunneling currents on electric field (reciprocal applied electric field) and barrier height. The fraction of voltage across the interpoly or intergate insulator, ΔV2, can be increased by making the area of the intergate capacitor, C2, (e.g. intergate insulator 707) smaller than the area of the transistor gate capacitor, C1 (e.g. gate oxide 703). This would be required with high dielectric constant intergate dielectric insulators 707 and is easily realized with the vertical floating gate structures described above in connection with FIGS. 3, and 5A-5E.

[0082] Methods of Formation

[0083] Several examples are outlined below in order to illustrate how a diversity of such metal oxide tunnel barriers can be formed, according to the teachings of the present invention. Processing details and precise pathways taken which are not expressly set forth below will be obvious to one of ordinary skill in the art upon reading this disclosure. Firstly, although not included in the details below, it is important also to take into account the following processing factors in connection with the present invention:

[0084] (i) The poly-Si layer is to be formed with emphasis on obtaining a surface that is very smooth and morphologically stable at subsequent device processing temperatures which will exceed that used to grow Metal oxide.

[0085] (ii) The native SiOx oxide on the poly-Si surface must be removed (e.g., by sputter cleaning in an inert gas plasma in situ) just prior to depositing the metal film. The electrical characteristics of the resultant Poly-Si/Metal/Metal oxide/Metal/Poly-Si structure will be better defined and reproducible than that of a Poly-Si/Native SiOx/Metal/Metal oxide/Poly-Si structure.

[0086] (iii) The oxide growth rate and limiting thickness will increase with oxidation temperature and oxygen pressure. The oxidation kinetics of a metal may, in some cases, depend on the crystallographic orientations of the very small grains of metal which comprise the metal film (see generally, O, Kubaschewski and B. E. Hopkins, “Oxidation of Metals and Alloys”, Butterworth, London, pp. 53-64, 1962). If such effects are significant, the metal deposition process can be modified in order to increase its preferred orientation and subsequent oxide thickness and tunneling uniformity. To this end, use can be made of the fact that metal films strongly prefer to grow during their depositions having their lowest free energy planes parallel to the film surface. This preference varies with the crystal structure of the metal. For example, fcc metals prefer to form {111} surface plans. Metal orientation effects, if present, would be larger when only a limited fraction of the metal will be oxidized and unimportant when all or most of the metal is oxidized.

[0087] (iv) Modifications in the structure shown in FIG. 2 may be introduced in order to compensate for certain properties in some metal/oxide/metal layers. Such changes are reasonable since a wide range of metals, alloys and oxides with quite different physical and chemical properties can be used to form these tunnel junctions.

EXAMPLE I

Formation of PbO Tunnel Barriers

[0088] This oxide barrier has been studied in detail using Pb/PbO/Pb structures. The oxide itself can be grown very controllably on deposited lead films using either thermal oxidation (see generally, J. M. Eldridge and J. Matisoo, “Measurement of tunnel current density in a Meal-Oxide-Metal system as a function of oxide thickness,” Proc. 12th Intern. Conf. on Low Temperature Physics, pp. 427-428, 1971; J. M. Eldridge and D. W. Dong, “Growth of thin PbO layers on lead films. I. Experiment,” Surface Science, Vol. 40, pp. 512-530, 1973) or rf sputter etching in an oxygen plasma (see generally, J. H. Greiner, “Oxidation of lead films by rf sputter etching in an oxygen plasma”, J. Appl. Phys., Vol. 45, No. 1, pp. 32-37, 1974). It will be seen that there are a number of possible variations on this structure. Starting with a clean poly-Si substrate, one processing sequence using thermal oxidation involves:

[0089] (i) Depositing a clean lead film on the poly-Si floating gate at ˜25 to 75° C. in a clean vacuum system having a base pressure of ˜10−8 Torr or lower. The Pb film will be very thin with a thickness within 1 or 2A of its target value.

[0090] (ii) Lead and other metal films can be deposited by various means including physical sputtering and/or from a Knudsen evaporation cell. The sputtering process also offers the ability to produce smoother films by increasing the re-sputtering-to-deposition ratio since re-sputtering preferentially reduces geometric high points of the film.

[0091] (iii) Using a “low temperature oxidation process” to grow an oxide film of self-limited thickness. In this case, oxygen gas is introduced at the desired pressure in order to oxidize the lead in situ without an intervening exposure to ambient air. For a fixed oxygen pressure and temperature, the PbO thickness increases with log(time). Its thickness can be controlled via time or other parameters to within 0.10 A, as determined via in situ ellipsometric or ex situ measurements of Josephson tunneling currents. This control is demonstrated by the very limited statistical scatter of the current PbO thickness data shown in the insert of FIG. 3 in an article by J. M. Eldridge and J. Matisoo, entitled “Measurement of tunnel current density in a Meal-Oxide-Metal system as a function of oxide thickness,” Proc. 12th Intern. Conf. on Low Temperature Physics, pp. 427-428, 1971. This remarkable degree of control over tunnel current is due to the excellent control over PbO thickness that can be achieved by “low temperature oxidation.” For example, increasing the oxidation time from 100 to 1,000 minutes at an oxygen pressure of 750 Torr at 25C only raises the PbO thickness by 3 A (e.g., from ˜21 to 24 A, see FIG. 1 in J. M. Eldridge and J. Matisoo, “Measurement of tunnel current density in a Meal-Oxide-Metal system as a function of oxide thickness,” Proc. 12th Intern. Conf. on Low Temperature Physics, pp. 427-428, 1971). Accordingly, controlling the oxidation time to within 1 out of a nominal 100 minute total oxidation time provides a thickness that is within 0.1 A of 21A. The PbO has a highly stoichiometric composition throughout its thickness, as evidenced from ellipsometry (e.g., see FIG. 6 in J. M. Eldridge and D. W. Dong, “Growth of thin PbO layers on lead films. I. Experiment,” Surface Science, Vol. 40, pp. 512-530, 1973) and the fact that the tunnel barrier heights are identical for Pb/PbO/Pb structures.

[0092] (iv) Re-evacuate the system and deposit the top lead electrode. This produces a tunnel structure having virtually identical tunnel barriers at both Pb/O interfaces.

[0093] (v) The temperature used to subsequently deposit the Poly-Si control gate must be held below the melting temperature (327C) of lead. The PbO itself is stable (up to ˜500C or higher) and thus introduces no temperature constraint on subsequent processes. One may optionally oxidize the lead film to completion, thereby circumventing the low melting temperature of metallic lead. In this case, one would form a Poly-Si/PbO/Poly-Si tunnel structure having an altered tunnel barrier for charge injection. Yet another variation out of several would involve: oxidizing the lead film to completion; replacing the top lead electrode with a higher melting metal such as Al; and, then adding the poly-Si control layer. This junction would have asymmetrical tunneling behavior due to the difference in barrier heights between the Pb/PbO and PbO/Al electrodes.

EXAMPLE II

Formation of Al2O3 Tunnel Barriers

[0094] A number of studies have dealt with electron tunneling in Al/Al2O3/Al structures where the oxide was grown by “low temperature oxidation” in either molecular or plasma oxygen (see generally, S. M. Sze, Physics of Semiconductor Devices, Wiley, N.Y., pp. 553-556, 1981; G. Simmons and A. El-Badry, “Generalized formula for the electric tunnel effect between similar electrodes separated by a thin insulating film,” J. Appl. Phys., Vol. 34, p. 1793, 1963; S. R. Pollack and C. E. Morris, “Tunneling through gaseous oxidized films of Al2O3,” Trans. AIME, Vol. 233, p. 497, 1965; Z. Hurych, “Influence of nonuniform thickness of dielectric layers on capacitance and tunnel currents,” Solid-State Electronics, Vol. 9, p. 967, 1966; S. P. S. Arya and H. P. Singh, “Conduction properties of thin Al2O3 films,” Thin Solid Films, Vol. 91, No. 4, pp. 363-374, May 1982; K. -H. Gundlach and J. Holzl, “Logarithmic conductivity of Al—Al2O3—Al tunneling junctions produced by plasma- and by thermal-oxidation”, surface Science, Vol. 27, pp. 125-141, 1971). Before sketching out a processing sequence for these tunnel barriers, note:

[0095] (i) Capacitance and tunnel measurements indicate that the Al2O3 thickness increases with the log (oxidation time), similar to that found for PbO/Pb as well as a great many other oxide/metal systems.

[0096] (ii) Tunnel currents are asymmetrical in this system with somewhat larger currents flowing when electrons are injected from Al/Al2O3 interface developed during oxide growth. This asymmetry is due to a minor change in composition of the growing oxide: there is a small concentration of excess metal in the Al2O3, the concentration of which diminishes as the oxide is grown thicker. The excess Al+3 ions produce a space charge that lowers the tunnel barrier at the inner interface. The oxide composition at the outer Al2O3/Al contact is much more stoichiometric and thus has a higher tunnel barrier. In situ ellipsometer measurements on the thermal oxidation of Al films deposited and oxidized in situ support this model (see generally, J. Grimblot and J. M. Eldridge, “I. Interaction of Al films with O2 at low pressures”, J. Electro. Chem. Soc., Vol. 129, No. 10, pp. 2366-2368, 1982. J. Grimblot and J. M. Eldridge, “II. Oxidation of Al films”, ibid, 2369-2372, 1982). In spite of this minor complication, Al/Al2O3/Al tunnel barriers can be formed that will produce predictable and highly controllable tunnel currents that can be ejected from either electrode. The magnitude of the currents are still primarily dominated by Al2O3 thickness which can be controlled via the oxidation parametrics.

[0097] With this background, we can proceed to outline one process path out of several that can be used to form Al2O3 tunnel barriers. Here the aluminum is thermally oxidized although one could use other techniques such as plasma oxidation (see generally, S. R. Pollack and C. E. Morris, “Tunneling through gaseous oxidized films of Al2O3,” Trans. AIME, Vol. 233, p. 497, 1965; K. -H. Gundlach and J. Holzl, “Logarithmic conductivity of Al—Al2O3—Al tunneling junctions produced by plasma- and by thermal-oxidation”, Surface Science, Vol. 27, pp. 125-141, 1971) or rf sputtering in an oxygen plasma (see generally, J. H. Greiner, “Oxidation of lead films by rf sputter etching in an oxygen plasma”, J. Appl. Phys., Vol. 45, No. 1, pp. 32-37, 1974). For the sake of brevity, some details noted above will not be repeated. The formation of the Al/Al2O3/Al structures will be seen to be simpler than that described for the Pb/PbO/Pb junctions owing to the much higher melting point of aluminum, relative to lead.

[0098] (i) Sputter deposit aluminum on poly-Si at a temperature of ˜25 to 150C. Due to thermodynamic forces, the micro-crystallites of the f.c.c. aluminum will have a strong and desirable (111) preferred orientation.

[0099] (ii) Oxidize the aluminum in situ in molecular oxygen using temperatures, pressure and time to obtain the desired Al2O3 thickness. As with PbO, the thickness increases with log (time) and can be controlled via time at a fixed oxygen pressure and temperature to within 0.10 Angstroms, when averaged over a large number of aluminum grains that are present under the counter-electrode. One can readily change the Al2O3 thickness from ˜15 to 35A by using appropriate oxidation parametrics (e.g., see FIG. 2 in J. Grimblot and J. M. Eldridge, “II. Oxidation of Al films”, J. Electro. Chem. Soc., Vol. 129, No. 10, pp. 2369-2372, 1982). The oxide will be amorphous and remain so until temperatures in excess of 400C are reached. The initiation of recrystallization and grain growth can be suppressed, if desired, via the addition of small amounts of glass forming elements (e.g., Si) without altering the growth kinetics or barrier heights significantly.

[0100] (iii) Re-evacuate the system and deposit a second layer of aluminum.

[0101] (iv) Deposit the Poly-Si control gate layer using conventional processes.

EXAMPLE III

Formation of Single- and Multi-Layer Transition Metal Oxide Tunnel Barriers

[0102] Single layers of Ta2O5, TiO2, ZrO2, Nb2O5 and similar transition metal oxides can be formed by “low temperature oxidation” of numerous Transition Metal (e.g., TM oxides) films in molecular and plasma oxygen and also by rf sputtering in an oxygen plasma. The thermal oxidation kinetics of these metals have been studied for decades with numerous descriptions and references to be found in the book by Kubaschewski and Hopkins (O. Kubaschewski and B. E. Hopkins, “Oxidation of Metals and Alloys”, Butterworth, London, pp. 53-64, 1962). In essence, such metals oxidize via logarithmic kinetics to reach thicknesses of a few to several tens of angstroms in the range of 100 to 300C. Excellent oxide barriers for Josephson tunnel devices can be formed by rf sputter etching these metals in an oxygen plasma (see generally, J. M. Greiner, “Josephson tunneling barriers by rf sputter etching in an oxygen plasma,” J. Appl. Phys., Vol. 42, No. 12, pp. 5151-5155, 1971; O. Michikami et al., “Method of fabrication of Josephson tunnel junctions,” U.S. Pat. No. 4,412,902, Nov. 1, 1983). Such “low temperature oxidation” approaches differ considerably from MOCVD processes used to produce these TM oxides. MOCVD films require high temperature oxidation treatments to remove carbon impurities, improve oxide stoichiometry and produce recrystallization. Such high temperature treatments also cause unwanted interactions between the oxide and the underlying silicon and thus have necessitated the introduction of interfacial barrier layers. See, for example, H. F. Luan et al., “High quality Ta2O5 gate dielectrics with Tox,eq<10 angstroms,” IEDM Tech. Digest, pp. 141-144, 1999.

[0103] A new approach was described in a copending application by J. M. Eldridge, entitled “Thin Dielectric Films for DRAM Storage Capacitors,” patent application Ser. No. 09/651,380 filed Aug. 29, 2000 that utilizes “low temperature oxidation” to form duplex layers of TM oxides. Unlike MOCVD films, the oxides are very pure and stoichiometric as formed. They do require at least a brief high temperature (est. 700 to 800C but may be lower) treatment to transform their microstructures from amorphous to crystalline and thus increase their dielectric constants to the desired values (>20 or so). Unlike MOCVD oxides, this treatment can be carried out in an inert gas atmosphere, thus lessening the possibility of inadvertently oxidizing the poly-Si floating gate. While this earlier disclosure was directed at developing methods and procedures for producing high dielectric constant films for storage cells for DRAMs, the same teachings can be applied to producing thinner metal oxide tunnel films for the flash memory devices described in this disclosure. The dielectric constants of these TM oxides are substantially greater (>25 to 30 or more) than those of PbO and Al2O3. Duplex layers of these high dielectric constant oxide films are easily fabricated with simple tools and also provide improvement in device yields and reliability. Each oxide layer will contain some level of defects but the probability that such defects will overlap is exceedingly small. Effects of such duplex layers were first reported by one J. M. Eldridge of the present authors and are well known to practitioners of the art. It is worth mentioning that highly reproducible TM oxide tunnel barriers can be grown by rf sputtering in an oxygen ambient, as referenced above (see generally, J. M. Greiner, “Josephson tunneling barriers by rf sputter etching in an oxygen plasma,” J. Appl. Phys., Vol. 42, No. 12, pp. 5151-5155, 1971; O. Michikami et al., “Method of fabrication of Josephson tunnel junctions,” U.S. Pat. No. 4,412,902, Nov. 1, 1983). Control over oxide thickness and other properties in these studies were all the more remarkable in view of the fact that the oxides were typically grown on thick (e.g., 5,000 A) metals such as Nb and Ta. In such metal-oxide systems, a range of layers and suboxides can also form, each having their own properties. In the present disclosure, control over the properties of the various TM oxides will be even better since we employ very limited (perhaps 10 to 100 A or so) thicknesses of metal and thereby preclude the formation of significant quantities of unwanted, less controllable sub-oxide films. Thermodynamic forces will drive the oxide compositions to their most stable, fully oxidized state, e.g., Nb2O5, Ta2O5, etc. As noted above, it will still be necessary to crystallize these duplex oxide layers. Such treatments can be done by RTP and will be shorter than those used on MOCVD and sputter-deposited oxides since the stoichiometry and purity of the “low temperature oxides” need not be adjusted at high temperature.

[0104] Fairly detailed descriptions for producing thicker duplex layers of TM oxides have been given in the copending application by J. M. Eldridge, entitled “Thin Dielectric Films for DRAM Storage Capacitors,” patent application Ser. No. 09/651,380 filed Aug. 29, 2000, so there is no need to repeat them here. Although perhaps obvious to those skilled in the art, one can sketch out a few useful fabrication guides:

[0105] (i) Thinner TM layers will be used in this invention relative to those used to form DRAMs. Unlike DRAMs where leakage must be eliminated, the duplex oxides used here must be thin enough to carry very controlled levels of current flow when subjected to reasonable applied fields and times.

[0106] (ii) The TM and their oxides are highly refractory and etchable (e.g., by RIE). Hence they are quite compatible with poly-Si control gate processes and other subsequent steps.

[0107] (iii) TM silicide formation will not occur during the oxidation step. It could take place at a significant rate at the temperatures used to deposit the poly-Si control gate. If so, several solutions can be applied including:

[0108] (i) Insert certain metals at the TM/poly-Si boundaries that will prevent inter-diffusion of the TM and the poly-Si.

[0109] (ii) Completely oxide the TMs. The electrical characteristics of the resulting poly-Si/TM oxide 1/TM oxide 2/poly-Si structure will be different in the absence of having TM at the oxide/metal interfaces.

EXAMPLE IV

Formation of Alternate Metal Compound Tunnel Barriers

[0110] Although no applications may be immediately obvious, it is conceivable that one might want to form a stack of oxide films having quite different properties, for example, a stack comprised of a high dielectric constant (k) oxide/a low k oxide/a high k oxide. “Low temperature oxidation” can be used to form numerous variations of such structures. While most of this disclosure deals with the formation and use of stacks of oxide dielectrics, it is also possible to use “low temperature oxidation” to form other thin film dielectrics such as nitrides, oxynitrides, etc. that could provide additional functions such as being altered by monochromatic light, etc. These will not be discussed further here.

EXAMPLE V

Formation of Perovskite Oxide Tunnel Barriers

[0111] Some results have been obtained which demonstrate that at least a limited range of high temperature, super-conducting oxide films can be made by thermally oxidizing Y—Ba—Cu alloy films (see generally, Hase et al., “Method of manufacturing an oxide superconducting film,” U.S. Pat. No. 5,350,738, Sept. 27, 1994). The present inventors have also disclosed how to employ “low temperature oxidation” and short thermal treatments in an inert ambient at 700C in order to form a range of perovskite oxide films from parent alloy films (see generally, J. M. Eldridge, “Low Cost Processes for Producing High Quality Perovskite Dielectric Films,” application Ser. No. ______). The dielectric constants of crystallized, perovskite oxides can be very large, with values in the 100 to 1000 or more range. The basic process is more complicated than that needed to oxidize layered films of transition metals. (See Example III.) The TM layers would typically be pure metals although they could be alloyed. The TMs are similar metallurgically as are their oxides. In contrast, the parent alloy films that can be converted to a perovskite oxide are typically comprised of metals having widely different chemical reactivities with oxygen and other common gasses. In the Y—Ba—Cu system referenced above, Y and Ba are among the most reactive of metals while the reactivity of Cu approaches (albeit distantly) those of other noble metals. If the alloy is to be completely oxidized, then thin film barriers such as Pd, Pt, etc. or their conductive oxides must be added between the Si and the parent metal film to serve as: electrical contact layers; diffusion barriers; and, oxidation stops. In such a case, the Schottky barrier heights of various TM oxides and perovskite oxides in contact with various metals will help in the design of the tunnel device. In the more likely event that the perovskite parent alloy film will be only partially converted to oxide and then covered with a second layer of the parent alloy (recall the structure of FIG. 2), then the barrier heights will represent that developed during oxide growth at the parent perovskite alloy/perovskite oxide interface. Obviously, such barrier heights cannot be predicted ab initio for such a wide class of materials but will have to be developed as the need arises. This information will have to be developed on a system-by-system basis.

[0112] Methods of Operation

[0113] Write Operation

[0114] Write can be achieved by the normal channel hot electron injection and gate current through the silicon oxide to the floating gate. This is done by selecting a particular column by applying a high control gate voltage and applying relatively large drain voltage as is done with conventional ETOX flash memory devices. However, according to the teachings of the present invention, write can also be accomplished by applying a positive voltage to the substrate or well select line and a large negative voltage to the control gates, electrons will tunnel from the control gate to the floating gate. The low tunnel barrier will provide an easy write operation and the selection of the substrate or well bias will provide selectivity and address only one device.

[0115] Erase Operation

[0116] According to the teachings of the present invention, erase is achieved by providing a negative voltage to the substrate or well address line and a large positive voltage to the control gate. This causes electrons to tunnel off of the floating gate on to the control gate. A whole row can be erased by addressing all the column lines along that row and a block can be erased by addressing multiple row back gate or substrate/well address lines.

[0117] Read Operation

[0118] Read is accomplished as in conventional ETOX flash memory devices. A column line is addressed by applying a positive control gate voltage and sensing the current along the data bit or drain row address line.

[0119] System Level

[0120] FIG. 8 shows a conventional NOR-NOR logic array 800 which is programmable at the gate mask level by either fabricating a thin oxide gate transistor, e.g. logic cells 801-1, 801-2, . . . , 801-N and 803-1, 803-2, . . . , 803-N, at the intersection of lines in the array or not fabricating a thin oxide gate transistor, e.g. missing thin oxide transistors, 802-1, 802-2, . . . , 802-N, at such an intersection. As one of ordinary skill in the art will understand upon reading this disclosure, the same technique is conventionally used to form other types of logic arrays not shown. As shown in FIG. 8, a number of depletion mode NMOS transistors, 816 and 818 respectively, are used as load devices.

[0121] The conventional logic array shown in FIG. 8 includes a first logic plane 810 which receives a number of input signals at input lines 812. In this example, no inverters are provided for generating complements of the input signals. However, first logic plane 810 can include inverters to produce the complementary signals when needed in a specific application.

[0122] First logic plane 810 includes a number of thin oxide gate transistors, e.g. transistors 801-1, 801-2, . . . , 801-N. The thin oxide gate transistors, 801-1, 801-2, . . . , 801-N, are located at the intersection of input lines 812, and interconnect lines 814. In the conventional PLA of FIG. 8, this selective fabrication of thin oxide gate transistor, e.g. transistors 801-1, 801-2, . . . , 801-N, is referred to as programming since the logical function implemented by the programmable logic array is entered into the array by the selective arrangement of the thin oxide gate transistors, or logic cells, 801-1, 801-2, . . . , 801-N, at the intersections of input lines 812, and interconnect lines 814 in the array.

[0123] In this embodiment, each of the interconnect lines 814 acts as a NOR gate for the input lines 812 that are connected to the interconnect lines 814 through the thin oxide gate transistors, 801-1, 801-2, . . . , 801-N, of the array. For example, interconnection line 814A acts as a NOR gate for the signals on input lines 812A and 812B. That is, interconnect line 814A is maintained at a high potential unless one or more of the thin oxide gate transistors, 801-1, 801-2, . . . , 801-N, that are coupled to interconnect line 814A are turned on by a high logic level signal on one of the input lines 812. When a control gate address is activated, through input lines 812, each thin oxide gate transistor, e.g. transistors 801-1, 801-2, . . . , 801-N, conducts which performs the NOR positive logic circuit function, an inversion of the OR circuit function results from inversion of data onto the interconnect lines 814 through the thin oxide gate transistors, 801-1, 801-2, . . . , 801-N, of the array.

[0124] As shown in FIG. 8, a second logic plane 824 is provided which includes a number of thin oxide gate transistor, e.g. transistors 803-1, 803-2, . . . , 803-N. The thin oxide gate transistors, 803-1, 803-2, . . . , 803-N, are located at the intersection of interconnect lines 814, and output lines 820. Here again, the logical function of the second logic plane 824 is implemented by the selective arrangement of the thin oxide gate transistors, 803-1, 803-2, . . . , 803-N, at the intersections of interconnect lines 814, and output lines 820 in the second logic plane 824. The second logic plane 824 is also configured such that the output lines 820 comprise a logical NOR function of the signals from the interconnection lines 814 that are coupled to particular output lines 820 through the thin oxide gate transistors, 803-1, 803-2, . . . , 803-N, of the second logic plane 824. Thus, in FIG. 8, the incoming signals on each line are used to drive the gates of transistors in the NOR logic array as the same is known by one of ordinary skill in the art and will be understood by reading this disclosure.

[0125] FIG. 9 illustrates an embodiment of a novel in-service programmable logic array (PLA) formed according to the teachings of the present invention. In FIG. 9, PLA 900 implements an illustrative logical function using a two level logic approach. Specifically, PLA 900 includes first and second logic planes 910 and 922. In this example, the logic function is implemented using NOR-NOR logic. As shown in FIG. 9, first and second logic planes 910 and 922 each include an array of, logic cells, non-volatile memory cells, or floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N respectively, formed according to the teachings of the present invention. The floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N, have their first source/drain regions coupled to source lines or a conductive source plane, as shown and described in more detail in connection with FIGS. 2 and 7C. These floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N are configured to implement the logical function of FPLA 900. The floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N are shown as n-channel floating gate transistors. However, the invention is not so limited. Also, as shown in FIG. 9, a number of p-channel metal oxide semiconductor (PMOS) transistors are provided as load device transistors, 916 and 924 respectively, having their source regions coupled to a voltage potential (VDD). These load device transistors, 916 and 924 respectively, operate in complement to the floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N to form load inverters.

[0126] It is noted that the configuration of FIG. 9 is provided by way of example and not by way of limitation. Specifically, the teachings of the present application are not limited to programmable logic arrays in the NOR-NOR approach. Further, the teachings of the present application are not limited to the specific logical function shown in FIG. 9. Other logical functions can be implemented in a programmable logic array, with the floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N and load device transistors, 916 and 924 respectively, of the present invention, using any one of the various two level logic approaches.

[0127] First logic plane 910 receives a number of input signals at input lines 912. In this example, no inverters are provided for generating complements of the input signals. However, first logic plane 910 can include inverters to produce the complementary signals when needed in a specific application.

[0128] First logic plane 910 includes a number of floating gate driver transistors, 901-1, 901-2, . . . , 901-N, that form an array such as an array of non-volatile memory cells, or flash memory cells. The floating gate driver transistors, 901-1, 901-2, . . . , 901-N, are located at the intersection of input lines 912, and interconnect lines 914. Not all of the floating gate driver transistors, 901-1, 901-2, . . . , 901-N, are operatively conductive in the first logic plane. Rather, the floating gate driver transistors, 901-1, 901-2, . . . , 901-N, are selectively programmed, as described in detail below, to respond to the input lines 912 and change the potential of the interconnect lines 914 so as to implement a desired logic function. This selective interconnection is referred to as programming since the logical function implemented by the programmable logic array is entered into the array by the floating gate driver transistors, 901-1, 901-2, . . . , 901-N, that are used at the intersections of input lines 912, and interconnect lines 914 in the array.

[0129] In this embodiment, each of the interconnect lines 914 acts as a NOR gate for the input lines 912 that are connected to the interconnect lines 914 through the floating gate driver transistors, 901-1, 901-2, . . . , 901-N, of the array 900. For example, interconnection line 914A acts as a NOR gate for the signals on input lines 912A, 912B and 912C. Programmability of the vertical floating gate driver transistors, 901-1, 901-2, . . . , 901-N is achieved by charging the vertical floating gates. When the vertical floating gate is charged, that floating gate driver transistor, 901-1, 901-2, . . . , 901-N will remain in an off state until it is reprogrammed. Applying and removing a charge to the vertical floating gates is performed by tunneling charge between the floating gate and control gates of the floating gate driver transistors, 901-1, 901-2, . . . , 901-N through a low tunnel barrier interpoly, or intergate insulator as described in detail above and in connection with FIGS. 2-7C. A floating gate driver transistors, 901-1, 901-2, . . . , 901-N programmed in an off state remains in that state until the charge is removed from its vertical floating gate.

[0130] Floating gate driver transistors, 901-1, 901-2, . . . , 901-N not having a corresponding vertical floating gate charged operate in either an on state or an off state, wherein input signals received by the input lines 912A, 912B and 912C determine the applicable state. If any of the input lines 912A, 912B and 912C are turned on by input signals received by the input lines 912A, 912B and 912C, then a ground is provided to load device transistors 916. The load device transistors 916 are attached to the interconnect lines 914. The load device transistors 916 provide a low voltage level when any one of the floating gate driver transistors, 901-1, 901-2, . . . , 901-N connected to the corresponding interconnect line 914 is activated. This performs the NOR logic circuit function, an inversion of the OR circuit function results from inversion of data onto the interconnect lines 914 through the floating gate driver transistors, 901-1, 901-2, . . . , 901-N of the array 900. When the floating gate driver transistors, 901-1, 901-2, . . . , 901-N are in an off state, an open is provided to the drain of the load device transistors 916. The VDD voltage level is applied to corresponding input lines, e.g. the interconnect lines 914 for second logic plane 922 when a load device transistors 916 is turned on by a clock signal received at the gate of the load device transistors 916 (Φ). Each of the floating gate driver transistors, 901-1, 901-2, . . . , 901-N described herein are formed according to the teachings of the present invention as described in detail in connection with FIGS. 2-7C.

[0131] In a similar manner, second logic plane 922 comprises a second array of floating gate driver transistors, 902-1, 902-2, . . . , 902-N that are selectively programmed to provide the second level of the two level logic needed to implement a specific logical function. In this embodiment, the array of floating gate driver transistors, 902-1, 902-2, . . . , 902-N is also configured such that the output lines 920 comprise a logical NOR function of the signals from the interconnection lines 914 that are coupled to particular output lines 920 through the floating gate driver transistors, 902-1, 902-2, . . . , 902-N of the second logic plane 922.

[0132] Programmability of the vertical floating gate driver transistors, 902-1, 902-2, . . . , 902-N is achieved by charging the vertical floating gate. When the vertical floating gate is charged, that floating gate driver transistor, 902-1, 902-2, . . . , 902-N will remain in an off state until it is reprogrammed. Applying and removing a charge to the vertical floating gates is performed by tunneling charge between the floating gate and control gates of the floating gate driver transistors, 901-1, 901-2, . . . , 901-N through a low tunnel barrier interpoly, or intergate insulator as described in detail above and in connection with FIGS. 2-7C. A floating gate driver transistors, 902-1, 902-2, . . . , 902-N programmed in an off state remains in that state until the charge is removed from the vertical floating gate.

[0133] Floating gate driver transistors, 902-1, 902-2, . . . , 902-N not having a corresponding vertical floating gate charged operate in either an on state or an off state, wherein signals received by the interconnect lines 914 determine the applicable state. If any of the interconnect lines 914 are turned on, then a ground is provided to load device transistors 924 by applying a ground potential to the source line or conductive source plane coupled to the transistors first source/drain region as described herein. The load device transistors 924 are attached to the output lines 920. The load device transistors 924 provide a low voltage level when any one of the floating gate driver transistors, 902-1, 902-2, . . . , 902-N connected to the corresponding output line is activated. This performs the NOR logic circuit function, an inversion of the OR circuit function results from inversion of data onto the output lines 920 through the floating gate driver transistors, 902-1, 902-2, . . . , 902-N of the array 900. When the floating gate driver transistors, 902-1, 902-2, . . . , 902-N are in an off state, an open is provided to the drain of the load device transistors 924. The VDD voltage level is applied to corresponding output lines 920 for second logic plane 922 when a load device transistor 924 is turned on by a clock signal received at the gate of the load device transistors 924 (Φ). In this manner a NOR-NOR electrically programmable logic array is most easily implemented utilizing the normal PLA array structure. Each of the floating gate driver transistors, 902-1, 902-2, . . . , 902-N described herein are formed according to the teachings of the present invention as described in detail in connection with FIGS. 2-7C.

[0134] Thus FIG. 9 shows the application of the novel, non-volatile floating gate transistors with low tunnel barrier intergate insulators in a logic array. If a floating gate driver transistors, 901-1, 901-2, . . . , 901-N, and 902-1, 902-2, . . . , 902-N, is programmed with a negative charge on the vertical floating gate it is effectively removed from the array. In this manner the array logic functions can be programmed even when the circuit is in the final circuit or in the field and being used in a system.

[0135] The absence or presence of stored charge on the floating gates is read by addressing the input lines 912 or control gate lines and y-column/sourcelines to form a coincidence in address at a particular floating gate. The control gate line would for instance be driven positive at some voltage of 1.0 Volts and the y-column/sourceline grounded, if the floating gate is not charged with electrons then the transistor would turn on tending to hold the interconnect line on that particular row down indicating the presence of a stored “one” in the cell. If this particular floating gate is charged with stored electrons, the transistor will not turn on and the presence of a stored “zero” indicated in the cell. In this manner, data stored on a particular floating gate can be read.

[0136] Programming can be achieved by hot electron injection. In this case, the interconnect lines, coupled to the second source/drain region for the non-volatile memory cells in the first logic plane, are driven with a higher drain voltage like 2 Volts for 0.1 micron technology and the control gate line is addressed by some nominal voltage in the range of twice this value. Electrons can also be transfered between the floating gate and the control gate through the low tunnel barrier intergate insulator to selectively program the non-volatile memory cells, according to the teachings of the present invention, by the address scheme as described above in connection with FIGS. 6A-6C. Erasure is accomplished by driving the control gate line with a large positive voltage and the sourceline and/or backgate or substrate/well address line of the transistor with a negative bias so the total voltage difference is in the order of 3 Volts causing electrons to tunnel off of the floating gates to the control gates. Writing can be performed, as also described above, by either normal channel hot electron injection, or according to the teachings of the present invention, by driving the control gate line with a large negative voltage and the the sourceline and/or backgate or substrate/well address line of the transistor with a positive bias so the total voltage difference is in the order of 3 Volts causing electrons to tunnel off of the control gates to the floating gates. According one embodiment of the present invention, data can be erased in “bit pairs” since both floating gates on each side of a control gate can be erased at the same time. This architecture is amenable to block address schemes where sections of the array are erased and reset at the same time.

[0137] One of ordinary skill in the art will appreciate upon reading this disclosure that a number of different configurations for the spatial relationship, or orientation of the input lines 912, interconnect lines 914, and output lines 920 are possible. That is, the spatial relationship, or orientation of the input lines 912, interconnect lines 914, and output lines 920 can parallel the spatial relationship, or orientation configurations detailed above for the floating gates and control gates as described in connection with FIGS. 5A-5E

[0138] FIG. 10 is a simplified block diagram of a high-level organization of an electronic system 1000 according to the teachings of the present invention. As shown in FIG. 10, the electronic system 1000 is a system whose functional elements consist of an arithmetic/logic unit (ALU), e.g. processor 1020, a control unit 1030, a memory unit 1040, or memory device 1040, and an input/output (I/O) device 1050. Generally such an electronic system 1000 will have a native set of instructions that specify operations to be performed on data by the ALU 1020 and other interactions between the ALU 1020, the memory device 1040 and the I/O devices 1050. The memory devices 1040 contain the data plus a stored list of instructions.

[0139] The control unit 1030 coordinates all operations of the ALU 1020, the memory device 1040 and the I/O devices 1050 by continuously cycling through a set of operations that cause instructions to be fetched from the memory device 1040 and executed. In service programmable logic arrays, according to the teachings of the present invention, can be implemented to perform many of the logic functions performed by these components. With respect to the ALU 1020, the control unit 1030 and the I/O devices 1050, arbitrary logic functions may be realized in the “sum-of-products” form that is well known to one skilled in the art. A logic function sum-of-products may be implemented using any of the equivalent two-level logic configurations: AND-OR, NAND-NAND, NOR-OR, OR-NOR, AND-NOR, NAND-AND or OR-AND, and using the novel non-volatile memory cells of the present invention.

Conclusion

[0140] The above structures and fabrication methods have been described, by way of example and not by way of limitation, with respect to in service programmable logic arrays using non-volatile memory cells with low tunnel barrier interpoly insulators.

[0141] It has been shown that the low tunnel barrier interpoly insulators of the present invention avoid the large barriers to electron tunneling or hot electron injection presented by the silicon oxide-silicon interface, 3.2 eV, which result in slow write and erase speeds even at very high electric fields. The present invention also avoids the combination of very high electric fields and damage by hot electron collisions in the which oxide result in a number of operational problems like soft erase error, reliability problems of premature oxide breakdown and a limited number of cycles of write and erase. Further, the low tunnel barrier interploy dielectric insulator erase approach, of the present invention remedies the above mentioned problems of having a rough top surface on the polysilicon floating gate which results in, poor quality interpoly oxides, sharp points, localized high electric fields, premature breakdown and reliability problems.

[0142] According to the teachings of the present invention, any arbitrary combinational logic function can be realized in the so-called sum-of-products form. A sum of products may be implemented by using a two level logic configuration such as the NOR-NOR arrays shown in FIG. 10, or by a combination of NOR gates and NAND gates. A NAND gate can be realized by a NOR gate with the inputs inverted. By programming the floating gates of the non-volatile memory cells in the array, these arrays can be field programmed or erased and reprogrammed to accomplish the required logic functions.

Claims

1. An in-service programmable logic array, comprising: a first logic plane that receives a number of input signals, the first logic plane having a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the in service programmable logic array implements a logical function; and wherein each of the logic cells includes a floating gate transistor, comprising: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator.

2. The in-service programmable logic array of claim 1, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al2O3).

3. The in-service programmable logic array of claim 1, wherein the low tunnel barrier intergate insulator includes a transition metal oxide.

4. The in-service programmable logic array of claim 3, wherein the transition metal oxide is selected from the group consisting of Ta2O5, TiO2, ZrO2, and Nb2O5.

5. The in-service programmable logic array of claim 1, whereing the low tunnel barrier intergate insulator includes a Perovskite oxide tunnel barrier.

6. The in-service programmable logic array of claim 1, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

7. The in-service programmable logic array of claim 6, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

8. The in service programmable logic array of claim 1, wherein the first logic plane and the second logic plane each comprise NOR planes.

9. A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a vertical non-volatile memory cell including: a first source/drain region formed on a substrate; a body region including a channel region formed on the first source/drain region; a second source/drain region formed on the body region; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator.

10. The programmable logic array of claim 9, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5.

11. The programmable logic array of claim 9, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

12. The programmable logic array of claim 11, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

13. The programmable logic array of claim 9, wherein the floating gate includes a vertical floating gate formed alongside of the body region.

14. The programmable logic array of claim 13, wherein the control gate includes a vertical control gate formed alongside of the vertical floating gate.

15. The programmable logic array of claim 9, wherein the floating gate includes a horizontally oriented floating gate formed alongside of the body region.

16. The programmable logic array of claim 15, wherein the control gate includes a horizontally oriented control gate formed above the horizontally oriented floating gate.

17. A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to a received input signal, wherein each logic cell includes a non-volatile memory cell including: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a polysilicon floating gate opposing the channel region and separated therefrom by a gate oxide; a first metal layer formed on the polysilicon floating gate; a metal oxide intergate insulator formed on the metal layer; a second metal layer formed on the metal oxide intergate insulator; and a polysilicon control gate formed on the second metal layer.

18. The programmable logic array of claim 17, wherein first and the second metal layers are lead and the metal oxide intergate insulator is lead oxide (PbO).

19. The programmable logic array of claim 17, wherein the first and second metal layer are aluminum and the metal oxide intergate insulator is aluminum oxide (Al2O3).

20. The programmable logic array of claim 17, wherein the first and the second metal layers include transition metal layers and the metal oxide intergate insulator includes a transition metal oxide intergate insulator.

21. The programmable logic array of claim 20, wherein the transition metal oxide is selected from the group consisting of Ta2O5, TiO2, ZrO2, and Nb2O5.

22. The programmable logic array of claim 17, wherein the metal oxide intergate insulator includes a Perovskite oxide intergate insulator.

23. The programmable logic array of claim 17, wherein the floating gate transistor includes a vertical floating gate transistor.

24. The programmable logic array of claim 17, wherein each input line is integrally formed with the polysilicon control gate for addressing the floating gate.

25. The programmable logic array of claim 17, wherein each input line is integrally formed with the polysilicon control gate in a trench opposing the floating gate.

26. The programmable logic array of claim 17, wherein the programmable logic array includes a number of buried source lines which are formed integrally with the first source/drain region and are separated from the semiconductor substrate by an oxide layer.

27. The programmable logic array of claim 17, wherein each input line includes a vertically oriented input line having a vertical length of less than 100 nanometers.

28. A programmable logic array, comprising: a plurality of input lines for receiving an input signal; a plurality of output lines; and one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein the first logic plane and the second logic plane comprise a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein each logic cell includes a vertical non-volatile memory cell including: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a plurality of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first source/drain region of pillars in the array; and wherein each of the number of input lines is disposed between rows of the pillars and integrally formed with the number of control gates and opposing the floating gates of the vertical non-volatile memory cells for serving as a control gate and are separated from the number of floating gates by a low tunnel barrier integrate insulator.

29. The programmable logic array of claim 28, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, A2O3, Ta2O5, TiO2, ZrO2, and Nb2O5.

30. The programmable logic array of claim 28, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

31. The programmable logic array of claim 28, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

32. The programmable logic array of claim 28, wherein the number of floating gates includes vertical floating gates formed alongside of the body region.

33. The programmable logic array of claim 32, wherein the number of control gates includes vertical control gates formed alongside of the vertical floating gates.

34. The programmable logic array of claim 28, wherein the number of floating gates includes horizontally oriented floating gates formed alongside of the body regions.

35. The programmable logic array of claim 28, wherein the number of buried source lines are formed integrally with the first source/drain regions and are separated from the substrate by an oxide layer.

36. A low voltage programmable logic array, comprising: a number of input lines for receiving an input signal; a number of output lines; and a first logic plane that receives a number of input signals on the number of input lines, the first logic plane having a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane coupled to the first logic plane by a number of interconnect lines, the second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function; wherein each logic cell includes a vertical non-volatile memory cell including: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates, wherein the number of control gates are separated from the number of floating gates by a low tunnel barrier integrate insulator; a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first source/drain regions of column adjacent pillars in the array.

37. The low voltage programmable logic array of claim 36, wherein the number of input lines are disposed in a trench between rows of the pillars in the first logic plane and oppose the floating gates of the vertical non-volatile memory cells for serving as control gates, and wherein the number of interconnect lines couple to the second source/drain region in columns of pillars for implementing a logic function in the first logic plane.

38. The low voltage programmable logic array of claim 36, wherein the number of interconnect lines are disposed in a trench between rows of the pillars in the second logic plane and oppose the floating gates of the vertical non-volatile memory cells for serving as control gates, and wherein the number of output lines couple to the second source/drain region in columns of pillars for implementing a logic function in the second logic plane.

39. The low voltage programmable logic array of claim 36, wherein column adjacent pillars are separated by a trench and each trench includes a pair of floating gates opposing the body regions on opposite sides of the trench.

40. The low voltage programmable logic array of claim 39, wherein each trench in the first logic plane includes a single vertically oriented input line formed between the pair of floating gates for serving as a shared control gate.

41. The low voltage programmable logic array of claim 39, wherein each trench in the second logic plane includes a single vertically oriented interconnect line formed between the pair of floating gates for serving as a shared control gate in the second logic plane.

42. The low voltage programmable logic array of claim 39, wherein each trench in the first logic plane includes a pair of vertically oriented input lines formed between the pair of floating gates, and wherein each one of the pair of vertically oriented input lines independently addresses the floating gates on opposing sides of the trench, and wherein the pair of vertically oriented input lines are separated by an insulator layer.

43. The low voltage programmable logic array of claim 39, wherein the number of input lines are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single input line in the first logic plane.

44. The low voltage programmable logic array of claim 39, wherein the number of input lines are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the number of input lines in the first logic plane.

45. The low voltage programmable logic array of claim 39, wherein a pair of input lines are formed above the pair of floating gates in each trench in the first logic plane for serving as control lines, and wherein the interconnect lines are coupled to the second source/drain regions in the first logic plane and are formed above the pair of floating gates in each trench in the second logic plane for serving as control lines.

46. The low voltage programmable logic array of claim 36, wherein column adjacent pillars are separated by a trench and each trench includes a horizontally oriented floating gate formed below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in column adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body regions of the pillars.

47. The low voltage programmable logic array of claim 46, wherein the number of input lines are disposed vertically above the floating gates in the first logic plane.

48. An electronic system, comprising: a memory; a processor coupled to the memory; and wherein the processor includes at least one in service programmable logic array including: a first logic plane that receives a number of input signals, the first logic plane having a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and wherein each of the logic cells includes a non-volatile memory cell including; a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator.

49. The electronic system of claim 48, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al2O3).

50. The electronic system of claim 48, wherein the low tunnel barrier intergate insulator includes a transition metal oxide.

51. The electronic system of claim 50, wherein the transition metal oxide is selected from the group consisting of Ta2O5, TiO2, ZrO2, and Nb2O5.

52. The electronic system of claim 48, wherein the floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

53. The electronic system of claim 52, wherein the control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

54. The electronic system of claim 48, wherein the first logic plane and the second logic plane each comprise NOR planes.

55. An electronic system, comprising: a memory; a processor coupled to the memory; and wherein at least one of the processor and memory include an in-service programmable logic array including: a number of input lines for receiving an input signal; a number of output lines; a first logic plane that receives a number of input signals on the number of input lines, the first logic plane having a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; a second logic plane coupled to the first logic plane by a number of interconnect lines, the second logic plane having a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane on the interconnect lines and that are interconnected to produce a number of logical outputs on the output lines such that the programmable logic array implements a logical function; wherein each logic cell includes a vertical non-volatile memory cell including: a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates, wherein the number of control gates are separated from the number of floating gates by a low tunnel barrier integrate insulator; a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first source/drain regions of column adjacent pillars in the array.

56. The electronic system of claim 55, wherein the low tunnel barrier intergate insulator includes a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5.

57. The electronic system of claim 55, wherein each floating gate includes a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

58. The electronic system of claim 57, wherein each control gate includes a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

59. The electronic system of claim 55, wherein each floating gate is a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

60. The electronic system of claim 59, wherein the number of control gates are formed in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

61. The electronic system of claim 59, wherein the number of control gates are formed in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gate lines each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gate lines are separated by an insulator layer.

62. The electronic system of claim 59, wherein the number of control gates are disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate.

63. The electronic system of claim 59, wherein the number of control gates are disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the number of control gates.

64. The electronic system of claim 55, wherein each floating gate is a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

65. The electronic system of claim 64, wherein the number of control gates are disposed vertically above the floating gates.

66. A method for forming a programmable logic array, comprising: forming a first logic plane that receives a number of input signals, wherein forming the first logic plane includes forming a number of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs; forming a second logic plane, wherein forming the second logic plane includes forming a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function; and wherein forming each of the logic cells includes; forming a first source/drain region and a second source/drain region separated by a channel region in a substrate; forming a floating gate opposing the channel region and separated therefrom by a gate oxide; forming a control gate opposing the floating gate; and forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate.

67. The method of claim 66, wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of lead oxide (PbO) and aluminum oxide (Al2O3).

68. The method of claim 66, wherein forming the low tunnel barrier intergate insulator includes forming a transition metal oxide insulator.

69. The method of claim 68, wherein forming the transition metal oxide insulator includes forming the transition metal oxide insulator selected from the group consisting of Ta2O5, TiO2, ZrO2, and Nb2O5.

70. The method of claim 66, wherein forming the floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

71. The method of claim 70, wherein forming the control gate includes a forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

72. The method of claim 66, wherein forming the first logic plane and the second logic plane each comprise forming NOR planes.

73. A method for forming an in service programmable logic array, comprising: forming a plurality of input lines for receiving an input signal; forming a plurality of output lines; and forming one or more arrays having a first logic plane and a second logic plane connected between the input lines and the output lines, wherein forming the first logic plane and the second logic plane forming a plurality of logic cells arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal, wherein forming each logic cell includes forming a vertical non-volatile memory cell including: forming a vertical pillar extending outwardly from a semiconductor substrate at intersections of the input lines and interconnect lines and at the intersections of the interconnect lines and the output lines, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; forming a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; forming a number of control gates opposing the floating gates; and forming a low tunnel barrier intergate insulator to separate the control gate from the floating gate forming a number of buried source lines formed of single crystalline semiconductor material and disposed below the pillars in the array for interconnecting with the first source/drain regions of column adjacent pillars in the array.

74. The electronic system of claim 73, wherein forming the low tunnel barrier intergate insulator includes forming a metal oxide insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5.

75. The electronic system of claim 73, wherein forming each floating gate includes forming a polysilicon floating gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

76. The electronic system of claim 73, wherein forming each control gate includes forming a polysilicon control gate having a metal layer formed thereon in contact with the low tunnel barrier intergate insulator.

77. The electronic system of claim 73, wherein forming each floating gate includes forming a vertical floating gate formed in a trench below a top surface of each pillar such that each trench houses a pair of floating gates opposing the body regions in adjacent pillars on opposing sides of the trench.

78. The electronic system of claim 77, wherein forming the number of control gates includes forming the control gates in the trench below the top surface of the pillar and between the pair of floating gates, wherein each pair of floating gates shares a single control gate line, and wherein each floating gate includes a vertically oriented floating gate having a vertical length of less than 100 nanometers.

79. The electronic system of claim 77, wherein forming the number of control gates includes forming the control gates in the trench below the top surface of the pillar and between the pair of floating gates such that each trench houses a pair of control gates each addressing the floating gates one on opposing sides of the trench respectively, and wherein the pair of control gates are separated by an insulator layer.

80. The electronic system of claim 77, wherein forming the number of control gates includes forming the control gates disposed vertically above the floating gates, and wherein each pair of floating gates shares a single control gate.

81. The electronic system of claim 77, wherein forming the number of control gates includes forming the control gates disposed vertically above the floating gates, and wherein each one of the pair of floating gates is addressed by an independent one of the number of control gates.

82. The electronic system of claim 73, wherein forming each floating gate includes forming a horizontally oriented floating gate formed in a trench below a top surface of each pillar such that each trench houses a floating gate opposing the body regions in adjacent pillars on opposing sides of the trench, and wherein each horizontally oriented floating gate has a vertical length of less than 100 nanometers opposing the body region of the pillars.

83. The electronic system of claim 82, wherein forming the number of control gates includes forming the control gates disposed vertically above the floating gates.

84. A method for operating an in-server programmable logic array, comprising: writing to one or more floating gates of a number of non-volatile memory cells in one or more arrays using channel hot electron injection, the one or more arrays having a first logic plane and a second logic plane connected between a number of input lines and a number of output lines, wherein number of non-volatile memory cells in the first logic plane and the second logic plane are arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal on the input lines, wherein each non-volatile memory cell includes: a first source/drain region and a second source/drain region separated by a channel region in a substrate; a floating gate opposing the channel region and separated therefrom by a gate oxide; a control gate opposing the floating gate; and wherein the control gate is separated from the floating gate by a low tunnel barrier intergate insulator; erasing charge from one or more floating gates by tunneling electrons off of the floating gate and onto the control gate.

85. The method of claim 84, wherein erasing charge from one or more floating gates by tunneling electrons off of the floating gates and onto the control gates further includes: providing a negative voltage to the substrate of an addressed cell; and providing a large positive voltage to the control gate of the addressed cell.

86. The method of claim 84, wherein the method further includes writing to one or more floating gates by tunneling electrons from the control gate to the floating gate in one or more addressed cells.

87. The method of claim 86, wherein writing to one or more floating gates by tunneling electrons from the control gate to the floating gate in one or more addressed cells further includes: applying a positive voltage to the substrate of an addressed cell; and applying a large negative voltage to the control gate of the addressed cell.

88. The method of claim 84, wherein erasing charge from the floating gate by tunneling electrons off of the floating gate and onto the control gate includes tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator.

89. The method of claim 88, wherein tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator includes tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator selected from the group consisting of PbO, Al2O3, Ta2O5, TiO2, ZrO2, and Nb2O5.

90. The method of claim 88, wherein tunneling electrons from the floating gate to the control gate through a low tunnel barrier intergate insulator includes tunneling electrons from a metal layer formed on the floating gate in contact with the low tunnel barrier intergate insulator to a metal layer formed on the control gate and also in contact with the low tunnel barrier intergate insulator.

91. A method for operating an in-server programmable logic array, comprising: writing to one or more floating gates of a number of non-volatile memory cells in one or more arrays using channel hot electron injection, the one or more arrays having a first logic plane and a second logic plane connected between a number of input lines and a number of output lines, wherein number of non-volatile memory cells in the first logic plane and the second logic plane are arranged in rows and columns for providing a sum-of-products term on the output lines responsive to the received input signal on the input lines, wherein each non-volatile memory cell includes: a number of pillars extending outwardly from a substrate, wherein each pillar includes a first source/drain region, a body region, and a second source/drain region; a number of floating gates opposing the body regions in the number of pillars and separated therefrom by a gate oxide; a number of control gates opposing the floating gates; a number of buried sourcelines disposed below the number of pillars and coupled to the first source/drain regions along a first selected direction in the array of non-volatile memory cells; a number of control gate lines formed integrally with the number of control gates along a second selected direction in the array of non-volatile memory cells, wherein the number of control gates lines are separated from the floating gates by a low tunnel barrier intergate insulator; and a number of bitlines coupled to the second source/drain regions along a third selected direction in the array of non-volatile memory cells; and erasing charge from the one or more floating gates by tunneling electrons off of the one or more floating gates and onto the number of control gates.

92. The method of claim 91, wherein erasing charge from the one or more floating gates by tunneling electrons off of the floating gate and onto the number of control gate further includes: providing a negative voltage to a substrate of one or more non-volatile memory cells; and providing a large positive voltage to the control gate for the one or more non-volatile memory cells.

93. The method of claim 92, wherein the method further includes erasing an entire row of non-volatile memory cells by providing a negative voltage to all of the substrates along an entire row of non-volatile memory cells and providing a large positive voltage to all of the control gates along the entire row of non-volatile memory cells.

94. The method of claim 92, wherein the method further includes erasing an entire block of non-volatile memory cells by providing a negative voltage to all of the substrates along multiple rows of non-volatile memory cells and providing a large positive voltage to all of the control gates along the multiple rows of nonvolatile memory cells.