Orthogonal spin transfer magnetic random access devices (OST-MRAM™) incorporate a polarizer. The devices and layer stacks are discussed in U.S. Pat. No. 6,980,469, the entirety of which is incorporated by reference. Roughness within and near the magnetic tunnel junction of a layer stack impacts performance of the OST™ device. Increased roughness can negatively impact the breakdown of the magnetic tunnel junction. An OST™ layer stack with the polarizer on the top of the stack can reduce the roughness of the magnetic tunnel junction, increase the device magnetoresistance, and improve the performance of OST™ memory devices.
In general, one aspect of the subject matter described in this specification is embodied in a magnetic device that includes a pinned magnetic layer that has a first fixed magnetization vector with a first fixed magnetization direction. The magnetic device also includes a free magnetic layer including a first body-centered cubic material and having a variable magnetization vector having at least a first stable state and a second stable state. The magnetic device also includes a first non-magnetic layer and a reference layer. The first non-magnetic layer spatially separates the pinned magnetic layer and the free magnetic layer and includes a second body-centered cubic material that interfaces with the first body-centered cubic material. The reference magnetic layer has a second fixed magnetization vector with a second fixed magnetization direction. The magnetic device also includes a second non-magnetic layer spatially separating the free magnetic layer and the reference magnetic layer. A magnetic tunnel junction is formed by the free magnetic layer, the second non-magnetic layer, and the reference magnetic layer. Application of a current pulse, having either positive or negative polarity and a selected amplitude and duration, through the magnetic device switches the variable magnetization vector. The magnetic tunnel junction is spatially located below the pinned magnetic layer. Other implementations of memory devices and memory systems are described in greater detail below.
The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, implementations, and features described above, further aspects, implementations, and features will become apparent by reference to the following drawings and the detailed description.
The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. Understanding that these drawings depict only several implementations in accordance with the disclosure and are, therefore, not to be considered limiting of its scope, the disclosure will be described with additional specificity and detail through use of the accompanying drawings.
All numerical thicknesses illustrated in the figures are nanometers (nm). Reference is made to the accompanying drawings throughout the following detailed description. In the drawings, similar symbols typically identify similar components, unless context dictates otherwise. The illustrative implementations described in the detailed description, drawings, and claims are not meant to be limiting. Other implementations may be utilized, and other changes may be made, without departing from the spirit or scope of the subject matter presented here. It will be readily understood that the aspects of the present disclosure, as generally described herein, and illustrated in the figures, can be arranged, substituted, combined, and designed in a wide variety of different configurations, all of which are explicitly contemplated and made part of this disclosure.
Structure of a Basic Magnetic Device
The pinned magnetic layer FM1 and the free magnetic layer FM2 are separated by a first non-magnetic layer N1 that spatially separates the two layers FM1 and FM2. N1 may be a non-magnetic metal (Cu, CuN, Cr, Ag, Au, Al, Ru, Ta, TaN, etc.) or a thin non-magnetic insulator such as Al2O3 or MgO. When N1 is a non-magnetic metal its thickness must be less or approximately equal to the spin-diffusion length in the material at the temperature of the device. This allows the electron spin-polarization to be substantially maintained as electrons traverse N1. In one implementation where Cu is used, the thickness of the layer be less than or approximately equal to 0.5 to 50 nm for a device operating at or near room temperature. When N1 is an insulating layer, its thickness must be such that electrons can traverse this layer by quantum mechanical tunneling and mainly preserve their direction of spin-polarization in this process. In an implementation where N1 is MgO or Al2O3, the layer should be approximately equal to 0.3 to 4 nm in thickness. The thickness of the non-magnetic layer N1 should be such there is an absence of scattering of the electron spin-direction on a short length scale, which is less than about the layer thickness. The pillar-shaped magnetic device is typically sized in nanometers, e.g., it may be less than approximately 200 nm laterally.
The free magnetic layer FM2 is essentially a magnetic thin film element imbedded in a pillar-shaped magnetic device with two additional layers—the pinned magnetic layer FM1 and the non-magnetic layer N1. The layer thicknesses are typically approximately 0.7 nm to 10 nm.
These pillar-shaped magnetic devices can be fabricated in a stacked sequence of layers by many different means, including physical vapor deposition (sputtering), thermal and electron-beam evaporation through a sub-micron stencil mask. These magnetic devices can also be fabricated in a stack sequence using sputtering, thermal and electron-beam evaporation to form a multilayered film followed by a subtractive nanofabrication process that removes materials to leave the pillar-shaped magnetic device on a substrate surface, such as that of a silicon of other semiconducting or insulating wafer. The semiconducting wafer may already include portions of the CMOS circuitry for reading and writing the magnetic device. Annealing may be used when the layer stack incorporates a magnetic tunnel junction. Annealing can crystallize an MgO insulating barrier and enhance the junction magnetoresistance. In various implementations, a single annealing process is used. In one implementation, the stacks are annealed at a temperature of 300 C to 450 C to thermally crystallize the MgO layer. The duration of the annealing is minutes (a rapid thermal anneal) to several hours, with higher annealing temperatures requiring shorter annealing times. The annealing is often done in a magnetic field of 1 Tesla or greater to set the magnetic state of the reference layer (FM3). The annealing provides a preferred direction of magnetic anisotropy and an enhanced uniaxial magnetic anisotropy of the free layer (FM2).
Materials for the ferromagnetic layers include (but are not limited to) Fe, Co, Ni; alloys of these elements, such as Ni1-xFex, and CoFe; alloys of these ferromagnetic metals with non-magnetic metals, such as B, Cu, V, Pd, and Pt at compositions in which the materials are ferromagnetically ordered at room temperature; conducting materials; conducting magnetic oxides such as CrO2 and Fe3O4; and fully spin-polarized materials such as the Heusler alloy NiMnSb. For the nonmagnetic layers, materials include (but are not limited to) Cu, CuN, Cr, Ag, Au, Al, Ru, Ta, and TaN.
An electric current source is connected to the pinned magnetic layer FM1 and the free magnetic layer FM2 so that an electric current, I, can traverse the pillar device. In another implementation, an electrical contact is made to the top and bottom of a pillar that incorporates the layer stack.
Other inverted stacks can be produced with additional layers.
The synthetic antiferromagnet polarizer 404 reduces the magnetic interactions between the perpendicular polarizer and the free magnetic layer FM2 in the inverted layer stack 400. The reduced magnetic interactions improves device performance, such as, but not limited to, more uniform rotation of the magnetization of the free layer during switching (e.g., writing data); reduction of the likelihood of undesired thermally induced switching events (e.g., fluctuations that erase or corrupt stored data).
In addition to inverting the perpendicular polarizer, changing the materials within the N1 layer can impact the properties of an inverted layer stack.
While not limited to the following reason, Copper can induce its face-centered cubic (fcc) crystalline structure into the CoFeB layer with which it shares an interface. For an optimal TMR, a (body-centered cubic) bcc texture of the CoFeB is favorable. The Copper layer can magnetically decouple the polarizer and the magnetic tunnel junction. In these implementations, the Cu/CoFeB interfaces between the Copper interlayer and the CoFeB free layer is the reason for the reduced electric performance, e.g., smaller TMR. Using a bcc texture rather than an fcc structure such as Copper, can increase the TMR of the stack. In addition, using a material that crystallizes at a higher temperature than the CoFeB favors the formation of bcc textured CoFeB and can increase the TMR.
In one implementation, the Copper layer is replaced by a bcc non-magnetic layer.
In another implementation, the non-magnetic layer N1 can be composed of both fcc and bcc materials.
While this specification contains many specific implementation details, these should not be construed as limitations on the scope of any inventions or of what may be claimed, but rather as descriptions of features specific to particular implementations of particular inventions. Certain features described in this specification in the context of separate implementations can also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated in a single software product or packaged into multiple software products.
Thus, particular implementations of the invention have been described. Other implementations are within the scope of the following claims. In some cases as one of skill in the art would understand after reading this disclosure, the actions recited in the claims can be performed in a different order and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing may be advantageous.
This application claims the benefit of U.S. Provisional Patent Application No. 61/715,073, filed on Oct. 17, 2012, which is incorporated by reference herein in its entirety.
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| Number | Date | Country | |
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| Number | Date | Country | |
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| 61715073 | Oct 2012 | US |