The present disclosure, according to one embodiment, relates to semiconductor devices, more specifically to N-channel Electrically Erasable Programmable Read Only Memory (EEPROM) (hereinafter memory) devices that may have segmented independently programmable memory sub-arrays.
A common practice in fabricating Electrically Erasable Programmable Read Only Memory (EEPROM) was to produce N-channel cells over a P-well substrate because of a simpler manufacturing process and lower programming voltages. The approach used by Caywood; as disclosed in U.S. Pat. No. 5,986,931, entitled “Low Voltage Single Supply CMOS Electrically Erasable Read-Only Memory” which is a continuation-in-part of U.S. Pat. No. 5,790,455, and U.S. Pat. No. 5,986,931 (Caywood 2) and U.S. Pat. No. 5,790,455 (Caywood 1), incorporated by reference herein for all purposes; produces precisely the opposite configuration, i.e., P-channel devices over an N-well, which itself resides in a P-type substrate. The novelty of the Caywood approach is the reduction in magnitude of the applied voltage required for erasing and writing to the device while maintaining a similar writing speed as found in the related technology prior to Caywood as well as the elimination of certain components functionally necessary in the related technology.
Referring to
Referring to
Alternatively stated, as disclosed by Caywood, the cell rows are not segmented such that some memory cells in the cell row may be selected for writing while other memory cells in the row are not. Thus, in order to program the contents of a single memory cell, the entire cell row must then be programmed in order to change the data in one memory cell.
In many applications it is desired to change the data in the memory array, one byte at a time. In the N-channel device prior art, this feature was accomplished by the inclusion of a byte select transistor (BYTE) for each eight memory transistors as shown in
Moreover, the capability of changing one byte at a time would give an endurance advantage over row select memory arrays because only one byte of cells would need to undergo the electrical stress of the programming cycle as opposed to the entire row. It is well known to those skilled in the art of semiconductor memory fabrication that one cause of EEPROM failure is attributable to excessive erase/write operations.
Advantages of N-channel/P-well EEPROM technology are maximized by providing independently programmable memory segments within the EEPROM array other than with byte select transistors. This may be accomplished by providing an N-channel/P-well electrically erasable programmable read only memory array that is divided into independently programmable memory segments within a memory array by fabricating a plurality of P-wells within a deep N-well of the array or by segmenting the P-well of the array into sub-P-wells in the deep N-well. The independently programmable memory segments are achieved without the necessity for byte select transistors. Creating a plurality of P-wells within a deep N-well may be done with p-n junction isolation. Segmenting a P-well of the memory array may done by dielectric isolation.
According to a specific example embodiment of the present disclosure, a memory array comprises a plurality of P-wells within a deep N-well that is in a P-type substrate and each of the plurality of P-wells comprises a plurality of independently programmable memory segments. Each independently programmable memory segment is comprised of M memory cell columns and N memory cell rows. Each independently programmable memory segment resides within a unique and separate P-well. Thus, each P-well contains an independently programmable memory segment.
According to another specific example embodiment of the present disclosure, a memory array comprises a P-well within a deep N-well that is within a P-type substrate wherein the P-well is segmented into a plurality of electrically isolated sub P-wells, M memory transistor columns within each of the plurality of electrically isolated sub P-wells and N memory transistor rows within each of the plurality of electrically isolated sub P-wells.
Commonly owned U.S. Pat. Nos. 6,222,761 B1; 6,236,595 B1; 6,300,183 B1; and 6,504,191 B2; all by Gerber et al., disclose PMOS EEPROM having independently programmable memory segments, all of which are incorporated by reference herein for all purposes.
A more complete understanding of the present disclosure thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings wherein:
While the present disclosure is susceptible to various modifications and alternative forms, specific example embodiments thereof have been shown in the drawings and are herein described in detail. It should be understood, however, that the description herein of specific example embodiments is not intended to limit the disclosure to the particular forms disclosed herein, but on the contrary, this disclosure is to cover all modifications and equivalents as defined by the appended claims.
Referring now to the drawings, the details of example embodiments are schematically illustrated. Like elements in the drawings will be represented by like numbers, and similar elements will be represented by like numbers with a different lower case letter suffix.
Referring to
In the specific example embodiment of the present disclosure, there are eight memory transistor columns within each P-well segment, thereby comprising byte (8 bit) segments. There are a common number of cell rows 100 within each P-well and the total number of rows 100 is determined by the desired size of the memory array 10. In
In the embodiment of
Furthermore, each of the independently programmable memory segments which may be comprised of M cell columns, where M is either smaller or larger than a byte. The number M of cell columns 200, alternative to the byte format, include, but are not limited to: 2, 4, 16, 32, 64, etc., cell columns 200 for each independently programmable memory segment. These various memory array 10 geometries are easily implemented according to the specific example embodiments of this disclosure.
Each independently programmable memory segment may be comprised of a plurality of independently programmable memory units. An independently programmable memory unit is defined as those cell columns 200 which are common to a given cell row 100 and within a single independently programmable memory segment. The intersection of a cell column 200 and a cell row 100 defines a memory cell which may be a single memory transistor. Thus, for the specific example embodiment geometry illustrated in
The functional relevance of the independently programmable memory unit may be as follows. A single independently programmable memory unit defines the smallest or most narrow portion of the memory array 10 that may be addressed by the write and erase memory operations described below. Additionally, all independently programmable memory units within a common cell row 100 may be simultaneously addressed by the read, write and erase memory operations.
Referring to
Referring to
Referring to
Two separate P-wells with accompanying independently programmable memory segments are shown in dashed lines drawn around a group of cells. Contained within P-well 301 are 8 memory transistor columns (only three are shown for clarity) and N memory transistor rows. P-well 302 is identical to P-well 301, however, P-well 302 is electrically isolated from P-well 301. Note that each independently programmable memory segment corresponds to a P-well and thus, the quantity of P-wells is equal to the quantity of independently programmable memory segments. The upper left independently programmable memory unit in P-well 301 is enclosed in a solid line box 702 to indicate that this is the target independently programmable memory unit (e.g., target byte) for the write, erase, and read operations described herein below.
The control electrodes of the N-channel memory transistors 401-1 to 416-n for each row are connected to common word lines WL1 to WLn, respectively. The drain electrodes of the memory transistors of any particular column are connected to a common bit lines BL1-BL16, respectively. The source electrodes of each memory transistor in a particular column are commonly connected to a respective one of the source select transistors 501-516. The source select transistors 501-516 are controlled by two control lines, SSG and SSD, connected to the gates and drains, respectively, of the source select transistors 501-516. Voltage potentials at P-well 301 and P-well 302 may also be independently controlled, as represented by node 704 and 706, respectively.
In this disclosure the IEEE standard 1005 will be followed for consistent nomenclature. Writing or programming a memory cell bit is defined as placing electrons, e.g., a charge, onto the floating gate of the memory transistor. Erasing is defined as removing electrons from the floating gate of the memory transistor. The various writing, erasing and reading operations are performed by applying different combinations of voltages onto the word lines WLx, bit lines BLx, source select transistor gates SSG, source select transistor drains SSD, and P-wells, as described herein more fully below.
Referring to
Conversely, using WL2 as an example, the P-well 301 and the control electrodes of memory transistors 401-2 to 408-2 are biased to Vpp. Under these conditions, no tunneling occurs because of an absence of an electric field between these memory transistors 401-2 to 408-2 and the P-well 301. Thus, memory transistors 401-2 to 408-2 are not erased.
With respect to memory transistors 409-2 to 416-2, the P-well 302 is at substantially ground or zero volts and the control electrodes at Vpp potential results in a N-type inversion layer under the poly 2 layer of each of the memory cells 409-2 to 416-2. With BL9-16 at Vpp and the drain electrodes of memory transistors 409-2 to 416-2 tied to the inversion layer, there is no voltage potential between the control electrode and the inversion layer at the surface of the P-well 302. Thus, even with the P-well 302 biased to substantially ground or zero volts, no tunneling occurs thereby precluding an erase operation for memory transistors 409-2 to 416-2.
For the erase operation, the bit line to each of the columns BL1:8 and BL9:16 are set to Vpp, SSG is set to substantially ground or zero volts, SSD is set to Vpp, and the P-well 301 is biased to Vpp. This permits a sufficient voltage potential between the floating gate of the memory transistors 401-1 to 408-1, controlled by WL1 and the P-well 301. Electrons tunnel from the floating gate across the dielectric layer to the P-well 301, thus positively charging the floating gate. Conversely, P-well 302 is biased to substantially ground or zero volts, thereby failing to create the sufficient voltage potential between the control electrodes of the memory transistors 409-1 to 416-1 that are within P-well 302 and the P-well 302. Without a sufficient voltage differential, tunneling cannot occur and the erase cycle is not accomplished. Thus, by providing for separate and isolated P-wells, the N-channel memory transistors in any row may be organized in byte selectable segments where byte selection is effected, at least in part, by the application of, or biasing at, different voltage potentials, the plurality of the P-wells themselves.
Referring to
Conversely, with WL1, BL1, and BL3:16 set to Vpp, the inversion layer for memory transistors 401-1 and 403-1 to 416-1 is biased at Vpp, which results in substantially no electron tunneling. Thus, the write operation is not accomplished for memory transistors 401-1 and 403-1 to 416-1. In the target independently programmable memory unit (e.g., target byte 702) of
Referring to
While embodiments of this disclosure have been depicted, described, and are defined by reference to example embodiments of the disclosure, such references do not imply a limitation on the disclosure, and no such limitation is to be inferred. The subject matter disclosed is capable of considerable modification, alteration, and equivalents in form and finction, as will occur to those ordinarily skilled in the pertinent art and having the benefit of this disclosure. The depicted and described embodiments of this disclosure are examples only, and are not exhaustive of the scope of the disclosure.