Patent Application
20120054421
The present application claims priority from Japanese patent application JP 2010-188174 filed on Aug. 25, 2010, the content of which is hereby incorporated by reference into this application.
The present invention relates to an information device with cache memories, an apparatus using it, and a program, and more specifically, to an information device that uses nonvolatile memory as cache memories and an apparatus using it.
In the related art, volatile memory has been used for cache memories. However, the volatile memory cache had a problem of consuming a lot of electric power in order to retain data. Moreover, there was a problem that data was lost by power supply cutoff etc. Therefore, the cache memories need to have contrivances of carrying a battery in order to supply electric power for a fixed period after power supply cutoff, not allowing data to stay in the cache for a long time, and the like.
Since the use of nonvolatile memory as the cache enables attainment of promotion of power saving and reduction in risk of data loss caused by power supply cutoff and the like, application of the nonvolatile memory for the cache is beginning to be considered.
Among nonvolatile memories that are currently on the market, one that has the largest size in the market is NAND flash memory. In recent years, its bit cost falls below that of Dynamic Random Access Memory (DRAM). Since write endurance of the NAND flash memory is as low as 103-106 (in the DRAM, it is 1016), it is used mainly in storage devices, such as a solid state drive.
Although read and write speeds of the NAND flash memory is fast as compared with the HDD, it is slow as compared with that of the DRAM by 1/103-4 (while the random read and write speed of the DRAM is 6 to 40 ns, in the case of the NAND flash memory, the speed of the random write is 105 ns and the speed of random read is 104 ns). Moreover, power consumption of the NAND flash memory at the time of write is comparable to that of the DRAM (the power consumption of the NAND flash and the DRAM at the time of write per bit is 65 pJ).
In recent years, developments of next-generation memories, such as Phase Change Random Access Memory (PRAM) Magnetic Random Access Memory (MRAM), and Ferroelectric Random Access Memory (FeRAM) are being progressed. These nonvolatile memories have a feature of having high write endurance as compared with the flash memory. However, although when comparing them with the DRAM, the write endurance of the MRAM is comparable to that of the DRAM, the write endurance of the PRAM and the FeRAM is 1012 and is inferior as compared with that of the DRAM. The PRAM and the FeRAM have random read and write performance comparable to that of the DRAM. Moreover, the read and write performance of the MARM is higher than the random read and write performance of the DRAM.
The power consumption of the PRAM and the MRAM at the time of write is comparable to that of the DRAM. Regarding the FeRAM, it has a feature that it is less than the power consumption of the DRAM at the time of write (while a writing power consumption of the DRAM per bit is 65 pJ, that of the FeRAM is 2 pJ).
Since the nonvolatile memory has various features as mentioned above, it is necessary to contrive how to use the nonvolatile memory when using it as a cache.
US 2007/0162693A1 describes an example of a magnetic disk drive equipped with nonvolatile memory as a cache. In this example, by storing a startup program of a computer (host), such as an operating system, and a frequently-used application program in nonvolatile memory, a data transfer rate to the host is improved, so that shortening of its startup time is achieved. Moreover, the disks are made to spin down when there is no access to the disks and write request data are written in the nonvolatile memory or read request data are transferred from the nonvolatile memory during a spin-down state, so that power saving is achieved.
Since nonvolatile memory has the above features, it is necessary to devise how to use the nonvolatile memory when using it as a cache. For example, in the magnetic disk drive described in US 2007/0162693A1, if nonvolatile memory whose write endurance is low, such as the flash memory, is used for the cache, with increasing number of times of use (since the number of times of writing data in the cache reaches a predetermined number of times), the cache will be unusable, and a data transfer rate and a power saving effect of the magnetic disk drive will decrease rapidly.
Moreover, in the magnetic disk drive as mentioned above, if nonvolatile memory, such as flash memory, that has slow read and write speeds is used for the cache, for an access to a continuous area, a difference between the speeds of the nonvolatile memory and read and write speeds for the disks becomes small, and therefore a speed improvement effect by the cache is low. Moreover, in the magnetic disk drive as mentioned above, in the case of using the nonvolatile memory whose power consumption at the time of write is large, such as the flash memory, as a cache, as the writing quantity of the write data in the flash memory is increased, the power saving effect decreases.
One of the problems that the present invention intends to address is that when the nonvolatile memory is used as a cache, persistence of the effect of the cache is short because its write endurance is low. Another problem that the present invention intends to address is that when the nonvolatile memory is used as a cache, the speed improvement effect is low because its speed is slow. Further another problem that the present invention intends to address is that when the nonvolatile memory is used as a cache, the power saving effect lowers because its power consumption at the time of writing data is large.
It's an object of the present invention to provide an information device that resolves various problems, such as the write endurance, the read/write speeds or the power consumption in an information device placed on a data transfer path between multiple devices being different in data processing speed, and an apparatus that uses it.
One of typical examples according to the present invention is shown as follows. The information device of the present invention is an information device equipped with cache memory for read and cache memory for write on the data transfer paths among multiple devices that are different in data processing speed, and the cache memory for write consists of first nonvolatile memory and the cache memory for read consists of second nonvolatile memory whose characteristic is different from that of the first nonvolatile memory.
According to the aspect of the present invention, by forming read and write caches with a combination of two kinds of nonvolatile memories whose characteristics are different, it is possible to much enhance the effect by the cache and to provide the information device that meets various requirements and the apparatus using it.
According to an exemplary embodiment of the present invention, the cache is formed with two kinds of nonvolatile memories that are different in write endurance: nonvolatile memory whose write endurance is high is adopted for the write cache and nonvolatile memory whose write endurance is low is adopted for a read cache, and management tables of data in those caches are stored in nonvolatile memory whose write endurance is high. Moreover, data in an area whose read-access frequency is high is extracted and written in the nonvolatile memory read cache whose write endurance is low. Thereby, persistence of an effect by the cache can be enhanced while suppressing increases in cost, power consumption, etc.
Moreover, according to another exemplary embodiment, the cache is configured with two kinds of nonvolatile memories that are different in read and write speeds: nonvolatile memory whose write speed is fast and whose read speed is slow is adapted for the write cache and nonvolatile memory whose write read speed is fast and whose write speed is slow is adapted for the read cache, respectively. Thereby, the improvement effect of the read and write speeds by the cache can be enhanced while suppressing increases in cost, power consumption, etc.
Moreover, according to another exemplary embodiment, the cache is configured with two kinds of nonvolatile memories that are different in power consumption: nonvolatile memory whose power consumption at the time of write is small is adopted for the write cache. Thereby, a power saving effect by a cache can be enhanced, while suppressing an increase in cost, a fall of read/write speeds, etc. Note that, in this application specification, the “information device” means one that is placed in a data transfer path between a pair of devices whose processing speeds are different and is equipped with “a cache memory device”. More specifically, one of the pair of devices is a computer, and the other thereof is a storage device or storage medium. The “storage device” includes a magnetic system storage device, an optical system storage device, and further a drive unit that uses flash memory for a storage medium (SSD: Solid State Drive). The “storage medium” includes a magnetic disk, an optical disk, semiconductor memory, etc. The “cache memory device” is a device that incorporates a controller, the nonvolatile memory read cache, and a nonvolatile memory write cache as a set. The “cache memory device” is appended a “volatile memory read cache” if needed. Incidentally, the controller in the cache memory device is expressed as a hard disk controller (an HDC) in the magnetic disk drive, and as a controller in other information device and apparatus.
The “nonvolatile memory” used in the present invention is memory that can be read and written, which includes, for example, ReRAM, STT-RAM, etc. in addition to previously enumerated PRAM (or PCM), MRAM, and FeRAM.
Moreover, in the present invention, the “memory that is different in characteristic” means discrete memory that adopts a memory technology different in physical principal. These “memories of different characteristics” make a difference mutually in any characteristic of “write endurance,” “read/write performance”, and “power consumption.” Moreover, as a result, these “memories of different characteristics” make a difference in terms of cost. Naturally, memory that is different from the others in terms of cost as a result of adopting a memory technology different in physical principle is one of the “memories whose characteristics are different” in the present invention. On the other hand, even if the memory that adopts the same physical principle as that of the other memory is different from the other in specification, performance, cost, or the like, they do not come under the “memory whose characteristics are different” of the present invention.
Hereinafter, embodiments of the information device equipped with the cache memory device of nonvolatile memory of the present invention will be described in detail by using drawings.
A first embodiment is configured as the apparatus by integrating an information device of the present invention into a magnetic disk drive and will be described referring to
Furthermore, the magnetic disk drive is equipped with a servo control unit 121 for performing a control for moving a head to a position specified when reading and writing data, a voice coil motor (VCM) 125 for moving the head (illustration is omitted) following an instruction of this servo control unit, a motor driver 122 for controlling rotation of the disks 102, a spindle motor for disk rotation (illustration is omitted), and a selector 126 for selecting only a signal of the head specified from magnetic signals read from the heads. Furthermore, it is equipped with a signal processing unit 124 for converting analog data sent from the selector 126 into digital data or converting digital data sent from the HDC 105 into analog data and a disk formatter 123. The disk formatter 123 transfers read data sent from the signal processing unit 124 to the volatile memory read cache 109 by opening and closing a gate for read, and transfers write data transferred from the nonvolatile memory write cache 104 to the signal processing unit 124 by opening and closing a gate for write.
The HDC 105 in the above-mentioned cache memory device writes the write data received from the host 100 in the nonvolatile memory write cache, and reads data of addresses read-requested by the host 100 from the nonvolatile memory read cache 103 or the volatile memory read cache 109.
The nonvolatile memory for write and the nonvolatile memory for read are different in characteristic. That is, the nonvolatile memory 104 for write consists of nonvolatile memory whose write endurance is high, and the nonvolatile memory for read consists of the nonvolatile memory 103 whose write endurance is lower than that of the nonvolatile memory 104 for write. A reason that nonvolatile memories that are different in write endurance are used for the read cache and the write cache is, for example, that the nonvolatile memory whose write endurance is low is superior to the nonvolatile memory whose write endurance is high in respects of cost etc. What is necessary in using nonvolatile memories is just to assign two kinds of nonvolatile memories that are different in property to the read cache and the write cache, respectively, according to specifications required for the information device, such as cost and performance.
The nonvolatile memory write cache 104 is equipped with a nonvolatile memory write-data management table 107 and a nonvolatile memory read-data management table 106 for managing the write data in the nonvolatile memory and the read data in the nonvolatile memory, respectively. By placing the management tables of the write data of nonvolatile memory and of the read data of nonvolatile memory in the nonvolatile memory, loss of data in the cache caused by power supply cutoff etc. can be prevented. Moreover, by placing the nonvolatile memory write-data management table 107 and the nonvolatile memory read-data management table 106 on the write cache whose write endurance is high, depletion of the nonvolatile memory read cache whose write endurance is low can be mitigated.
Moreover, the volatile memory read cache 109 in the HDC 105 is equipped with a volatile memory read-data management table 110 for managing the read data in the volatile memory. Since by the HDC 105 being equipped with the volatile memory therein, it is possible for the nonvolatile memory read cache 103 whose write endurance is low to extract and store data whose read request frequency is high, the depletion of the nonvolatile memory read cache can be mitigated.
For example, the NAND flash memory and the PRAM are assigned to the nonvolatile memory read cache 103, and the MRAM is assigned to the nonvolatile memory write cache 104. Moreover, the DRAM is used for the volatile memory 1309. The above-mentioned memory combination is one example, and naturally other combination may be selected according to the characteristics of nonvolatile memories.
Moreover, an access frequency management table 111 (see
The CPU 120 reads the data from the disks and writes the data on the disks, writes the data in the cache, and reads the data from the cache by executing various computer programs stored in the local memory (ROM) 118 and controlling the disk drive means and the HDC 105; therefore, it realizes reading of the data from the magnetic disk drive and writing of the data to the magnetic disk drive. That is, in a read processing, it reads the read requested data from the disks by controlling the disk drive means in response to the read request from the host, and at the same time controls the HDC 105 to write the read requested data being read to the volatile memory read cache 109 and transfer it to the host 100, while in a write processing, it controls the HDC 105 to write the write request data transferred from the host 100 to the nonvolatile memory write cache 104, and read the write data being written from the write cache and controls the disk drive means to write the write data on the disks 102.
Next,
An address of the table entry on the memory can be shown by adding the offset address of the entry to a base address indicating a start address of the data. The base address shall be recorded in the nonvolatile register or in the nonvolatile memory whose write endurance is high (shall be stored in a nonvolatile storage area).
An outline of operations of the first embodiment will be explained with
In the present invention, the read cache 103 and the write cache 104 are made up of two different nonvolatile memories whose characteristics are different, respectively: the nonvolatile memory whose write endurance is high is assigned to the write cache 104, and the nonvolatile memory whose write endurance is low is assigned to the read cache 103 giving first consideration to the data transfer speed, parts costs, etc. In this case, the table 107 for managing the data in the nonvolatile memory read cache 103 and the table 106 for managing the data in the nonvolatile memory write cache 104 are saved in a work area 108 that is provided on the write cache 104 whose write endurance is high. Storing the management tables 106, 107 of the data in the cache in the nonvolatile memory enables to prevent the loss of the data in the event of power supply cutoff. Moreover, placing the management tables 106, 107 of the data in the cache in the write cache 104 whose write endurance is high enables to prevent the depletion of the read cache 103 whose write endurance is low.
Although the volatile memory 109 is in the interior of the HDC 105, this volatile memory 109 may be placed outside the HDC 105. In the event of power supply cutoff, (if there is no supply of electric power by a battery etc.) the data on the volatile memory will be lost, but since what is lost is limited to the read data, it will not become data loss substantially.
Although counting of an access frequency (202 and 203 of
In the read processing, whether a cache-hit is made is checked (Step S401), and if the cache-hit is made, the read-access frequency of the entry at which the cache-hit was made is increased by one (Step S402). At this time, an entry having the same Tag 31 as that of the entry at which the cache-hit was made is retrieved. If there is an entry having the same Tag 301 as the Tag 301 of the entry at which the cache-hit was made (Step S403), the read access frequencies 302 of all the corresponding entries will be increased by one (Step S404). Performing the above processing enables assigning weights to an area where access frequency is high.
Next, a sequence of the read processing including a read cache control function will be explained using a flow of
At Step S502, if the read request data does not exist on the write cache 104, the HDC 105 accesses the nonvolatile memory read-data management table 106 on the write cache 104, and retrieves data on the nonvolatile memory read cache 103 (Step S505).
Existence of the appropriate data is checked (Step S506) and if the cache-hit is made, the cache-hit data will be transferred from the nonvolatile memory read cache 103 to the host (Step S507). Next, in the nonvolatile memory read-data management table 106, the read-access frequency 302 of the cache-hit data is increased by one (Step S508). At Step S506, if there is no cache-hit data in the cache, next the HDC 105 will access the volatile memory read-data management table 110 on the volatile memory 109 and will retrieve data on the volatile memory read cache 109 (Step S509).
Existence of the appropriate data is checked (Step S510), and if the cache-hit is made, the cache-hit data will be transferred from the volatile memory read cache 109 to the host (Step S511). Next, in the read data management table 110 of the volatile memory 109, the read-access frequency 302 of the cache-hit data is increased by one (Step S512). At Step S510, if no cache-hit data exists in the read cache of the volatile memory 109, the CPU 120 will access the disks 102, will read the read requested data from disks 102 by working with servo controlling unit 121 (Step S513), and will write it in the read cache of the volatile memory 109 and further transfer it to the host by working with HDC 105 (Step S514).
A series of processings were explained along a flow of
Incidentally, the flow of
As a result of searching all the caches, when a cache mistake occurs, the CPU accesses the disks 102 and reads the data by controlling servo control unit 121. However, the HDC is configured to write the data being read in the cache of volatile memory 109 (Step S514) and not to directly write the read data in the nonvolatile memory read cache 103. By restricting the writing of the read data to the nonvolatile memory read cache 103 in this way, it is possible to prevent a delay of the read processing (in the case where the write speed in the nonvolatile memory read cache is slow) or the depletion of the nonvolatile memory read cache.
Next, a sequence of the write processing including a write cache control function will be explained using a flow of
Although not described in the flow of
Next, the HDC searches the nonvolatile memory read-data management table 106 to retrieve whether there is any data of the same area (address) as that of the write data in the nonvolatile memory read cache 103 (Step S602).
The existence of the appropriate data is checked (Step S603), and if the cache-hit data exists, a valid/invalid bit of the cache-hit entry in the nonvolatile memory read-data management table 106 will be set invalid (Step S604). At Step S603, if there exists no data of the same area as that of the write data in the nonvolatile memory read cache 103, the HDC will access the volatile memory read-data management table 110 and will retrieve whether there will exist any data of the same area as that of the write data in the volatile memory read cache 109 (Step S605). The existence of the appropriate data is checked (Step S606), and if there exists the cache-hit data, a valid/invalid bit of the cache-hit entry in the volatile memory read-data management table will be set invalid (Step S607).
In the flow of
Next, a processing of writing the read data in the nonvolatile memory read cache 103 from the volatile memory read cache 109 will be explained using a flow of
The data management table 110 of the volatile memory 109 is accessed first, the read-access frequency 302 is searched, and the entry whose access frequency becomes equal to or more than a fixed number of times is retrieved (Step S701). The existence of a corresponding entry is checked (Step S702), and if there is the corresponding entry, data of the entry will be transferred to the nonvolatile memory read cache (Step S703).
Next, it is checked whether transfer of the cache-hit data from the volatile memory 109 is completed (Step S704). This processing is repeated until the transfer is completed. If the transfer is completed, management information of the cache-hit data is registered in the nonvolatile memory read-data management table 106, and at the same time a valid/invalid flag 303 of the cache-hit data is set valid (Step S705).
Next, the read data management table 110 of the volatile memory 109 is accessed, and a value of the valid/invalid flag of the transferred data is set invalid (Step S706).
The processing of
Next, a processing of writing data whose read frequency in the nonvolatile memory write cache 104 is high from its write cache 104 to the nonvolatile memory read cache 103 will be explained using a flow of
The HDC 105 accesses the nonvolatile memory write-data management table 107 recorded in the work area 108 of the nonvolatile memory write cache 104 and checks whether there is any entry whose read-access frequency 202 is higher than a predetermined access frequency (Step S801).
The corresponding entry is checked (Step S802), and if there is no corresponding entry, the processing will be ended. At Step S802, if there is the corresponding entry, data of the corresponding entry will be written on the disks 102 (Step S803).
Next, it is checked whether the data transfer from the nonvolatile memory write cache 104 to the disks 102 is completed (Step S804), and if the transfer is not completed, Step S804 will be repeated. When the data transfer to the disks is completed, it is checked whether the already transferred data has been updated in the nonvolatile memory write cache (Step S805). If the transferred data has been updated in the nonvolatile memory write cache, the flow will return to Step S801; and if the transferred data has not been updated, the data of the corresponding entry will be written in the nonvolatile memory read cache 103, its management data will be registered in the nonvolatile memory read-data management table 106 (Step S806), and the valid/invalid flag of the entry is set invalid at this point. Next, the HDC checks whether the data being transferred to the read cache 103 has been updated in the nonvolatile memory write cache (Step S807), and if not updated, the valid/invalid flag of the entry of the data being already transferred to the read cache will be set valid (Step S808). Next, the HDC sets the valid/invalid flag of the data being already transferred to be invalid in the nonvolatile memory write-data management table 107 (Step S809), and the flow returns to Step S801. If the data being transferred to the read cache 103 has been updated at Step S807, the flow will return to Step S801.
The processing of
In the flow of
In the processing of the flow of
In the flows of
In the below, by recording the access frequency of read or write considering all areas on the disks as objects, not limiting the data in the caches, it becomes possible to perform the followings: at the time of start or in the event of shutdown etc., extracting data in an area where the read-access frequency is especially high among all the areas on the disks and replacing it with data whose access frequency is low in the nonvolatile memory; or selecting data in an area whose write-access frequency is low among all the areas on the disks from the write cache and writing it on the disks.
Moreover, in the case where the size of the access frequency management table 111 is intended to be made small, there is a method whereby the area on the disks is divided into some areas and the access frequency is taken for each area. For example, it is allowable that based on Tags 201, 301 of the table shown in
As long as the size of the access frequency management table 111 is such a size as can be put into the work area 108 of the write cache 104 sufficiently, the table data may be recorded in the work area and may be accessed. Alternatively, it may be allowable that in case where the frequency table is formed sector by sector and the size of the table becomes large, a part of the table is copied in the cache of the volatile memory 109, the copied portion is made accessible and the portion is made to be updated and referred to any time. This is because in the case where the magnetic disk drive 101 is configured so that the frequency table on the disks 102 area is always accessed and the access frequency of the table is updated and referred to, updating and referring to the data in the table takes time.
In this case, since a part of the access frequency management table 111 is stored in the volatile memory 109, in the event of power supply cutoff, that table data copied in the volatile memory 109 will be lost. However, if the data of the access frequency management table on the volatile memory 109 is written in the access frequency management table 111 on the disks at an appropriate timing, since a situation of the access frequency at a short while before the power supply cutoff is recorded on the disks 102, it will not become a serious problem.
An HDC 105 checks whether the magnetic disk drive 101 is in a power saving mode (Step S1001), and if it is not in the power saving mode, checks whether it is currently in read/write access (Step S1002). If the magnetic disk drive 101 is not in read/write access, the disk controller 105 checks whether a certain amount of time has elapsed (a lapse time from the last access can be checked by using a timer in the magnetic disk drive) (Step S1003). If the time of no accessing elapsed over the certain amount of time, the access frequency management table copied in the volatile memory is written back in the access frequency management table for the whole that is recorded in the system area on the disks (Step S1004). The flow returning to Step S1003, if the time of no accessing does not elapse over the certain amount of time, the flow repeats Step S1003 until the certain amount of time elapses.
The flow returning to Step S1002, if it is in the read/write access, the processing will be ended. The flow returning to Step S1001, if the processing is in the power saving mode, the processing will be ended.
By the above processing, it is possible to, at a right time when the magnetic disk drive 101 is in an active state and the read and write is not performed, i.e., at an idle time, write back the access frequency management table on the volatile memory in the access frequency management table on the disks and to alter the access frequency management table on the disks to be in a latest state.
According to this embodiment, by forming the read/write caches with a combination of two kinds of nonvolatile memories that are different in write endurance, it is possible to provide an information device that realizes high persistence of the effect while suppressing an increase in cost and an increase in power consumption.
A second embodiment in which an information device of the present invention is applied to a magnetic disk drive will be described referring to
For example, the PRAM is assigned to the read cache 1103 of nonvolatile memory, and the MRAM is assigned to the write cache 1104 of nonvolatile memory.
Although in the read cache, a requirement for the read speed is high, a requirement for the write speed is low. On the other hand, although in the write cache, the requirement for the write speed is high, the requirement for the read speed is low. Therefore, the above way of using the memory properly becomes possible. What is necessary is just to use suitably properly two kinds of nonvolatile memories that are different in read speed and write speed according to a specification required of the cache memory device, such as performance of data processing speed etc. and a cost as a read cache and a write cache.
Since the nonvolatile memory that has a fast read speed but a slow write speed is assigned for the read cache and the nonvolatile memory that has a fast write speed but a slow read speed is assigned for the write cache, respectively, the tables for managing the data in the caches are placed in the respective caches. That is, a nonvolatile memory read-data management table 1106 for managing the read data in the nonvolatile memory read cache 1103 is placed in a work area 1108A of the nonvolatile memory read cache, and the nonvolatile memory data management table 1107 for managing the write data in the nonvolatile memory write cache 1104 is placed in a work area 1108B of the nonvolatile memory write cache. This is because, in order to make the most of read and write speed characteristics of the nonvolatile memory cache, the read speed and the write speed to each table need to be equal to or more than the read speed and the write speed of the nonvolatile memory caches.
Like the first embodiment, whether the volatile memory read cache 1109 and a volatile memory read-data management table 1110 are provided in HDC 105 depends on a difference between the read speed of the data from the disks and the write speed of the data in the nonvolatile memory read cache. That is, if the write speed of the nonvolatile memory read cache is slower than the read speed of the data from the disks, it will be necessary to provide the volatile memory read cache in the HDC. If there is no speed difference as mentioned above, it is not necessarily required to provide the volatile memory read cache in the HDC. Volatile memory may be provided outside the HDC if it is required to be provided.
Moreover, an access frequency management table 1111 is recorded on the disks 102. Configurations of the nonvolatile memory write-data management table 1107, the nonvolatile memory read-data management table 1106, the volatile memory read-data management table 1110, and the access frequency management table 1111 are the same as the configurations shown in the first embodiment, respectively. Configurations of other devices are the same as those of the first embodiment.
An outline of operations of the second embodiment will be explained with
In the second embodiment, the data in the nonvolatile memory caches is managed by the nonvolatile memory read-data management table 1106 being placed in the nonvolatile memory read cache 1103 and by the nonvolatile memory write-data management table 1107 being placed in the nonvolatile memory write cache 1104, respectively.
A reason of adopting such a configuration as described above is that, in order to make the most of the read and write speed characteristics of the nonvolatile memory cache, the read speed and the write speed to each table need to agree with the read speed and the write speed of the nonvolatile memory caches or to be larger than them, respectively.
According to this embodiment, by assigning the nonvolatile memory that has a fast write speed but a slow read speed to the write cache and assigning the nonvolatile memory that has a fast read speed but a slow write speed to the read cache, it is possible to attain improvement of the read and write speeds by the cache while suppressing increases in cost, power consumption, etc.
A third embodiment in which the information device of the present invention is applied to a magnetic disk drive will be described referring to
The magnetic disk drive of this embodiment is such that the read cache and the write cache are made up of two kinds nonvolatile memories that are different in power consumption, and a nonvolatile memory write-data management table 1307 for managing data of the nonvolatile memory write cache 1304 and a nonvolatile memory read-data management table 1306 for managing data of the nonvolatile memory read cache 1303 are recorded in respective work areas 1308B, 1308A of the nonvolatile memory write cache and the nonvolatile memory read cache, respectively.
In the third embodiment, the cache memory of volatile memory is not placed in the interior of the HDC 1305. The power consumption required by the read processing can be curtailed by reducing the number of caches in the read processing.
Configurations of the nonvolatile memory write-data management table 1307 and a nonvolatile memory read-data management table 1306 are the same as the configurations shown in the first embodiment, respectively. Configurations of other devices are the same as those of the first embodiment.
In this embodiment, for example, the read and write caches are constructed with two kinds of nonvolatile memories that are different in power consumptions at the time of write, and the write cache 1304 is made up of the nonvolatile memory whose power consumption at the time of write is small, or the read cache 1303 is made up of the nonvolatile memory whose power consumption at the time of write is small.
The MRAM is enumerated as the nonvolatile memory whose power consumption at the time of write is small. As an example mentioned above, it is conceivable that a nonvolatile memory cache whose power consumption at the time of write is small is assigned to a cache where a total amount of data to be written in the cache by a control of the HDC 1305 becomes larger, and a nonvolatile memory whose characteristic of the power consumption at the time of write is relatively inferior but whose other characteristics are superior is assigned to other cache. By doing in this way, it becomes possible to achieve reduction of the power consumption related to cache control.
Moreover, it is also recommendable that the read cache and the write cache are made up of two kinds of nonvolatile memories that are different in power consumption at the time of read, and the nonvolatile memory whose power consumption at the time of read is small is assigned to the read cache.
As the above-mentioned example, a cache of nonvolatile memory whose power consumption at the time of read is small is adopted for the nonvolatile memory read cache for storing an execution program such as an OS and an application. By doing in this way, it becomes possible to achieve reduction of the power consumption of the read cache of the nonvolatile memory whose read frequency becomes higher than the write frequency.
An outline of operations of the third embodiment will be explained with
In the third embodiment, although the nonvolatile memory read-data management table 1306 is placed in the nonvolatile memory read cache 1303, the nonvolatile memory write-data management table 1307 is placed in the nonvolatile memory write cache 1304, respectively, and thereby the data in the nonvolatile memory caches is controlled, the configuration does not need to be limited by this. Placement of the tables shall be placed so that the power consumption for accesses of read and write may become the minimum.
Moreover, in order to suppress the power consumption, the volatile memory read cache is not set up in the interior of the HDC 1305, but the cache memory device is configured so that the read data being read from the disks 102 is written directly in the read cache 1303 of nonvolatile memory in the third embodiment.
According to this embodiment, by forming the read and write caches with two kinds of nonvolatile memories that are different in power consumption characteristic, it is possible to suppress the power consumption required for a processing of caches while suppressing an increase in cost, reduction in read and write speeds, etc.
The information device 1501 of the present invention can perform connection of the northbridge, for example, using a dedicated bus.
The cache memory device 1501 of the present invention includes three kinds of cache memories: a read cache 1503 made up of volatile memory such as the DRAM, a write cache 1504 made up of nonvolatile memory such as the PRAM, and a read cache 1509 made up of nonvolatile memory such as the flash memory, and a controller 1505. A specific configuration and operations of the cache memory device 1501 are the same as those of the cache memory device of any one of the first embodiment to the third embodiment.
According to this embodiment, by forming the read and write caches by a combination of two kinds of nonvolatile memories whose characteristics are different, the effect by the cache can be enhanced while suppressing increases in cost, power consumption, etc. or the effect by the cache can be brought out to the maximum extent, so that it is possible to provide a PC that meets various requirements, such as low cost, high data transfer rate, and low power consumption.
According to this embodiment, by connecting a host 1610 and an HDD 1602 via the adapter 1600, it is possible to provide an apparatus that meets various requirements such as low cost, high data transfer rate, low power consumption, etc. while much enhancing the effect by the cache.
The host 1710 is a computer equipped with a CPU, memory, etc., recognizes logically storage areas of the plurality of HDD's 1702-1 to 1702-n provided by the storage controller 1716, and executes an application program using these logical storage areas (logical volumes). The disk adapter unit 1713 is a microcomputer, which functions as an interface for the HDD's 1702-1 to 1702-n.
According to this embodiment, it is possible to provide the storage system that meets the various requirements of low cost, high data transfer rate, low power consumption, etc. while much enhancing the effect by the cache.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-188174 | Aug 2010 | JP | national |
