Patent Grant
10846090
One or more aspects relate, in general, to processing within a computing environment, and in particular, to processing associated with generating pseudorandom numbers to be used in computer applications or other types of applications.
Pseudorandom numbers are numbers that appear random, but are not truly random. They are numbers generated by a deterministic computational process that provides statistically random numbers. Since the numbers are produced by a deterministic process, a given sequence of numbers can be reproduced at a later date, if the starting point is known. That is, given a particular function and seed value, the same sequence of numbers is generated by the function.
Pseudorandom numbers are used in numerous computer applications, such as simulation, cryptography, and procedural generation, as examples. Various implementations exist to generate pseudorandom numbers that can be used in these applications. These implementations include, for example, library subroutines, as well as a limited function of the Cipher Message with Chaining instruction available on some processors, such as IBM® z/Architecture capable processors.
Shortcomings of the prior art are overcome and advantages are provided through the provision of a computer program product for executing a machine instruction. The computer program product includes, for instance, a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method. The method includes, for instance, obtaining a machine instruction for execution, the machine instruction being defined for computer execution according to a computer architecture, the machine instruction including an opcode field to provide an opcode, the opcode to identify a perform pseudorandom number operation; and executing the machine instruction, the executing including: obtaining a modifier field associated with the machine instruction; based on the modifier field having a first value, performing a deterministic pseudorandom number generate operation, the deterministic pseudorandom number generate operation including: for each block of memory of one or more blocks of memory of a first operand located using the machine instruction, generating a hash value using a selected hash technique and at least one seed value of a parameter block associated with the machine instruction; and storing at least a portion of the generated hash value in a corresponding block of memory of the first operand, the generated hash value being at least a portion of a pseudorandom number.
Methods and systems relating to one or more aspects are also described and claimed herein. Further, services relating to one or more aspects are also described and may be claimed herein.
Additional features and advantages are realized through the techniques of one or more aspects. Other embodiments and aspects are described in detail herein and are considered a part of the claims.
One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
In one aspect, a machine instruction is provided for generating pseudorandom numbers. The instruction, referred to as a Perform Pseudorandom Number Operation instruction, includes capabilities to instantiate one or more seed values to be used to generate pseudorandom numbers, reseed one or more seed values, and/or generate pseudorandom numbers. As one example, the instruction uses a 512-bit secure hash algorithm (SHA-512) specified by the National Institute of Standards and Technology (NIST). It complies with the latest NIST recommendations for pseudorandom number generation. For performance reasons, however, the instruction operates in a right-to-left manner, rather than a left-to-right manner, as specified by NIST. In further embodiments, the instruction is extendable to use alternate encoding algorithms (also referred to as techniques).
One embodiment of a computing environment to incorporate and use one or more aspects is described with reference to
In one example, processor 102 is based on the z/Architecture offered by International Business Machines Corporation, and is part of a server, such as the System z server, which is also offered by International Business Machines Corporation and implements the z/Architecture. One embodiment of the z/Architecture is described in an IBM® publication entitled, “z/Architecture Principles of Operation,” IBM® Publication No. SA22-7832-09, Tenth Edition, Sep., 2012, which is hereby incorporated herein by reference in its entirety. In one example, the processor executes an operating system, such as z/OS, also offered by International Business Machines Corporation. IBM®, Z/ARCHITECTURE® and Z/OS® are registered trademarks of International Business Machines Corporation, Armonk, N.Y., USA. Other names used herein may be registered trademarks, trademarks, or product names of International Business Machines Corporation or other companies.
In a further embodiment, processor 102 is based on the Power Architecture offered by International Business Machines Corporation. One embodiment of the Power Architecture is described in “Power ISA™ Version 2.06 Revision B,” International Business Machines Corporation, Jul. 23, 2010, which is hereby incorporated herein by reference in its entirety. POWER ARCHITECTURE° is a registered trademark of International Business Machines Corporation.
In yet a further embodiment, processor 102 is based on an Intel architecture offered by Intel Corporation. One embodiment of the Intel architecture is described in “Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2B, Instructions Set Reference, A-L,” Order Number 253666-045US, January 2013, and “Intel® 64 and IA-32 Architectures Developer's Manual: Vol. 2B, Instructions Set Reference, M-Z,” Order Number 253667-045US, January 2013, each of which is hereby incorporated herein by reference in its entirety. Intel® is a registered trademark of Intel Corporation, Santa Clara, Calif.
Processor 102 includes a plurality of functional components used to execute instructions. As depicted in
Processor 102 also includes, in one embodiment, one or more registers 140 to be used by one or more of the functional components.
Another embodiment of a computing environment to incorporate and use one or more aspects is described with reference to
Native central processing unit 202 includes one or more native registers 210, such as one or more general purpose registers and/or one or more special purpose registers used during processing within the environment. These registers include information that represent the state of the environment at any particular point in time.
Moreover, native central processing unit 202 executes instructions and code that are stored in memory 204. In one particular example, the central processing unit executes emulator code 212 stored in memory 204. This code enables the computing environment configured in one architecture to emulate another architecture. For instance, emulator code 212 allows machines based on architectures other than the z/Architecture, such as PowerPC processors, pSeries servers, xSeries servers, HP Superdome servers or others, to emulate the z/Architecture and to execute software and instructions developed based on the z/Architecture.
Further details relating to emulator code 212 are described with reference to
Further, emulator 212 includes an emulation control routine 260 to cause the native instructions to be executed. Emulation control routine 260 may cause native CPU 202 to execute a routine of native instructions that emulate one or more previously obtained guest instructions and, at the conclusion of such execution, return control to the instruction fetch routine to emulate the obtaining of the next guest instruction or a group of guest instructions. Execution of the native instructions 256 may include loading data into a register from memory 204; storing data back to memory from a register; or performing some type of arithmetic or logic operation, as determined by the translation routine.
Each routine is, for instance, implemented in software, which is stored in memory and executed by native central processing unit 202. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software or some combination thereof. The registers of the emulated processor may be emulated using registers 210 of the native CPU or by using locations in memory 204. In embodiments, guest instructions 250, native instructions 256 and emulator code 212 may reside in the same memory or may be disbursed among different memory devices.
As used herein, firmware includes, e.g., the microcode, millicode and/or macrocode of the processor. It includes, for instance, the hardware-level instructions and/or data structures used in implementation of higher level machine code. In one embodiment, it includes, for instance, proprietary code that is typically delivered as microcode that includes trusted software or microcode specific to the underlying hardware and controls operating system access to the system hardware.
In one example, a guest instruction 250 that is obtained, translated and executed is the Perform Pseudorandom Number Operation instruction described herein. The instruction, which is of one architecture (e.g., the z/Architecture), is fetched from memory, translated and represented as a sequence of native instructions 256 of another architecture (e.g., PowerPC, pSeries, xSeries, Intel, etc.). These native instructions are then executed.
Details relating to the Perform Pseudorandom Number Operation instruction, including explicit and implied fields of the instruction, as well as execution by a central processing unit (either in a native or emulated system), are described herein. The Perform Pseudorandom Number Operation instruction includes a generate operation to generate pseudorandom numbers, as well as a seed operation to initiate or reseed one or more seed values used to generate the pseudorandom numbers. The seed values are stored in a parameter block accessed by the instruction.
Referring initially to
In one example, selected bits (e.g., the first two bits) of the opcode designated by opcode field 302 specify the length of the instruction. In this particular example, the selected bits indicate that the length is two halfwords. Further, the format of the instruction is a register-and-register operation with an extended opcode field. With this format, the contents of the register designated by the R1 field are called the first operand. The register containing the first operand is sometimes referred to as the first operand location. Further, the R2 field designates the register containing the second operand, and R2 may designate the same register as the R1 field.
In addition to R1 and R2 encoded in the instruction, one implementation of the instruction uses one or more implied registers including, for instance, general register 0 (GR0) and general register 1 (GR1). Each of the registers is further described below with reference to
Referring initially to
The query function (function code 0) provides the means of indicating the availability of other functions, including, but not limited to, other random or pseudorandom number generator functions. The R1 and R2 fields and the contents of general register 1 are ignored for the query function.
In this embodiment, for functions other than the query function, bit 56 is the modifier bit used to indicate a particular operation to be performed. For instance, when the modifier bit is zero, a generate operation is performed, and when the modifier bit is 1, a seed operation is performed. The modifier bit is ignored for the query function. All other bits of general register 0 are ignored in one implementation. In a further embodiment, if other functions are provided, they may or may not use the modifier bit.
Use of the function code and modifier bit are further described with reference to
Thereafter, a determination is made as to whether the function specified by the function code uses the modifier indicator, INQUIRY 384. If the modifier indicator is not used, then processing proceeds with performing the designated function, STEP 386. Otherwise, the modifier indicator is obtained, STEP 388, and processing proceeds based on the modifier indicator, STEP 390.
One embodiment of use of the modifier indicator is further described with reference to
If the value of the modifier bit is 0, then the generate operation of the SHA-512-DRNG function is performed, STEP 394. This includes, for instance, generating, for each block of memory of the first operand, a hash value using the 512 bit secure hash technique and one or more seed values in the parameter block; and storing at least a portion of the generated hash value in the first operand.
Otherwise, if the value of the modifier bit is 1, then a seed operation is performed, STEP 396. This includes, for instance, obtaining seed material, which is formed based on a value of a reseed counter and using information included in the second operand of the instruction; using the seed material and the 512 bit secure hash technique to provide one or more seed values; and storing the seed value(s) in the parameter block.
In other embodiments in which the function code represents other types of random number generator functions, the same modifier bit values may be used to determine whether a generate or seed operation is to be performed for that random number generator function. Additionally, in further embodiments, for other types of function codes specifying other types of functions, the value of the modifier indicator may specify different operations than described herein. Many variations are possible.
Continuing with a description of the instruction registers, referring to
For a seed operation, the R2 field 306 (
Regardless of whether a generate or seed operation is specified, the contents of the even-numbered general register designating the storage operand (R1 or R2, respectively) are subject to the addressing mode. In the 24-bit addressing mode, the contents of bit positions 40-63 of the register constitute the address of the storage operand, and the contents of bit positions 0-39 are ignored. In the 31-bit addressing mode, the contents of bit positions 33-63 of the register constitute the address of the storage operand, and the contents of bit positions 0-32 are ignored. In the 64-bit addressing mode, the contents of bit positions 0-63 of the register constitute the address of the storage operand. In the access-register mode, the respective access register (R1 or R2) specifies the address space containing the storage operand.
Regardless of whether a generate or seed operation is specified, in both the 24-bit and the 31-bit addressing modes, the contents of bit positions 32-63 of the odd-numbered general register (R1+1 or R2+1, respectively) form a 32-bit unsigned binary integer which specifies the number of bytes in the storage operand. In the 64-bit addressing mode, the contents of bit positions 0-63 of the register form a 64-bit unsigned binary integer which specifies the number of bytes in the storage operand.
For a generate operation, the first operand length is updated in general register R1+1 at the completion of the instruction. In both the 24-bit and the 31-bit addressing modes, the updated value replaces the contents of bit positions 32-63 of general register R1+1; the contents of bit positions 0-31 of general register R1+1 remain unchanged. In the 64-bit addressing mode, the updated value replaces the contents of general register R1+1.
When the parameter block overlaps any portion of the storage operand, the results are unpredictable.
When the storage operand length is zero, access exceptions for the storage operand location are not recognized. However, the parameter block is accessed even when the storage operand length is zero. For a generate operation, when the storage operand length is zero, general register R1+1 is not changed, and condition code 0 is set.
As observed by other CPUs and the I/O subsystem, references to the parameter block and storage operand may be multiple access references, accesses to these locations are not necessarily block concurrent, and the sequence of these accesses or references is undefined.
For a generate operation, when a PER (Program Event Recording—implemented on, for instance, processors based on the z/Architecture) storage alteration event is recognized, fewer than 4K additional bytes are stored into the first operand location before the event is reported. When a PER storage alteration event is recognized both for the first operand location and for the portion of the parameter block that is stored, it is unpredictable which of these two locations is indicated in the PER access identification (PAID) and PER ASCE ID (Program Event Recording address space control element identification (AI)). Similarly, when a PER zero-address-detection event is recognized for both for the first operand location and for the parameter block, it is unpredictable which of these two locations is identified in the PAID and AI.
For a generate operation, access exceptions may be reported for a larger portion of the first operand than is processed in a single execution of the instruction. However, access exceptions are not recognized for locations that do not encompass the first operand nor for locations more than 4K bytes from the current location being processed.
For a generate operation, when the operation ends due to normal completion, condition code 0 is set and the resulting value in general register R1+1 is zero. When the operation ends due to partial completion, condition code 3 is set and the resulting value in general register R1+1 is nonzero.
In one implementation, when the function code of the Perform Pseudorandom Number Operation instruction is 0 indicating a query function, a 128-bit status word 402 (
Condition code 0 is set when execution of the Query function completes; condition code 3 is not applicable to this function.
In one implementation, when the function code of the Perform Pseudorandom Number Operation instruction is 3, a deterministic random number generator (DRNG) function is performed. Depending on the modifier bit, bit 56 of general register 0, the DRNG function performs either a deterministic pseudorandom number generate operation or a deterministic pseudorandom number seed operation, each using the 512-bit secure hash algorithm (SHA-512).
Deterministic pseudorandom number generation, also known as deterministic random bit generation, is defined in, for instance, Recommendation for Random Number Generation Using Deterministic Random Bit Generators, National Institute of Standards and Technology (NIST), NIST Special Publication 800-90A, January 2012, which is hereby incorporated herein by reference in its entirety. Further, a description of the secure hash algorithm is found in, for instance, Secure Hash Standard (SHS), Federal Information Processing Standards Publication, FIPS PUB 180-4, National Institute of Standards and Technology, Gaithersburg, Md., March 2012, which is hereby incorporated herein by reference in its entirety.
One embodiment of a parameter block used for the DRNG function is depicted in
Reserved: Bytes 0-3, 16, and 128 of the parameter block are reserved.
Reseed Counter 422: Bytes 4-7 of the parameter block contain a 32-bit unsigned binary integer indicating the number of times that the instruction has completed with condition code 0 since the parameter block was last instantiated or reseeded.
When the reseed counter contains zero, the following applies:
When the reseed counter contains a nonzero value, the parameter block is considered to be instantiated, and the following applies:
Stream Bytes 424: Bytes 8-15 of the parameter block contain a 64-bit unsigned binary integer. The stream bytes field is set to zero by the execution of the seed operation when instantiating the parameter block (that is, when the reseed counter is zero); the field is not changed by the execution of the seed operation when the parameter block is already instantiated.
Partial or full completion of a generate operation causes the contents of the stream bytes field to be incremented by the number of bytes stored into the first operand; any carry out of bit position 0 of the stream bytes field is ignored.
Value (V) 426: Bytes 17-127 of the parameter block contain, for instance, an 888-bit value indicating the internal state of the random number generator represented by the parameter block. V is initialized by the execution of the seed operation when instantiating the parameter block. V is updated by either (a) the execution of the seed operation when the reseed counter is nonzero, or (b) the execution of the generate operation that ends in condition code 0.
Constant (C) 428: Bytes 129-239 of the parameter block contain, for instance, an 888-bit value indicating the internal state of the random number generator represented by the block. C is initialized by the execution of the seed operation, and inspected by the generate operation.
The same parameter block format is used by both the generate operation and the seed operation (including instantiation and reseeding). A parameter block containing all zeros is considered to be not instantiated. The program should zero the parameter block prior to issuing the seed operation to instantiate the parameter block, and subsequently, the program should not alter the contents of the parameter block except to zero it; otherwise, unpredictable results may be produced by the instruction.
Further details regarding the seed operation and the generate operation of the DRNG function (also referred to herein as the SHA-512-DRNG function) are described below.
Seed Operation
The SHA-512-DRNG seed operation instantiates or reseeds a deterministic pseudorandom number generation parameter block using the 512-bit secure hash algorithm. In one embodiment, the operation is performed by a central processing unit; however, in other embodiments, it is performed by other components or co-processors.
Depending on whether the reseed counter in bytes 4-7 of the parameter block is zero or nonzero, an instantiation or reseeding operation is performed, respectively. Further details of instantiation and reseeding are described below with reference to the figures. In the figures, the indicated symbols/abbreviations have the following meaning: <#>: length of field in bytes; R2+1: the length of operand 2 in storage in the range of 0-512 bytes; #bits: 32-bit count of bits to be produced by the SHA-512 algorithm—888 bits (378 hex); ct: 8-bit counter (e.g., m used by the hash derivation function); z: 8-bit field of zeros.
As an example, entropy input is an input bitstring that provides an assessed minimum amount of unpredictability for a Deterministic Random Bit Generator (DRBG) mechanism. A DRBG mechanism is the portion of a random bit generator (RBG) that includes the functions to instantiate and uninstantiate the RBG, generate pseudorandom bits, optionally reseed the RBG, and test the health of the DRBG mechanism.
A Random Bit Generator (RBG) is a device, algorithm, technique or mechanism that outputs a sequence of binary bits that appear to be statistically independent and unbiased. One example of an RBG is a DRBG. A DRBG is, for instance, an RBG that includes a DRBG mechanism and (at least initially) has access to a source of entropy input. The DRBG produces a sequence of bits from a secret initial value called a seed, along with other possible inputs.
A seed is a string of bits that is used as input to a DRBG mechanism. The seed determines a portion of the internal state of the DRBG, and its entropy is to be sufficient to support the security strength of the DRBG. Entropy is a measure of the disorder, randomness or variability in a closed system. Min-entropy is the measure used in one implementation
The min-entropy (in bits) of a random variable X is the largest value m having the property that each observation of X provides at least m bits of information (i.e., the min-entropy of X is the greatest lower bound for the information content of potential observations of X). The min-entropy of a random variable is a lower bound on its entropy. The precise formulation for min-entropy is −(log2 max pi) for a discrete distribution having probabilities p1, . . . , n, Min-entropy is often used as a worst case measure of the unpredictability of a random variable.
Nonce is a time-varying value that has at most a negligible chance of repeating, e.g., a random value that is generated anew for each use, a timestamp, a sequence number, or some combination of these.
Personalization string is an optional string of bits that is combined with a secret entropy input and (possibly) a nonce to produce a seed.
When performing an instantiation operation, seed material is formed using only the second operand, as depicted in
For either the instantiation or reseed operation, one or more seed values are initialized/updated. One such seed value is Vnew, which is formed as described with reference to
The SHA-512 algorithm is invoked twice to form two 64-bit hashed results 612a, 612b; the one-byte counter 600a contains the value 1 for the first invocation of the SHA-512 algorithm, and it contains the value 2 (600b) for the second invocation. The second invocation also uses a four byte value of 888 (602b), seed material 604b, and padding 606b as input to SHA-512 algorithm 608b, along with IHV 610b to form 64-bit hashed result 612b. In this example, 602b is the same value as 602a; 604b is the same as 604a; 606b is the same as 606a; and 610b is the same as 610a. However, in other embodiments, for instance, for other techniques, the values may be different from one another.
The two 64-byte hashed results 612a, 612b are concatenated together, and, in this example, the leftmost 111 bytes of the 128-byte concatenation form the new Value field (Vnew) 614 in the parameter block.
Similar to the formation of the Vnew field, a new constant field (Cnew) is formed during both the instantiation or reseeding operation. Cnew is another seed value stored in the parameter block. As shown in
The SHA-512 algorithm is invoked twice to form two 64-bit hashed results 712a, 712b; the one-byte counter 700a contains the value 1 for the first invocation of the SHA-512 algorithm, and it contains the value 2 (700b) for the second invocation. The second invocation also uses a four byte value of 888 (702b), a one byte value of zero (704b), Vnew field 706b, and padding 708b as input to SHA-512 algorithm 710b, along with IHV 711b. In this example, 702b is the same as 702a; 704b is the same as 704a; 706b is the same as 706a; 708b is the same as 708a; and 711b is the same as 711a. However, in other embodiments, for instance, for other techniques, they may be different from one another.
The two 64-byte hashed results 712a, 712b are concatenated together, and, in this example, the leftmost 111 bytes of the 128-byte concatenation form the new constant field (Cnew) 714.
For either the instantiate or reseed operation, the reseed counter field 720 in the parameter block is set to the value of one. For the instantiate operation only, the stream bytes field 722 in the parameter block is set zeros; the stream bytes field remains unchanged by a reseed operation.
Condition code 0 is set when execution of the SHA-512-DRNG seed operation completes; condition code 3 is not applicable to the seed operation.
Generate Operation
The SHA-512-DRNG generate operation generates pseudorandom numbers using the parameter block instantiated or reseeded, as described above, as well as the 512-bit secure hash algorithm. In one embodiment, the operation is performed by a central processing unit; however, in other embodiments, it is performed by other components or co-processors.
When the first operand length in general register R1+1 is nonzero, the first operand is stored in right-to-left order in units of 64-byte blocks, except that the rightmost block may contain fewer than 64 bytes. The number of blocks to be stored, including any partial rightmost block, is determined by rounding the first operand length in general register R1+1 up to a multiple of 64 and dividing the value by 64. The blocks of the first operand are numbered from left to right as 0 to n-1, where n-1 represents the rightmost block.
The following procedure is performed, in one implementation, for each block of the first operand location, beginning with the rightmost (n-1) block and proceeding to the left, as described with reference to
Referring initially to
The above process is repeated 820a-820n until either the first operand length in general register R1+1 is zero (called normal completion) or a CPU-determined number of blocks has been processed (called partial completion), INQUIRY 813 (
Based on performing the generate operation, the first operand includes a pseudorandom number.
When the first operand length in general register R1+1 is initially zero, normal completion occurs without storing into the first operand location; however, the parameter block is updated, as described with reference to
Referring to
When the pseudorandom number generation process ends due to partial completion, the first operand length in general register R1+1 contains a nonzero multiple of 64, the reseed counter and value (V) fields in the parameter block are not updated, and condition code 3 is set.
In one particular embodiment, a specification exception is recognized and no other action is taken if any of the following conditions exist:
Condition Code
0 Normal completion
1—
2—
3 Partial completion (generate operation only)
Program Exceptions:
One embodiment of further details of the SHA-512 algorithm is now described.
SHA-512
SHA-512 may be used to hash a message, M, having a length of ∝ bits, where 0≤∝<2128. The algorithm uses 1) a message schedule of eighty 64-bit words, 2) eight working variables of 64 bits each, and 3) a hash value of eight 64-bit words. The final result of SHA-512 is a 512-bit message digest.
The words of the message schedule are labeled W0, W1, . . . , W79. The eight working variables are labeled a, b, c, d, e, f g, and h. The words of the hash value are labeled H0(i), H1(i), . . . , H7(i), which will hold the initial hash value, H(o), replaced by each successive intermediate hash value (after each message block is processed), H(i), and ending with the final hash value, H(N). SHA-512 also uses two temporary words, T1 and T2.
The SHA-512 algorithm may use one or more of the following parameters:
Further, one or more of the following symbols is used in the secure hash algorithm specification; each operates on w-bit words:
Yet further, one or more of the following operations is used in the secure hash algorithm specification:
Moreover, the following operations are applied to w-bit words in the 512-bit secure hash algorithm. SHA-512 operates on 64-bit words (w=64).
Additionally, SHA-512 uses one or more of six logical functions, where each function operates on 64-bit words, which are represented as x, y, and z. The result of each function is a new 64-bit word.
CH(x, y, z)=(x∧y)⊕(¬x∧z)
Maj(x, y, z)=(x∧y)⊕(x,∧z)⊕(y∧z)
Σ0{512}(x)=ROTR28(x)⊕ROTR34(x)⊕ROTR39(x)
Σ1{512}(x)=ROTR14(x)⊕ROTR18(x)⊕ROTR41(x)
σ0{512}(x)=ROTR1(x)⊕ROTR8(x)⊕SHR7(x)
σ1{512}(x)=ROTR19(x)⊕ROTR61(x)⊕SHR6(x)
SHA-512 is described in two stages: Preprocessing and Hash Computation.
SHA-512 Preprocessing
Preprocessing involves padding a message, parsing the padded message into m-bit blocks, and setting initialization values to be used in the hash computation. Initialization, padding and parsing are described below.
Initialization
Set the initial hash value, H(0), as described below.
For SHA-512, the initial hash value, H(0), shall include the following eight 64-bit words, in hex:
H0(0)=6a09e667f3bcc908
H1(0)=bb67ae8584caa73b
H2(0)=3c6ef372fe94f82b
H3(0)=a54ff53a5f1d36f1
H4(0)=510e527fade682d1
H5(0)=9b05688c2b3e6c1f
H6(0)=1f83d9abfb41bd6b
H7(0)=5be0cd19137e2179
The words are obtained by taking the first sixty-four bits of the fractional parts of the square roots of the first eight prime numbers.
Padding the Message
The purpose of this padding is to ensure that the padded message is a multiple of 512 or 1024 bits, depending on the algorithm. Padding can be inserted before hash computation begins on a message, or at any other time during the hash computation prior to processing the block(s) that will contain the padding.
Suppose the length of the message M, in bits, is ∝ bits. Append the bit “1” to the end of the message, followed by k zero bits, where k is the smallest non-negative solution to the equation ∝+1+k=896mod1024. Then append the 128-bit block that is equal to the number ∝ expressed using a binary representation. For example, the (8-bit ASCII) message “abc” has length 8×3=24 , so the message is padded with a one bit, then 896−(24+1)=871 zero bits, and then the message length, to become the 1024-bit padded message
The length of the padded message is now a multiple of 1024 bits.
Parsing the Message
The message and its padding are parsed into N m-bit blocks.
For SHA-512, the message and its padding are parsed into N 1024-bit blocks, M(1), . . . , M(N). Since the 1024 bits of the input block may be expressed as sixteen 64-bit words, the first 64 bits of message block i are denoted M0(i), the next 64 bits are M1(i), and so on up to M15(t).
SHA-512 Hash Computation
The hash computation generates a message schedule from the padded message and uses that schedule along with functions, constants, and word operations to iteratively generate a series of hash values. The final hash value generated by the hash computation is used to determine the message digest.
The SHA-512 hash computation uses functions and constants, as described herein, and addition (+) is performed modulo 264.
Each message block, M(1), M(2), . . . , M(N), is processed in order, using the following steps:
1. Prepare the message schedule, {Wt}:
2. Initialize the eight working variables, a, b, c, d, e, f, g, and h, with the (i−1)st hash value:
a=H0(i−1)
b=H1(i−1)
c=H2(i−1)
d=H3(i−1)
e=H4(i−1)
f=H5(i−1)
g=H6(i−1)
h=H7(i−1)
3. For t=0 to 79:
4. Computer the ith intermediate hash value H(i):
After repeating steps one through four a total of N times (i.e., after processing M(N)), the resulting 512-bit message digest of the message, M, is
H0(N)∥H1(N)∥H2(N)∥H3(N)∥H4(N)∥H5(N)∥H6(N)∥H7(N)
where ∪ is concatenation.
Described above is one example of a CPU instruction to initially seed or reseed a pseudorandom number generator and/or to perform a generate operation to produce pseudorandom numbers. This instruction provides a high-performance means of generating pseudorandom numbers, meets the NIST standards, and is extendable to alternate generation techniques. The right-to-left processing of the instruction (e.g., in the generate operation) offers certain performance advantages since, for instance, certain information need not be saved.
In one example, the instruction is extendable by specifying additional function codes, each of which corresponds to a different algorithm used to perform the initiation, reseeding and/or generation. The different algorithms may include other algorithms to meet NIST standards. Examples of other algorithms include HMAC_DRBG (Hash-based Message Authentication Code_DRBG), CTR_DRBG (Counter-DRBG), and DUAL_EC_DRBG (Dual_Elliptic Curve_DRBG). Further, the function codes may be used to identify different hash or key lengths, such as 512, 256, or others. Thus, in one example, the function code includes an indication of an algorithm and an indication of hash or key length, which provides many possibilities aside from the SHA-512 technique described herein. Further, the function codes can specify other types of functions. Many possibilities exist.
Herein, memory, main memory, storage and main storage are used interchangeably, unless otherwise noted explicitly or by context.
As will be appreciated by one skilled in the art, aspects may be embodied as a system, method or computer program product. Accordingly, aspects may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system”. Furthermore, aspects may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.
Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable storage medium. A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.
Referring now to
Program code embodied on a computer readable medium may be transmitted using an appropriate medium, including but not limited to, wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations for aspects may be written in any combination of one or more programming languages, including an object oriented programming language, such as JAVA, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language, assembler or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).
Aspects are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to one or more embodiments. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider who offers management of customer environments. For instance, the service provider can create, maintain, support, etc. computer code and/or a computer infrastructure that performs one or more aspects for one or more customers. In return, the service provider may receive payment from the customer under a subscription and/or fee agreement, as examples. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.
In one aspect, an application may be deployed for performing one or more aspects. As one example, the deploying of an application comprises providing computer infrastructure operable to perform one or more aspects.
As a further aspect, a computing infrastructure may be deployed comprising integrating computer readable code into a computing system, in which the code in combination with the computing system is capable of performing one or more aspects.
As yet a further aspect, a process for integrating computing infrastructure comprising integrating computer readable code into a computer system may be provided. The computer system comprises a computer readable medium, in which the computer medium comprises one or more aspects. The code in combination with the computer system is capable of performing one or more aspects.
Although various embodiments are described above, these are only examples. For example, computing environments of other architectures can incorporate and use one or more aspects. Further, changes to the instructions may be made without departing from the one or more aspects. Moreover, other registers may be used. Additionally, in other embodiments (e.g., for other techniques), other values may be used in the concatenations or other computations. Other variations are also possible.
Further, other types of computing environments can benefit from one or more aspects. As an example, a data processing system suitable for storing and/or executing program code is usable that includes at least two processors coupled directly or indirectly to memory elements through a system bus. The memory elements include, for instance, local memory employed during actual execution of the program code, bulk storage, and cache memory which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.
Input/Output or I/O devices (including, but not limited to, keyboards, displays, pointing devices, DASD, tape, CDs, DVDs, thumb drives and other memory media, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.
Referring to
As noted, a computer system includes information in local (or main) storage, as well as addressing, protection, and reference and change recording. Some aspects of addressing include the format of addresses, the concept of address spaces, the various types of addresses, and the manner in which one type of address is translated to another type of address. Some of main storage includes permanently assigned storage locations. Main storage provides the system with directly addressable fast-access storage of data. Both data and programs are to be loaded into main storage (from input devices) before they can be processed.
Main storage may include one or more smaller, faster-access buffer storages, sometimes called caches. A cache is typically physically associated with a CPU or an I/O processor. The effects, except on performance, of the physical construction and use of distinct storage media are generally not observable by the program.
Separate caches may be maintained for instructions and for data operands. Information within a cache is maintained in contiguous bytes on an integral boundary called a cache block or cache line (or line, for short). A model may provide an EXTRACT CACHE ATTRIBUTE instruction which returns the size of a cache line in bytes. A model may also provide PREFETCH DATA and PREFETCH DATA RELATIVE LONG instructions which effects the prefetching of storage into the data or instruction cache or the releasing of data from the cache.
Storage is viewed as a long horizontal string of bits. For most operations, accesses to storage proceed in a left-to-right sequence. The string of bits is subdivided into units of eight bits. An eight-bit unit is called a byte, which is the basic building block of all information formats. Each byte location in storage is identified by a unique nonnegative integer, which is the address of that byte location or, simply, the byte address. Adjacent byte locations have consecutive addresses, starting with 0 on the left and proceeding in a left-to-right sequence. Addresses are unsigned binary integers and are 24, 31, or 64 bits.
Information is transmitted between storage and a CPU or a channel subsystem one byte, or a group of bytes, at a time. Unless otherwise specified, in, for instance, the z/Architecture, a group of bytes in storage is addressed by the leftmost byte of the group. The number of bytes in the group is either implied or explicitly specified by the operation to be performed. When used in a CPU operation, a group of bytes is called a field. Within each group of bytes, in, for instance, the z/Architecture, bits are numbered in a left-to-right sequence. In the z/Architecture, the leftmost bits are sometimes referred to as the “high-order” bits and the rightmost bits as the “low-order” bits. Bit numbers are not storage addresses, however. Only bytes can be addressed. To operate on individual bits of a byte in storage, the entire byte is accessed. The bits in a byte are numbered 0 through 7, from left to right (in, e.g., the z/Architecture). The bits in an address may be numbered 8-31 or 40-63 for 24-bit addresses, or 1-31 or 33-63 for 31-bit addresses; they are numbered 0-63 for 64-bit addresses. Within any other fixed-length format of multiple bytes, the bits making up the format are consecutively numbered starting from 0. For purposes of error detection, and in preferably for correction, one or more check bits may be transmitted with each byte or with a group of bytes. Such check bits are generated automatically by the machine and cannot be directly controlled by the program. Storage capacities are expressed in number of bytes. When the length of a storage-operand field is implied by the operation code of an instruction, the field is said to have a fixed length, which can be one, two, four, eight, or sixteen bytes. Larger fields may be implied for some instructions. When the length of a storage-operand field is not implied but is stated explicitly, the field is said to have a variable length. Variable-length operands can vary in length by increments of one byte (or with some instructions, in multiples of two bytes or other multiples). When information is placed in storage, the contents of only those byte locations are replaced that are included in the designated field, even though the width of the physical path to storage may be greater than the length of the field being stored.
Certain units of information are to be on an integral boundary in storage. A boundary is called integral for a unit of information when its storage address is a multiple of the length of the unit in bytes. Special names are given to fields of 2, 4, 8, and 16 bytes on an integral boundary. A halfword is a group of two consecutive bytes on a two-byte boundary and is the basic building block of instructions. A word is a group of four consecutive bytes on a four-byte boundary. A doubleword is a group of eight consecutive bytes on an eight-byte boundary. A quadword is a group of 16 consecutive bytes on a 16-byte boundary. When storage addresses designate halfwords, words, doublewords, and quadwords, the binary representation of the address contains one, two, three, or four rightmost zero bits, respectively. Instructions are to be on two-byte integral boundaries. The storage operands of most instructions do not have boundary-alignment requirements.
On devices that implement separate caches for instructions and data operands, a significant delay may be experienced if the program stores into a cache line from which instructions are subsequently fetched, regardless of whether the store alters the instructions that are subsequently fetched.
In one embodiment, the invention may be practiced by software (sometimes referred to licensed internal code, firmware, micro-code, milli-code, pico-code and the like, any of which would be consistent with one or more aspects). Referring to
The software program code includes an operating system which controls the function and interaction of the various computer components and one or more application programs. Program code is normally paged from storage media device 5011 to the relatively higher-speed computer storage 5002 where it is available for processing by processor 5001. The techniques and methods for embodying software program code in memory, on physical media, and/or distributing software code via networks are well known and will not be further discussed herein. Program code, when created and stored on a tangible medium (including but not limited to electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like is often referred to as a “computer program product”. The computer program product medium is typically readable by a processing circuit preferably in a computer system for execution by the processing circuit.
The system 5021 may communicate with other computers or networks of computers by way of a network adapter capable of communicating 5028 with a network 5029. Example network adapters are communications channels, token ring, Ethernet or modems. Alternatively, the system 5021 may communicate using a wireless interface, such as a CDPD (cellular digital packet data) card. The system 5021 may be associated with such other computers in a Local Area Network (LAN) or a Wide Area Network (WAN), or the system 5021 can be a client in a client/server arrangement with another computer, etc. All of these configurations, as well as the appropriate communications hardware and software, are known in the art.
Still referring to
Referring concurrently to
Alternatively, the programming code may be embodied in the memory 5025, and accessed by the processor 5026 using the processor bus. Such programming code includes an operating system which controls the function and interaction of the various computer components and one or more application programs 5032. Program code is normally paged from storage media 5027 to high-speed memory 5025 where it is available for processing by the processor 5026. The techniques and methods for embodying software programming code in memory, on physical media, and/or distributing software code via networks are well known and will not be further discussed herein. Program code, when created and stored on a tangible medium (including but not limited to electronic memory modules (RAM), flash memory, Compact Discs (CDs), DVDs, Magnetic Tape and the like is often referred to as a “computer program product”. The computer program product medium is typically readable by a processing circuit preferably in a computer system for execution by the processing circuit.
The cache that is most readily available to the processor (normally faster and smaller than other caches of the processor) is the lowest (L1 or level one) cache and main store (main memory) is the highest level cache (L3 if there are 3 levels). The lowest level cache is often divided into an instruction cache (I-Cache) holding machine instructions to be executed and a data cache (D-Cache) holding data operands.
Referring to
A program counter (instruction counter) 5061 keeps track of the address of the current instruction to be executed. A program counter in a z/Architecture processor is 64 bits and can be truncated to 31 or 24 bits to support prior addressing limits. A program counter is typically embodied in a PSW (program status word) of a computer such that it persists during context switching. Thus, a program in progress, having a program counter value, may be interrupted by, for example, the operating system (context switch from the program environment to the operating system environment). The PSW of the program maintains the program counter value while the program is not active, and the program counter (in the PSW) of the operating system is used while the operating system is executing. Typically, the program counter is incremented by an amount equal to the number of bytes of the current instruction. RISC (Reduced Instruction Set Computing) instructions are typically fixed length while CISC (Complex Instruction Set Computing) instructions are typically variable length. Instructions of the IBM z/Architecture are CISC instructions having a length of 2, 4 or 6 bytes. The Program counter 5061 is modified by either a context switch operation or a branch taken operation of a branch instruction for example. In a context switch operation, the current program counter value is saved in the program status word along with other state information about the program being executed (such as condition codes), and a new program counter value is loaded pointing to an instruction of a new program module to be executed. A branch taken operation is performed in order to permit the program to make decisions or loop within the program by loading the result of the branch instruction into the program counter 5061.
Typically an instruction fetch unit 5055 is employed to fetch instructions on behalf of the processor 5026. The fetch unit either fetches “next sequential instructions”, target instructions of branch taken instructions, or first instructions of a program following a context switch. Modern Instruction fetch units often employ prefetch techniques to speculatively prefetch instructions based on the likelihood that the prefetched instructions might be used. For example, a fetch unit may fetch 16 bytes of instruction that includes the next sequential instruction and additional bytes of further sequential instructions.
The fetched instructions are then executed by the processor 5026. In an embodiment, the fetched instruction(s) are passed to a dispatch unit 5056 of the fetch unit. The dispatch unit decodes the instruction(s) and forwards information about the decoded instruction(s) to appropriate units 5057, 5058, 5060. An execution unit 5057 will typically receive information about decoded arithmetic instructions from the instruction fetch unit 5055 and will perform arithmetic operations on operands according to the opcode of the instruction. Operands are provided to the execution unit 5057 preferably either from memory 5025, architected registers 5059 or from an immediate field of the instruction being executed. Results of the execution, when stored, are stored either in memory 5025, registers 5059 or in other machine hardware (such as control registers, PSW registers and the like).
A processor 5026 typically has one or more units 5057, 5058, 5060 for executing the function of the instruction. Referring to
An ADD instruction for example would be executed in an execution unit 5057 having arithmetic and logical functionality while a floating point instruction for example would be executed in a floating point execution having specialized floating point capability. Preferably, an execution unit operates on operands identified by an instruction by performing an opcode defined function on the operands. For example, an ADD instruction may be executed by an execution unit 5057 on operands found in two registers 5059 identified by register fields of the instruction.
The execution unit 5057 performs the arithmetic addition on two operands and stores the result in a third operand where the third operand may be a third register or one of the two source registers. The execution unit preferably utilizes an Arithmetic Logic Unit (ALU) 5066 that is capable of performing a variety of logical functions such as Shift, Rotate, And, Or and XOR as well as a variety of algebraic functions including any of add, subtract, multiply, divide. Some ALUs 5066 are designed for scalar operations and some for floating point. Data may be Big Endian (where the least significant byte is at the highest byte address) or Little Endian (where the least significant byte is at the lowest byte address) depending on architecture. The IBM z/Architecture is Big Endian. Signed fields may be sign and magnitude, 1's complement or 2's complement depending on architecture. A 2's complement number is advantageous in that the ALU does not need to design a subtract capability since either a negative value or a positive value in 2's complement requires only an addition within the ALU. Numbers are commonly described in shorthand, where a 12 bit field defines an address of a 4,096 byte block and is commonly described as a 4 Kbyte (Kilo-byte) block, for example.
Referring to
The execution of a group of instructions can be interrupted for a variety of reasons including a context switch initiated by an operating system, a program exception or error causing a context switch, an I/O interruption signal causing a context switch or multi-threading activity of a plurality of programs (in a multi-threaded environment), for example. Preferably a context switch action saves state information about a currently executing program and then loads state information about another program being invoked. State information may be saved in hardware registers or in memory for example. State information preferably comprises a program counter value pointing to a next instruction to be executed, condition codes, memory translation information and architected register content. A context switch activity can be exercised by hardware circuits, application programs, operating system programs or firmware code (microcode, pico-code or licensed internal code (LIC)) alone or in combination.
A processor accesses operands according to instruction defined methods. The instruction may provide an immediate operand using the value of a portion of the instruction, may provide one or more register fields explicitly pointing to either general purpose registers or special purpose registers (floating point registers for example). The instruction may utilize implied registers identified by an opcode field as operands. The instruction may utilize memory locations for operands. A memory location of an operand may be provided by a register, an immediate field, or a combination of registers and immediate field as exemplified by the z/Architecture long displacement facility wherein the instruction defines a base register, an index register and an immediate field (displacement field) that are added together to provide the address of the operand in memory for example. Location herein typically implies a location in main memory (main storage) unless otherwise indicated.
Referring to
Preferably addresses that an application program “sees” are often referred to as virtual addresses. Virtual addresses are sometimes referred to as “logical addresses” and “effective addresses”. These virtual addresses are virtual in that they are redirected to physical memory location by one of a variety of dynamic address translation (DAT) technologies including, but not limited to, simply prefixing a virtual address with an offset value, translating the virtual address via one or more translation tables, the translation tables preferably comprising at least a segment table and a page table alone or in combination, preferably, the segment table having an entry pointing to the page table. In the z/Architecture, a hierarchy of translation is provided including a region first table, a region second table, a region third table, a segment table and an optional page table. The performance of the address translation is often improved by utilizing a translation lookaside buffer (TLB) which comprises entries mapping a virtual address to an associated physical memory location. The entries are created when the DAT translates a virtual address using the translation tables. Subsequent use of the virtual address can then utilize the entry of the fast TLB rather than the slow sequential translation table accesses. TLB content may be managed by a variety of replacement algorithms including LRU (Least Recently used).
In the case where the processor is a processor of a multi-processor system, each processor has responsibility to keep shared resources, such as I/O, caches, TLBs and memory, interlocked for coherency. Typically, “snoop” technologies will be utilized in maintaining cache coherency. In a snoop environment, each cache line may be marked as being in any one of a shared state, an exclusive state, a changed state, an invalid state and the like in order to facilitate sharing.
I/O units 5054 (
Further, other types of computing environments can benefit from one or more aspects. As an example, an environment may include an emulator (e.g., software or other emulation mechanisms), in which a particular architecture (including, for instance, instruction execution, architected functions, such as address translation, and architected registers) or a subset thereof is emulated (e.g., on a native computer system having a processor and memory). In such an environment, one or more emulation functions of the emulator can implement one or more aspects of the present invention, even though a computer executing the emulator may have a different architecture than the capabilities being emulated. As one example, in emulation mode, the specific instruction or operation being emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.
In an emulation environment, a host computer includes, for instance, a memory to store instructions and data; an instruction fetch unit to fetch instructions from memory and to optionally, provide local buffering for the fetched instruction; an instruction decode unit to receive the fetched instructions and to determine the type of instructions that have been fetched; and an instruction execution unit to execute the instructions. Execution may include loading data into a register from memory; storing data back to memory from a register; or performing some type of arithmetic or logical operation, as determined by the decode unit. In one example, each unit is implemented in software. For instance, the operations being performed by the units are implemented as one or more subroutines within emulator software.
More particularly, in a mainframe, architected machine instructions are used by programmers, usually today “C” programmers, often by way of a compiler application. These instructions stored in the storage medium may be executed natively in a z/Architecture IBM® Server, or alternatively in machines executing other architectures. They can be emulated in the existing and in future IBM® mainframe servers and on other machines of IBM® (e.g., Power Systems servers and System x® Servers). They can be executed in machines running Linux on a wide variety of machines using hardware manufactured by IBM®, Intel®, AMD™, and others. Besides execution on that hardware under a z/Architecture, Linux can be used as well as machines which use emulation by Hercules, UMX, or FSI (Fundamental Software, Inc), where generally execution is in an emulation mode. In emulation mode, emulation software is executed by a native processor to emulate the architecture of an emulated processor.
The native processor typically executes emulation software comprising either firmware or a native operating system to perform emulation of the emulated processor. The emulation software is responsible for fetching and executing instructions of the emulated processor architecture. The emulation software maintains an emulated program counter to keep track of instruction boundaries. The emulation software may fetch one or more emulated machine instructions at a time and convert the one or more emulated machine instructions to a corresponding group of native machine instructions for execution by the native processor. These converted instructions may be cached such that a faster conversion can be accomplished. Notwithstanding, the emulation software is to maintain the architecture rules of the emulated processor architecture so as to assure operating systems and applications written for the emulated processor operate correctly. Furthermore, the emulation software is to provide resources identified by the emulated processor architecture including, but not limited to, control registers, general purpose registers, floating point registers, dynamic address translation function including segment tables and page tables for example, interrupt mechanisms, context switch mechanisms, Time of Day (TOD) clocks and architected interfaces to I/O subsystems such that an operating system or an application program designed to run on the emulated processor, can be run on the native processor having the emulation software.
A specific instruction being emulated is decoded, and a subroutine is called to perform the function of the individual instruction. An emulation software function emulating a function of an emulated processor is implemented, for example, in a “C” subroutine or driver, or some other method of providing a driver for the specific hardware as will be within the skill of those in the art after understanding the description of one or more embodiments. Various software and hardware emulation patents including, but not limited to U.S. Pat. No. 5,551,013, entitled “Multiprocessor for Hardware Emulation”, by Beausoleil et al.; and U.S. Pat. No. 6,009,261, entitled “Preprocessing of Stored Target Routines for Emulating Incompatible Instructions on a Target Processor”, by Scalzi et al; and U.S. Pat. No. 5,574,873, entitled “Decoding Guest Instruction to Directly Access Emulation Routines that Emulate the Guest Instructions”, by Davidian et al; and U.S. Pat. No. 6,308,255, entitled “Symmetrical Multiprocessing Bus and Chipset Used for Coprocessor Support Allowing Non-Native Code to Run in a System”, by Gorishek et al; and U.S. Pat. No. 6,463,582, entitled “Dynamic Optimizing Object Code Translator for Architecture Emulation and Dynamic Optimizing Object Code Translation Method”, by Lethin et al; and U.S. Pat. No. 5,790,825, entitled “Method for Emulating Guest Instructions on a Host Computer Through Dynamic Recompilation of Host Instructions”, by Eric Traut, each of which is hereby incorporated herein by reference in its entirety; and many others, illustrate a variety of known ways to achieve emulation of an instruction format architected for a different machine for a target machine available to those skilled in the art.
In
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of one or more aspects has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of one or more aspects. The embodiment was chosen and described in order to best explain the principles of the one or more aspects and the practical application, and to enable others of ordinary skill in the art to understand the one or more aspects for various embodiments with various modifications as are suited to the particular use contemplated.
This application is a continuation of co-pending U.S. Ser. No. 15/988,725, entitled “INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER GENERATE OPERATION,” filed May 24, 2018, which is a continuation of U.S. Ser. No. 15/008,850 entitled “INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER GENERATE OPERATION” filed Jan. 28, 2016, which is a continuation U.S. Ser. No. 14/519,621 entitled “INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER GENERATE OPERATION,” filed Oct. 21, 2014, which is a continuation of U.S. Ser. No. 13/828,057, entitled “INSTRUCTION FOR PERFORMING A PSEUDORANDOM NUMBER GENERATE OPERATION,” filed Mar. 14, 2013, each of which is hereby incorporated herein by reference in its entirety.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4162519 | Hanewinkel | Jul 1979 | A |
| 5365551 | Snodgrass et al. | Nov 1994 | A |
| 5416783 | Broseghini et al. | May 1995 | A |
| 5493687 | Garg et al. | Feb 1996 | A |
| 5551013 | Beausoleil et al. | Aug 1996 | A |
| 5574873 | Davidian | Nov 1996 | A |
| 5778069 | Thomlinson | Jul 1998 | A |
| 5790825 | Traut | Aug 1998 | A |
| 5830064 | Bradish et al. | Nov 1998 | A |
| 6009261 | Scalzi et al. | Dec 1999 | A |
| 6049612 | Fielder et al. | Apr 2000 | A |
| 6061703 | DeBellis | May 2000 | A |
| 6097815 | Shimada | Aug 2000 | A |
| 6104810 | DeBellis et al. | Aug 2000 | A |
| 6253223 | Sprunk | Jun 2001 | B1 |
| 6308255 | Gorishek, IV et al. | Oct 2001 | B1 |
| 6463582 | Lethin et al. | Oct 2002 | B1 |
| 6507808 | LaFauci | Jan 2003 | B1 |
| 6968460 | Gulick | Nov 2005 | B1 |
| 7209561 | Shankar et al. | Apr 2007 | B1 |
| 7234645 | Silverbrook et al. | Jun 2007 | B2 |
| 7249108 | Walmsley et al. | Jul 2007 | B1 |
| 7257718 | Lundvall et al. | Aug 2007 | B2 |
| 7904494 | Cho et al. | Mar 2011 | B2 |
| 7979482 | Gammel | Jul 2011 | B2 |
| 8015224 | Chaichanavong | Sep 2011 | B1 |
| 8374284 | Watson | Feb 2013 | B2 |
| 8873570 | Greiner et al. | Oct 2014 | B2 |
| 9128791 | Boppana | Sep 2015 | B1 |
| 9252953 | Greiner et al. | Feb 2016 | B2 |
| 9860056 | Greiner et al. | Jan 2018 | B2 |
| 10061585 | Greiner et al. | Aug 2018 | B2 |
| 20020059119 | Wiebe et al. | May 2002 | A1 |
| 20030037079 | Wilber | Feb 2003 | A1 |
| 20030059045 | Ruehle | Mar 2003 | A1 |
| 20030149863 | Henry et al. | Aug 2003 | A1 |
| 20030159036 | Walmsley et al. | Aug 2003 | A1 |
| 20030188044 | Bohizic et al. | Oct 2003 | A1 |
| 20030206630 | Rarick | Nov 2003 | A1 |
| 20040006680 | Duncan | Jan 2004 | A1 |
| 20040076293 | Smeets et al. | Apr 2004 | A1 |
| 20040098429 | Crispin et al. | May 2004 | A1 |
| 20040103286 | Geiringer et al. | May 2004 | A1 |
| 20040185785 | Mir et al. | Sep 2004 | A1 |
| 20050036610 | Krell | Feb 2005 | A1 |
| 20050097153 | Dirscherl | May 2005 | A1 |
| 20050193217 | Case | Sep 2005 | A1 |
| 20060039558 | Morii | Feb 2006 | A1 |
| 20060294312 | Walmsley | Dec 2006 | A1 |
| 20070005672 | Yushiya | Jan 2007 | A1 |
| 20070033242 | Wilber | Feb 2007 | A1 |
| 20070165842 | Lecomte et al. | Jul 2007 | A1 |
| 20070174374 | Inoha | Jul 2007 | A1 |
| 20070250719 | Lai | Oct 2007 | A1 |
| 20070266067 | Matsui | Nov 2007 | A1 |
| 20080010331 | Janke | Jan 2008 | A1 |
| 20080044014 | Corndorf | Feb 2008 | A1 |
| 20080177812 | Brandle | Jul 2008 | A1 |
| 20080181403 | Sakamoto | Jul 2008 | A1 |
| 20080258825 | Gressel et al. | Oct 2008 | A1 |
| 20080263117 | Rose et al. | Oct 2008 | A1 |
| 20080279370 | Hatakeyama | Nov 2008 | A1 |
| 20090060190 | Bauchot | Mar 2009 | A1 |
| 20090089578 | King et al. | Apr 2009 | A1 |
| 20090165086 | Trichina | Jun 2009 | A1 |
| 20090262928 | Busari | Oct 2009 | A1 |
| 20090300335 | Muff | Dec 2009 | A1 |
| 20090304179 | Gressel et al. | Dec 2009 | A1 |
| 20100002877 | Zhang | Jan 2010 | A1 |
| 20100017622 | Grinchuk et al. | Jan 2010 | A1 |
| 20100070549 | Nagaraj | Mar 2010 | A1 |
| 20110270676 | Vassilvitskii et al. | Nov 2011 | A1 |
| 20120079281 | Lowenstein | Mar 2012 | A1 |
| 20130010952 | Muise et al. | Jan 2013 | A1 |
| 20130159628 | Choquette | Jun 2013 | A1 |
| 20130262543 | Abdoo et al. | Oct 2013 | A1 |
| 20130262725 | Ito et al. | Oct 2013 | A1 |
| 20140164458 | Tkacik | Jun 2014 | A1 |
| 20140270162 | Greiner et al. | Sep 2014 | A1 |
| 20140280414 | Greiner et al. | Sep 2014 | A1 |
| 20150055778 | Cox et al. | Feb 2015 | A1 |
| 20150081751 | Greiner et al. | Mar 2015 | A1 |
| 20160202984 | Greiner et al. | Jul 2016 | A1 |
| 20180275992 | Greiner et al. | Sep 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 0582083 | Feb 1994 | EP |
| 2005534235 | Nov 2005 | JP |
| 2006337429 | Dec 2006 | JP |
| 2010152468 | Jul 2010 | JP |
| Entry |
|---|
| International Search Report and Written Opinion for PCT/IB2014/058916 dated Apr. 8, 2014, pp. 1-7. |
| “Secure Hash Standard (SHS),” Federal Information Processing Standards, FIPS PUB 180-4 Mar. 2012, pp. 1-35. |
| Barker, Elaine et al., “Recommendation for Random Number Generation Using Deterministic Random Bit Generations,” NIST Special Publication 800-90A, Computer Security Division, Information Technology Laboratory, Jan. 2012, pp. 1-136. |
| “Z/Architecture—Principles of Operation,” SA22-7832-09, Tenth Edition, Sep. 2012, pp. 1-1568. |
| International Search Report and Written Opinion for PCT/IB2014/058913 dated Jun. 13, 2014, pp. 1-12. |
| List of IBM Patents or Patent Applications Treated as Related, Feb. 22, 2019, 2 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20190065203 A1 | Feb 2019 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15988725 | May 2018 | US |
| Child | 16170913 | US | |
| Parent | 15008850 | Jan 2016 | US |
| Child | 15988725 | US | |
| Parent | 14519621 | Oct 2014 | US |
| Child | 15008850 | US | |
| Parent | 13828057 | Mar 2013 | US |
| Child | 14519621 | US |
