Patent Application
20060230259
I. Field of the Invention
The present disclosure pertains generally to digital signal processors, and more specifically to an instruction queue and method of operation.
II. Background
Digital signal processors are specialized microprocessors that are capable of executing operations with speed. Digital signal processors (DSPs) are commonly embedded in a variety of devices such as mobile telephones, personal digital assistants, and portable computing systems. The reduction of power consumption in these portable and mobile devices is an important design goal in order to maximize battery life. As functionality for these mobile devices expand to include multimedia and graphics applications, power consumption has become one of the most significant design and implementation considerations.
A consideration for reducing power consumption in digital signal processors is the energy used in the instruction memory unit when instructions are fetched from memory, instruction cache and instruction queue for execution, and when the fetched instructions are predecoded and decoded. Because digital signal processor programs typically spend the majority of time executing program loops, this characteristic may be exploited to reduce power consumption by the instruction memory unit.
In one aspect of an embodiment, a method comprises issuing a backward program redirect construct containing a backward branch path from an instruction queue, determining whether the backward branch path is being taken, determining whether a target instruction indicated by the backward branch path is already stored in the instruction queue in response to the backward branch path is being taken, issuing the target instruction from the instruction queue in response to it being already stored in the instruction queue, and fetching the target instruction from an instruction cache coupled to the instruction queue in response to the target instruction not already stored in the instruction queue.
In another aspect of an embodiment, a method comprises issuing a forward program redirect construct containing a forward branch path from an instruction queue, determining whether a last resolution of the forward program redirect construct reaches the same result as a current resolution of the forward program redirect construct, and issuing a next instruction from the instruction queue in response to same result being reached by the last and current resolution of the forward program redirect construct.
In yet another aspect of an embodiment, an instruction memory unit comprises a first memory structure operable to store program instructions, a second memory structure coupled to the first memory structure and operable to store program instructions fetched from the first memory structure, and operable to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward branch instruction, and issue a next program instruction already stored in the second memory structure in response to a resolution of the forward branching instruction identical to a last resolution of the same forward branching instruction. The second memory structure is further operable to issue a backward branch instruction stored in the second memory structure, determine whether a target instruction thereof is stored in the second memory structure, issue the target instruction in response to the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure in response to the target instruction not stored in the second memory structure.
Therefore, program loop executions are “captured” so that program loops may be executed from the instruction queue without having to fetch instructions out of the instruction cache for every iteration of the loop. As the instruction queue is much smaller than the instruction cache, significant power savings and speed may be achieved by avoiding the instruction cache during these program loop iterations. Further, because instructions in the instruction queue are already predecoded, there is additional power savings in not using the instruction decoding logic for program loop execution during instruction queue operating mode. As described above, the operation of the instruction memory unit in instruction queue or instruction cache operating mode does not require any software code in the program instructions to provide advanced notice to the instruction memory unit that a program loop execution is forthcoming and that special loop execution may take place.
Because the reduction of power consumption has become a vital design goal for mobile devices, design engineers are looking at all aspects of the device for opportunities to minimize total power use. One area of opportunity is the power consumed by the digital signal processor, and more specifically the power consumed by the digital signal processor during program loop execution. Digital signal processors may spend over 80% of the time executing program loops. These program loops may be of various sizes but most are small program loops containing fewer than ten program instructions, for example. When the number of times a loop is executed is deterministic such as a FOR loop, the zero-overhead loop construct is typically used. When the number of loop iteration is unknown such as a WHILE loop, a backward branch instruction is typically used. The instruction memory unit described herein and operation thereof exploit these digital signal processor execution characteristics to reduce power consumption and increase execution speed.
The instruction memory unit may operate in at least two modes: instruction cache mode and instruction queue mode. During the instruction cache mode, the instruction to be executed must be fetched from the instruction cache 12 into the instruction queue 14. During the instruction queue operating mode, the instructions to be executed are already loaded into the instruction queue 14 from the instruction cache 12, such as during iterations of a loop so that access to the instruction cache may be avoided. This strategy speeds up the operation of the instruction memory unit, and reduces power consumption by the instruction memory unit. Details of the operating modes of the instruction memory unit are set forth below.
FIGS. 2B-D are diagrammatical representations of exemplary contents of an embodiment of an instruction queue during three instruction execution scenarios. In
If in this iteration the branch forward path is not taken but was taken in the prior iteration as indicated by a T-bit that is set, then execution leaves the instruction queue mode and returns to an instruction cache mode. The T-bit is reset to indicate that the current branch is not taken. The sequential instructions after instruction I2, instructions 13 through I7 are loaded into entries 3 through 7 of the instruction queue 14, as shown by the contents 24 of the instruction queue shown in
If the backward branch path of instruction 17 is not taken while the operating mode is in the instruction queue mode, then the operating mode becomes the instruction cache mode and instructions 18 through 110 are also loaded into the instruction queue from the instruction cache.
If at
Referring to
If the T-bit is not set, as determined in block 54, then during the previous pass the forward branch path was not taken. The target instruction for the present forward program redirect construct is resolved in block 62. In block 64, a determination is made as to whether the forward branch path is being taken this time. If the forward branch is being taken, then the T-bit of the instruction queue address of the forward program redirect construct is set in block 66. The target instruction is then read from the instruction cache in block 68. This execution path results because the previous forward branch path was not taken (as indicated by the T-bit) and then taken this time. Therefore, the instruction queue does not contain the needed instructions and must be fetched from the instruction cache. If in block 64 it is determined that the forward branch path is not being taken this time, then the next instruction is already in the instruction queue, which is issued in block 70. This execution path results because the previous forward branch path was not taken (as indicated by the T-bit) and then also not taken this time. Therefore, the instruction queue already contains the needed instructions. Therefore, if the current and last resolution of the forward program redirect construct is identical and the instruction memory unit is operating in the instruction queue mode, then the next set of instructions are already in the instruction queue, which may be accessed by sequentially incrementing the instruction queue read pointer. During the instruction queue operating mode, no access to the instruction cache is necessary and significant savings in power consumption and greater speed are possible. If the current resolution is different from the previous resolution or if there is a program redirection instruction other than the forward program redirect construct, then the instruction memory unit transitions out of the instruction queue mode and into the instruction cache mode. The instruction cache is then accessed to fetch the target instruction.
Although not described herein, one or more pointers may be used to note the location(s) of instruction queue entries to issue and load instructions during the processes shown in
It may be seen from the foregoing that program loop executions are “captured” so that program loops may be executed from the instruction queue without having to fetch instructions out of the instruction cache for every iteration of the loop. As the instruction queue is much smaller than the instruction cache, significant power savings and speed may be achieved by avoiding the instruction cache during these program loop iterations. Further, because instructions in the instruction queue are already predecoded, there is additional power savings in not using the instruction decoding logic for program loop execution during instruction queue operating mode. As described above, the operation of the instruction memory unit in instruction queue or instruction cache operating mode does not require any software code in the program instructions to provide advanced notice to the instruction memory unit that a program loop execution is forthcoming and that special loop execution may take place.
Although embodiments of the present disclosure have been described in detail, those skilled in the art should understand that they may make various changes, substitutions and alterations herein without departing from the spirit and scope of the present disclosure. Accordingly, all such changes, substitutions and alterations are intended to be included within the scope of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.
