Claims
- 1. A method of manufacturing an insulated gate bipolar transistor comprising the steps of:
- preparing a first conductivity type semiconductor substrate having a first and a second major surface,
- forming a semiconductor layer of a second conductivity type which is opposite to said first conductivity type, on said first major surface of said semiconductor substrate;
- forming a first region of the first conductivity type in a surface of said semiconductor layer;
- forming a second region of the second conductivity type in a surface of said first region;
- forming an insulation film on the surface of said first region and extending between the surfaces of said semiconductor layer and second region;
- forming a control electrode on said insulation film;
- forming a trench in said first region through said second region;
- filling said trench with a conductive material including the step of doping said conductive material with an impurity;
- diffusing said impurity in said first region around said trench by employing said conductive material as a diffusion source to form a high concentration impurity diffusion region of the first conductivity type;
- forming a first electrode on said second region and said conductive material to electrically connect said second region and said conductive material; and
- forming a second electrode on said second major surface of said semiconductor substrate.
- 2. A method of manufacturing an insulated gate bipolar transistor comprising the steps of:
- preparing a first conductivity type semiconductor substrate having a first and a second major surface;
- forming a semiconductor layer of a second conductivity type, being opposite to said first conductivity type, on said first major surface of said semiconductor substrate;
- forming an insulation film over an entire surface of said semiconductor layer except for predetermined portions and forming a control electrode on said insulation film;
- forming a plurality of first regions of the first conductivity type in a surface of said semiconductor layer in the form of an array through the predetermined portions;
- forming a second region of the second conductivity type at the center of each said first region;
- forming a trench in a central portion of said second region to reach said first region through said second region;
- filling said trench with a conductive material including the step of doping said conductive material with an impurity;
- diffusing said impurity in said first region around said trench by employing said conductive material as a diffusion source to form a high concentration impurity diffusion region of the first conductivity type;
- forming an insulation film on said control electrode;
- forming a first electrode over a surface of said second region around said trench and a surface of said conductive material to electrically connect said first and second regions; and
- forming a second electrode on said second major surface of said semiconductor substrate.
Priority Claims (1)
Number |
Date |
Country |
Kind |
62-285807 |
Nov 1987 |
JPX |
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Parent Case Info
This is a division of application Ser. No. 07/195,652, filed on May 17, 1988 now U.S. Pat. No. 5,079,602.
US Referenced Citations (12)
Divisions (1)
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Number |
Date |
Country |
Parent |
195652 |
May 1988 |
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