Claims
- 1. A method of fabricating a semiconductor device, comprising:
providing a substrate; depositing a dielectric material over the substrate; forming a plurality of first conductive lines within the dielectric material, the first conductive lines including stack portions and non-stack portions; depositing an insulating cap layer over the first conductive lines and the dielectric material; patterning the insulating cap layer; removing portions of the insulating cap layer from over the first conductive line stack portions; and depositing a magnetic stack material over the insulating cap layer.
- 2. The method according to claim 1, wherein depositing the insulating cap layer comprises depositing an amorphous material.
- 3. The method according to claim 1, wherein depositing the insulating cap layer comprises depositing silicon dioxide or silicon nitride.
- 4. The method according to claim 1, further comprising:
patterning the magnetic stack material; and etching away portions of the magnetic stack material to form magnetic stacks over the stack portions of the first conductive lines.
- 5. The method according to claim 4, further comprising, after removing portions of the insulating cap layer from over the first conductive line stack portions:
depositing a conductive cap layer over the insulating cap layer; and planarizing the conductive cap layer to remove the conductive cap layer from over the insulating cap layer, leaving the conductive cap layer over the first conductive line stack portions.
- 6. The method according to claim 5, wherein planarizing the conductive cap layer comprises a chemical-mechanical polishing process.
- 7. The method according to claim 5, wherein depositing a conductive cap layer comprises depositing a conductive material having a top surface that is texturally smoother than the first conductive line top surface.
- 8. The method according to claim 5, wherein depositing a conductive cap layer comprises depositing a conductive material having a smaller grain structure than the grain structure of the first conductive lines.
- 9. The method according to claim 5, wherein depositing a conductive cap layer comprises depositing about 400 Angstroms of TaN, Ta, TiN or a copper alloy.
- 10. The method according to claim 5, wherein the method comprises fabricating a magnetic random access memory (MRAM) device, further comprising:
forming a plurality of second conductive lines over the magnetic stacks, wherein the second conductive lines run in a different direction than the first conductive line direction.
- 11. The method according to claim 10, further comprising:
annealing the conductive cap material; depositing a metallic hardmask over the magnetic stack material, after depositing the magnetic stack material; depositing an insulator over the insulating cap layer, after forming the magnetic stacks; and depositing an inter-level dielectric (ILD) material over the insulator, wherein the second conductive lines are formed within the ILD material.
- 12. A semiconductor device, comprising:
a substrate; a dielectric material formed over the substrate; a plurality of first conductive lines formed within the dielectric material, the first conductive lines including stack portions and non-stack portions; an insulating cap layer disposed over at least the first conductive line non-stack portions; and a magnetic material stack disposed over each first conductive line stack portion.
- 13. The semiconductor device according to claim 12, wherein the insulating cap layer is amorphous.
- 14. The semiconductor device according to claim 12, wherein the insulating cap layer comprises silicon dioxide or silicon nitride.
- 15. The semiconductor device according to claim 12, wherein the insulating cap layer is approximately 100 to 300 Angstroms thick.
- 16. The semiconductor device according to claim 12, further comprising a conductive cap layer disposed between the magnetic material stacks and the first conductive line stack portion.
- 17. The semiconductor device according to claim 16, wherein the insulating cap layer and the conductive cap layer comprise amorphous materials.
- 18. The semiconductor device according to claim 16, wherein the insulating cap layer comprises silicon dioxide or silicon nitride and the conductive cap layer comprises TaN, Ta, TiN or a copper alloy.
- 19. The semiconductor device according to claim 16, wherein the first conductive lines have a top surface, wherein the conductive cap layer has a top surface, and wherein the conductive cap layer top surface is texturally smoother than the first conductive line top surface.
- 20. The semiconductor device according to claim 16, wherein the conductive cap layer comprises a material having a smaller grain structure than the first conductive line material.
- 21. The semiconductor device according to claim 16, wherein the conductive cap layer is approximately 100 to 300 Angstroms thick.
- 22. The semiconductor device according to claim 16, wherein the magnetic material stacks comprise magnetic memory cells of a Magnetic Random Access Memory (MRAM) device, further comprising:
a plurality of second conductive lines disposed over the magnetic memory cells, wherein each magnetic memory cell is located at an intersection of a first and second conductive line.
- 23. The semiconductor device according to claim 22, further comprising:
a metallic hardmask disposed over the magnetic stacks; an insulator disposed over the insulating cap layer; and an inter-level dielectric (ILD) material disposed over the insulating cap layer, wherein the second conductive lines are formed within the ILD material.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present invention is related to U.S. patent application Ser. No. 10/143,673, filed on May 10, 2002 by Low, entitled “Surface-Smoothing Conductive Layer for Semiconductor Devices with Magnetic Material Layers”, which is incorporated herein by reference.