Patent Application
20250063748
The present disclosure relates to semiconductor devices and integrated circuit manufacture and, more specifically, to structures for an insulated-gate bipolar transistor and methods of forming a structure for an insulated-gate bipolar transistor.
Wide bandgap semiconductors, such as silicon carbide, may be used in high-power applications and/or high-temperature applications. Silicon carbide is well suited for power switching because of advantageous properties, such as a high saturated drift velocity, a high critical field strength, an exceptional thermal conductivity, and a significant mechanical strength. An insulated-gate bipolar transistor is a three-terminal power semiconductor device developed to combine high efficiency with fast switching. An insulated-gate bipolar transistor may leverage the favorable properties of a silicon carbide substrate to enable, for example, power converters, motor inverters, and motor drivers that are characterized by high reliability and high efficiency when operating at a high voltage.
Improved structures for an insulated-gate bipolar transistor and methods of forming a structure for an insulated-gate bipolar transistor are needed.
In an embodiment of the invention, a structure for a transistor is provided. The structure comprises a semiconductor substrate having a front surface and a back surface opposite from the front surface. The semiconductor substrate comprises a wide bandgap semiconductor material. The structure further comprises a gate electrode at the front surface of the semiconductor substrate, and a diode at the back surface of the semiconductor substrate.
In an embodiment of the invention, a method of forming a structure for a transistor is provided. The method comprises forming a gate electrode at a front surface of a semiconductor substrate. The semiconductor substrate comprises a wide bandgap semiconductor material, and the semiconductor substrate has a back surface opposite from the front surface. The method further comprises forming a diode at the back surface of the semiconductor substrate.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features in the various views.
With reference to
In an embodiment, the bulk substrate 12 may be lightly doped to have either n-type or p-type electrical conductivity. For example, the dopant concentration in the bulk substrate 12 may be about 1×1015 atoms per cubic centimeter to about 1×1017 atoms per cubic centimeter to provide the light doping. The light doping of the bulk substrate 12 may operate to minimize the defectivity (i.e., defect density) of the bulk substrate 12. In an alternative embodiment, the bulk substrate 12 may be heavily doped to have n-type electrical conductivity. For example, the dopant concentration in the bulk substrate 12 may be about 1×1018 atoms per cubic centimeter to about 1×1020 atoms per cubic centimeter to provide the heavy doping.
In an embodiment, the semiconductor layer 13 may be doped to have p-type electrical conductivity. In an embodiment, the semiconductor layer 14 may be doped to have n-type electrical conductivity. In an alternative embodiment, the semiconductor layer 14 may be omitted from the semiconductor substrate 11. In an embodiment, the semiconductor layer 15 may be doped to have n-type electrical conductivity at a lower dopant concentration than the semiconductor layer 14. In an embodiment, the semiconductor layer 15 may define a drift region of a field-effect transistor that is integrated into the insulating gate bipolar transistor, the semiconductor layer 14 may define a field stop region, and the semiconductor layer 13 may define a drain of the field-effect transistor that is integrated into the insulating gate bipolar transistor and a terminal (e.g., an emitter) of the insulating gate bipolar transistor.
The semiconductor substrate 11 has a front surface 17 and a back surface 27 that is opposite to the front surface 17. The semiconductor layer 15 adjoins the front surface 17, and the bulk substrate 12 adjoins the back surface 27 such that the entire thickness of the semiconductor substrate 11 is arranged between the front surface 17 and back surface 27. In an embodiment, both surfaces 17, 27 may be planar immediately after the semiconductor layers 13, 14, 15 are formed. The semiconductor layer 13 is disposed between the semiconductor layer 14 and the back surface 27. The semiconductor layers 14, 15 are disposed between the semiconductor layer 13 and the front surface 17. The semiconductor layer 15 is disposed between the semiconductor layer 14 and the front surface 17. The bulk substrate 12 is disposed between the semiconductor layer 13 and the back surface 27.
A doped region 16 may be formed in the semiconductor layer 15 adjacent to the front surface 17 of the semiconductor substrate 11. The doped region 16 is doped to have an opposite conductivity type from the semiconductor layer 15. The doped region 16 has a lower boundary that defines an interface with the underlying semiconductor material of the semiconductor layer 15 across which the dopant type changes. In an embodiment, the doped region 16 may define a body of the field-effect transistor that is integrated into the insulating gate bipolar transistor.
The doped region 16 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 15. An implantation mask may be formed to define a selected area on the front surface 17 of the semiconductor substrate 11 that is exposed for the implantation of ions. The implantation mask may include a hardmask that is applied and patterned to form an opening exposing the selected area on the front surface 17 and determining, at least in part, the location and horizontal dimensions of the doped region 16. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature) may be selected to tune the electrical and physical characteristics of the doped region 16, to minimize defects, and to maximize the ionization and activation of the implanted dopants. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. The implantation mask, which is compatible with the implantation conditions and is stripped following implantation, has a thickness and stopping power sufficient to block the implantation of ions in masked areas. In an embodiment, the doped region 16 may be doped with a concentration of a p-type dopant (e.g., aluminum) to provide p-type electrical conductivity.
A doped region 19 may be formed in the doped region 16. The doped region 19 may provide a body contact to the transistor body defined by the doped region 16. The doped region 19 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 15. An implantation mask may be formed to define a selected area on the front surface 17 of the semiconductor substrate 11 that is exposed for the implantation of ions. The implantation mask may include a hardmask that is applied and patterned to form an opening exposing the selected area on the front surface 17 and determining, at least in part, the location and horizontal dimensions of the doped region 19. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature) may be selected to tune the electrical and physical characteristics of the doped region 19, to minimize defects, and to maximize the ionization and activation of the implanted dopants. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. The implantation mask, which is compatible with the implantation conditions and is stripped following implantation, has a thickness and stopping power sufficient to block the implantation of ions in masked areas. In an embodiment, the doped region 19 may be doped with a concentration of a p-type dopant (e.g., aluminum) to provide p-type electrical conductivity, and the dopant concentration of the doped region 19 may be greater than the dopant concentration of the doped region 16. In an alternative embodiment, additional regions like the doped region 19 may be disposed within the doped region 16.
A doped region 18 may be formed in the semiconductor layer 15 adjacent to the front surface 17 of the semiconductor substrate 11. The doped region 18 has the same conductivity type as the semiconductor layer 15 but at a higher dopant concentration. The doped region 18 has an upper boundary that may be coplanar or substantially coplanar with the front surface 17 of the semiconductor substrate 11 and a lower boundary that defines an interface with the doped region 16 across which the conductivity type changes. In an embodiment, the doped region 18 may define a source of the field-effect transistor that is integrated into the insulating gate bipolar transistor and a terminal (e.g., a collector) of the insulating gate bipolar transistor.
The doped region 18 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 15. An implantation mask may be formed to define a selected area on the front surface 17 of the semiconductor substrate 11 that is exposed for the implantation of ions. The implantation mask may include a hardmask that is applied and patterned to form an opening exposing the selected area on the front surface 17 of the semiconductor substrate 11 and determining, at least in part, the location and horizontal dimensions of the doped region 18. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature) may be selected to tune the electrical and physical characteristics of the doped region 18. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. The implantation mask, which is compatible with the implantation conditions and is stripped following implantation, has a thickness and stopping power sufficient to block the implantation of ions in masked areas. In an embodiment, the doped region 18 may be doped (e.g., heavily doped) with a concentration of an n-type dopant (e.g., nitrogen and/or phosphorus) to provide n-type electrical conductivity. In an embodiment, the doped region 18 may be doped with a higher concentration of the n-type dopant than the semiconductor layer 15.
With reference to
A doped region 28 may be formed in the semiconductor layer 15 beneath and adjacent to the trench bottom 26 of each trench 22. The doped regions 28 have an opposite conductivity type from the semiconductor layer 15 and the doped region 16. The doped regions 28, which are formed after forming the trenches 22 and are self-aligned to the trenches 22, may define p-shields of the field-effect transistor that is integrated into the insulating gate bipolar transistor and may be connected to the doped region 16. The doped regions 28 may be connected to the doped regions 16, 19 and the doped region 18 by a doped region (not shown) that is disposed adjacent to the doped region 19 and that may have the same conductivity type as the doped regions 16, 19.
The doped regions 28 may be formed by introducing a dopant of a given conductivity type by, for example, ion implantation into the semiconductor layer 15. The trenches 22 in the dielectric layer 20 may determine, at least in part, the location and horizontal dimensions of the doped regions 28. The dielectric layer 20 has a thickness and stopping power sufficient to block the implantation of ions in masked areas. The implantation conditions (e.g., ion species, dose, kinetic energy, substrate temperature, tilt angle) may be selected to tune the electrical and physical characteristics of the doped regions 28. In an embodiment, the ion implantation may be performed at substrate temperature in a range of 200° C. to 600° C. to minimize defect formation. In an embodiment, the doped regions 28 may be doped with a concentration of a p-type dopant (e.g., aluminum) to provide p-type electrical conductivity.
A high-temperature anneal may be performed following the implantations to activate the implanted dopants and to alleviate post-implantation crystal damage. The high-temperature anneal may be performed with a removable carbon capping layer applied as a temporary coating and at a high temperature, such as a temperature in a range of 1600° C. to 1900° C., that is needed to activate the implanted dopants in a wide bandgap semiconductor material. The dielectric layer 20, which cannot withstand the high anneal temperature, is removed from the front surface 17 before the anneal is performed and before the carbon capping layer is applied. The removable carbon capping layer may prevent silicon outgassing during the high-temperature anneal. The carbon capping layer, which may be comprised of a cured and/or baked photoresist or a deposited layer of carbon, is removed following the high-temperature anneal.
With reference to
With reference to
The portion of the gate conductor layer 32 and the gate dielectric layer 34 inside the trenches 22 define a gate of the insulated gate bipolar transistor. The gate is disposed at the front surface 17 of the semiconductor substrate 11. The gate dielectric layer 34 electrically insulates the portions of the gate conductor layer 32 from the surfaces of the semiconductor layer 15.
With reference to
Silicide layers 42 are formed by a silicidation process on exposed areas of the front surface 17. The silicide layers 42 may be comprised of a metal, such as nickel. An electrode 44 comprised of, for example, aluminum may be formed that is coupled by the silicide layers 42 to the doped region 19 and doped region 18. A barrier layer 41, such as a bilayer of titanium and titanium nitride, may be disposed between the electrode 44 and the silicide layers 42. The dielectric layer 38 inside each trench 22 electrically isolates the electrode 44 from the gate electrodes defined by the portions of the gate conductor layer 36 inside the trenches 22.
With reference to
The trenches 48 divide the bulk substrate 12 and the semiconductor layer 13 into stacked sections. In particular, each trench 48 is disposed in a lateral direction between different sections of the semiconductor layer 13 and different sections of the bulk substrate 12 that are stacked with the sections of the semiconductor layer 13. The sections of the semiconductor layer 13 are disposed between the sections of the bulk substrate 12 and the semiconductor layer 14. Each section of the semiconductor layer 13 adjoins a portion of the semiconductor layer 14 to define a diode having a respective junction across which the conductivity type of the wide bandgap semiconductor material changes. The diodes may be reverse conducting diodes during device operation. The surface of a portion of the semiconductor layer 14 is disposed in a lateral direction at the trench bottom 52 between each adjacent pair of the trenches 48.
In an embodiment, the bulk substrate 12 and semiconductor layer 13 at the sidewalls 54 of the trenches 48 may be doped by, for example, a tilted ion implantation of a p-type dopant with rotation of the semiconductor substrate 11. In an embodiment, the semiconductor layer 14 at the trench bottoms 52 of the trenches 48 may be doped by, for example, a normal-incidence ion implantation of an n-type dopant. The resist layer used to pattern the trenches 48 may be used as an implantation mask. The semiconductor substrate 11 may be optionally annealed by a low-temperature furnace anneal or a laser anneal after the implantation(s).
With reference to
In an embodiment, the layer 56 may be comprised of a conductor. In an embodiment, the layer 56 may be comprised of a metal silicide, such as nickel silicide. In an embodiment, the layer 56 may be comprised of a metal, such as nickel, that is conformally deposited and optionally heated using a laser in order to locally form a low-resistance nickel silicide contact to the exposed semiconductor material. In an embodiment, the layer 56 may include a layer stack comprised of multiple metal layers, such as a layer stack of titanium, nickel, and silver or a layer stack of titanium, nickel, and gold. In an embodiment, the layer 56 may include a metal silicide layer and a layer stack comprised of multiple metal layers, such as a layer stack of titanium, nickel, and gold. The layer 56 may also be comprised of a layer of a metal, such as aluminum. The layer 56 is disposed on each section of the semiconductor layer 13 and portions of the semiconductor layer 14 between the trenches 48 as a continuous coating. The layer 56 connects the sections of the semiconductor layer 13 of the different diodes in series.
The structure 10 includes reverse conducting diodes that are monolithically integrated with the insulated-gate bipolar transistor. The reverse conducting diodes are formed at the back surface 27 of the semiconductor substrate 11 after the insulated-gate bipolar transistor is formed at the front surface 17 of the semiconductor substrate 11. The formation of the reverse conducting diodes is compatible with processing requirements for wide bandgap semiconductor materials. In that regard, implantation and activation of dopants by a high-temperature anneal is not required to form the reverse conducting diodes at the back surface 27.
In an alternative embodiment, the insulated-gate bipolar transistor may have a planar-gate construction instead of the trench-gate construction. In that regard, the gate dielectric layer 34 and the gate conductor layer 36 may be formed on the front surface 17 of the semiconductor substrate 11 instead of inside the trenches 22.
The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. The chip may be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product or an end product. The end product can be any product that includes integrated circuit chips, such as computer products having a central processor or smartphones.
References herein to terms modified by language of approximation, such as “about”, “approximately”, and “substantially”, are not to be limited to the precise value specified. The language of approximation may correspond to the precision of an instrument used to measure the value and, unless otherwise dependent on the precision of the instrument, may indicate a range of +/−10% of the stated value(s).
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate, regardless of its actual three-dimensional spatial orientation. The terms “vertical” and “normal” refer to a direction in the frame of reference perpendicular to the horizontal, as just defined. The term “lateral” refers to a direction in the frame of reference within the horizontal plane.
A feature “connected” or “coupled” to or with another feature may be directly connected or coupled to or with the other feature or, instead, one or more intervening features may be present. A feature may be “directly connected” or “directly coupled” to or with another feature if intervening features are absent. A feature may be “indirectly connected” or “indirectly coupled” to or with another feature if at least one intervening feature is present. A feature “on” or “contacting” another feature may be directly on or in direct contact with the other feature or, instead, one or more intervening features may be present. A feature may be “directly on” or in “direct contact” with another feature if intervening features are absent. A feature may be “indirectly on” or in “indirect contact” with another feature if at least one intervening feature is present. Different features “overlap” if a feature extends over, and covers a part of, another feature.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
