Patent Application
20120153427
The subject matter described herein relates generally to integrated circuits and, more particularly, to methods and apparatus for fabricating integrated circuits that facilitate electrical isolation of components on a semiconductor wafer, chip, or die, and facilitate use of the integrated circuits in high-temperature environments.
At least some known silicon carbide (SiC) integrated circuits include a wafer substrate that includes at least one semiconducting layer. The substrate is sometimes referred to as the body and may be fabricated from a p-type material, an n-type material, and/or a semi-insulating material. Further, the SiC integrated circuits may, or may not, have an epitaxial layer formed on top of the substrate.
Many of these known SiC integrated circuits include a plurality of electronic devices, for example, transistors, resistors, and diodes, and include a body terminal embedded in a portion of the substrate. Such body terminals share the same substrate and are therefore substantially electrically coupled. However, the substrate can only be maintained at a single voltage and the body terminals of the transistors and the substrate are maintained at the lowest voltage potential of the plurality of transistors to facilitate proper operation of the integrated circuit. Energizing the substrate to a particular voltage is often referred to as back-biasing. The source terminals of each transistor can be energized to voltages different from the substrate. Therefore, the source-to-body voltage differential, i.e., VSB, sometimes referred to as a reverse-bias voltage, is maintained at approximately 0 volts (V) or higher. Otherwise, if the body voltage exceeds a source voltage for a transistor, the body and source junction may operate as a diode and current paths will form between source terminals of different transistors,
When the source voltage exceeds the body voltage, an incremental increase in VSB facilitates an incremental increase in the VTH of the transistor, thereby necessitating an incremental increase in a gate-to-source voltage (VGS) to overcome the increased VTH. Furthermore, an incremental increase in VTH of the transistor facilitates an incremental decrease in a drain-to-source (or, source-to-drain) current. Therefore, body voltage has an effect on the operation of the affected transistor, and the body acts as a second gate. Such effect is referred to as the “body effect”.
In some known integrated circuits, in order to facilitate conditions such that VSB is a positive value, each transistor includes a hard-wired interconnection to each associated body terminal to attain the lowest voltage potential required for that particular set of transistors. These connections increase the interconnect complexity of the integrated circuit. The additional hard-wired interconnections increase the die area required for fabrication of the integrated circuit, decrease a yield per wafer, chip, or die, and increase a cost of integrated circuit fabrication.
Moreover, many known integrated circuits include other electronic devices, for example, resistive devices such as resistors that include resistive properties that are voltage and temperature dependent. Therefore, varying voltage conditions associated with the common substrate during dynamic operation of the integrated circuit induces variations in the resistance of the resistive devices, and thus detrimentally affects circuit performance. Furthermore, varying environmental conditions associated with the technical or industrial application of the integrated circuit may include significant temperature variations that will also vary the resistance. Anticipation of such varying circuit voltages and temperatures impose either more restrictive constraints on integrated circuit design and fabrication of the circuits, more restrictive constraints on industrial applications, or more complex and costly fabrication materials and techniques.
Furthermore, many known integrated circuits are limited to operating temperatures of approximately 175 degrees Celsius (° C.) (347 degrees Fahrenheit (° F.)), while many industrial applications include environments that exceed 175° C. Hardening integrated circuits to be more robust in such high-temperature environments significantly increases design and fabrication costs of such circuits.
In one aspect, a method includes providing a substrate with at least one semiconducting layer. The method also includes forming a plurality of isolation barriers within the at least one semiconducting layer, thereby forming a plurality of device islands. The method further includes inserting a plurality of electronic devices into a portion of the at least one semiconducting layer such that each electronic device is substantially isolated from each other electronic device by the device islands.
In another aspect, a device includes a substrate including at least one semiconducting layer. The device also includes a plurality of isolation barriers extending through the at least one semiconducting layer and defining at least one device island. The device also includes a plurality of electronic devices. At least one electronic device of the plurality of electronic devices is inserted onto the at least one device island.
In yet another aspect, an apparatus includes a base and a plurality of isolation barriers extending through at least a portion of the base. At least a portion of the plurality of isolation barriers defines a plurality of base islands. The apparatus also includes a plurality of electronic devices. At least one electronic device of the plurality of electronic devices is inserted onto each of the plurality of base islands.
These and other features, aspects, and advantages of the presently described embodiments will become better understood when the following detailed description is read with reference to the accompanying drawings in which like characters represent like parts throughout the drawings, wherein:
In the following specification and the claims, which follow, reference will be made to a number of terms, which shall be defined to have the following meanings
The singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise.
“Optional” or “optionally” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not.
Approximating language, as used herein throughout the specification and claims, may be applied to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it is related. Accordingly, a value modified by a term or terms, such as “about” and “substantially”, are not to be limited to the precise value specified. In at least some instances, the approximating language may correspond to the precision of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and/or interchanged, such ranges are identified and include all the sub-ranges contained therein unless context or language indicates otherwise.
The example integrated circuits and methods described herein may overcome disadvantages of known integrated circuits by defining a trench and/or a body well within a semiconducting layer between each individual electronic device positioned on the integrated circuit. The trenches and body wells can be formed using known methods of photolithography patterning and etching. The trenches can be filled with non-conductive materials that do not substantially increase costs of circuit fabrication. The body wells can be filled with a doped material that does not substantially increase costs of circuit fabrication. The trenches and body wells are isolation barriers. Each isolation barrier can surround a transistor, diode, or a resistor, thereby substantially eliminating electrical connectivity between a body terminal of a device and a body terminal of other devices. Such etching may be deep enough to extend through the semiconducting layer that houses the body of transistors and resistors, thus forming islands and isolating each device. Such island isolation may significantly reduce the body effect, i.e., the effect attained if a source terminal voltage exceeds a body voltage at which the substrate is maintained, thereby facilitating improvements in circuit performance.
Also, such isolation facilitates reducing a complexity of circuit interconnectivity, thereby potentially reducing an associated die area, facilitating an increase in yield per wafer, and facilitating a reduction of cost per die. Moreover, such isolation may facilitate a reduction of voltage variations in the vicinities of each resistor in the integrated circuit, thereby further facilitating improved circuit performance with varying operating conditions and further facilitating simplifying circuit design. Furthermore, decreasing voltage variations facilitates increasing functionality of integrated circuits in apparatus that include a wider tolerance range for varying temperatures, including extended high-temperature operations. Examples of such high-temperature apparatus include high-temperature tools and equipment for exploration of deep oil wells, in some case in conditions in excess of 175 degrees Celsius (° C.) (347 degrees Fahrenheit (° F.)), including temperatures that exceed 300° C. (572° F.), and in some cases, up to 500° C. (932° F.) for extended periods of time.
Circuit 100 also includes a first electronic device, or transistor 106 embedded within substrate 102. Circuit 100 also includes a second electronic device, or transistor 108 embedded within substrate 102. Circuit 100 further includes a first body terminal 110 associated with first transistor 106 and a second body terminal 112 associated with second transistor 108. First body terminal 110 and second body terminal 112 are coupled to each other via a body terminal interconnection 114. Circuit 100 also includes a first source terminal 116 coupled to first transistor 106 and a second source terminal 118 coupled to second transistor 108. Circuit 100 further includes a first drain terminal 120 coupled to first transistor 106 and a second drain terminal 122 coupled to second transistor 108. Circuit 100 also includes a first gate terminal 124 coupled to first transistor 106 and a second gate terminal 126 coupled to second transistor 108.
First transistor 106 has a first threshold voltage, or VTH1, wherein VTH1 is the first gate-to-first source differential voltage at which a current path (not shown) between first source terminal 116 and first drain terminal 120 is formed such that electric current flows therebetween and first transistor 106 changes from an “off” state to an “on” state. Similarly, second transistor 108 has a second threshold voltage, or VTH2, wherein VTH2 is the second gate-to-second source differential voltage at which a current path (not shown) between second source terminal 118 and second drain terminal 122 is formed such that electric current flows therebetween and second transistor 106 changes from an “off” state to an “on” state.
In operation, first source terminal 116 is energized to a source voltage of approximately 0 volts (V) and first gate terminal 124 has a gate voltage of approximately 0V. Therefore, the differential voltage is approximately 0V which is less than VTH1 and first transistor 106 is in an “off” state. As the gate voltage increases and the differential voltage between first gate terminal 124 and first source terminal 116, i.e., VGS1 exceeds VTH1, first transistor 106 changes to an “on” state. Also, in operation, second source terminal 118 is energized to a source voltage of approximately 1V and second gate terminal 126 has a gate voltage of approximately 1V. Therefore, the differential voltage between second gate terminal 126 and second source terminal 118, i.e., VGS2, is approximately 0V which is less than VTH2 and second transistor 108 is in an “off” state. As the gate voltage increases and VGS2, exceeds VTH2, second transistor 108 changes to an “on” state.
First body terminal 110 and second body terminal 112 share semiconducting layer 104 and are substantially electrically coupled, therefore, terminals 110 and 112 and semiconducting layer 104 can only be maintained at a single voltage. Body terminal interconnection 114 facilitates maintaining first body terminal 110, second body terminal 112, and semiconducting layer 104 at approximately 0V, thereby maintaining a source-to-body voltage differential, i.e., VSB, sometimes referred to as a reverse-bias voltage, at approximately 0V for first transistor 106 and approximately 1V for second transistor 108, thereby subjecting second transistor 108 to the body effect as described herein. First body terminal 110, second body terminal 112, and semiconducting layer 104 are maintained at the lowest voltage potential of transistors 106 and 108 to facilitate proper operation of integrated circuit 100. Therefore, the lowest voltage of 0V is selected rather than 1V.
Otherwise, if the voltage of 1V were selected, the voltage of semiconducting layer 104 exceeds the voltage of 0V for first source terminal 116 for first transistor 106. In some circumstances, first body terminal 110 and first source terminal 116 cooperate to act in a manner similar to a diode and may forward-bias to facilitate electric current flow within semiconducting layer 104 and disrupt normal transistor operation.
Also, otherwise, if the voltage of 0V is selected, if base terminal interconnection 114 is not present, and if the voltage of second source terminal 118 is 1V, the voltage of second source terminal 118 exceeds the voltage of semiconducting layer 104. Such conditions give rise to the body effect. The incremental increase in VSB facilitates an incremental increase in VTH2 of second transistor 108, thereby necessitating an incremental increase in second gate terminal 126-to-second source terminal 118 voltage (VGS2) to overcome the increased VTH2. Furthermore, an incremental increase in VTH2 facilitates an incremental decrease in a second drain terminal 122-to-second source terminal 118 current (not shown). Therefore, the voltage of semiconducting layer 104 has an effect on the operation of affected second transistor 108, and semiconducting layer 104 acts as a second gate. Body terminal interconnection 114 facilitates maintaining body terminal 110 and 112 of transistor 106 and 108, respectively, at the lowest potential of integrated circuit 100. Such body terminal interconnection 114 increases the interconnect complexity of integrated circuit 100. Also, such additional hard-wired interconnections 114 increases a value of the die area required for fabrication of integrated circuit 100, decrease a yield per wafer, and increase a cost of fabrication of integrated circuit 100.
In the example embodiment, trenches 210 are formed within substrate 205 to extend through second semiconducting layer 204 and at least some trenches 210 extend into first semiconducting layer 202 a distance 240 that is up to approximately 5 microns. Also, in the example embodiment, trenches 210 are positioned to surround a device, e.g., a transistor or a resistor, and define a plurality of device islands by breaking electrical connection between a body terminal of a device and those of other devices, and thus first transistor 106 may be substantially electrically isolated from second transistor 108. In one embodiment, first transistor 106 is positioned on first device island 220, second transistor 108 is positioned on second device island 230. In general, such electrical isolation facilitates each device on each device island to be back-biased at different potentials. Therefore, in the example embodiment, first device island 220 can be back-biased to a voltage of approximately 0V and second device island 230 can be back-biased to a voltage of 1V.
Forming trenches 210 to define first device island 220 and second device island 230 may facilitate substantially reducing deleterious consequences associated with the body effect. For example, threshold voltages for each device may be more stable with little variability. Also, for example, current flow through second semiconducting layer 204 associated with first device island 220 between first source terminal 116 and first drain terminal 120 may be substantially isolated to first transistor 106 and first device island 220. Similarly, current flow through second semiconducting layer 204 associated with second device island 230 between second source terminal 118 and second drain terminal 122 may be substantially isolated to second transistor 108 and second device island 230. Therefore, overall current flow through substrate 205 may be improved. Moreover, forming trenches 210 as described herein facilitates matching two similar devices in close physical proximity to each other since similar devices with similar operation may be candidates for positioning on one island together. Also, positioning similar devices on different islands facilitates each device operating in a substantially similar manner, thereby facilitating similar devices behaving in a consistent manner, also facilitating consistent operation of integrated circuit 200. Furthermore, elimination of such additional hard-wired interconnections, e.g., body terminal interconnection 114, facilitates decreasing the die area required for fabrication of integrated circuit 200, increasing a yield per wafer, and decreasing a cost of integrated circuit fabrication.
Further, in the example embodiment, first transistor 106 may be replaced by a first resistor 256 and second transistor 108 may be replaced by 258 to illustrate that resistors, as well as any other electronic device, including diodes, may be positioned on first device island 220 and second device island 230, respectively. Resistors 256 and 258 include resistive properties that are voltage and/or temperature dependent. Therefore, in the example embodiment, forming trenches 210 in substrate 205 facilitates substantially reducing varying voltage conditions associated with common second semiconductor layer 204 during dynamic operation of integrated circuit 200, therefore significantly reducing inducement of variations in the resistance of resistors 256 and 258 and, further, other resistances within integrated circuit 200.
Such reduction in resistance variations of integrated circuit 200 due to voltage variations facilitates a greater tolerance of varying environmental conditions associated with the technical or industrial application that integrated circuit 200 may be employed. Significant temperature variations will also vary the resistance of integrated circuit 200, however, in the example embodiment, integrated circuit 200 may be employed in environments with operating temperatures in excess of 175 degrees Celsius (° C.) (347 degrees Fahrenheit (° F.)), including temperatures that exceed 300° C. (572° F.), and in some cases, up to 500° C. (932° F.) for extended periods of time. Therefore, integrated circuit 200 may be embedded within high-temperature apparatus that include, without limitation, semiconductor wafers, chips, and dies. Moreover, integrated circuit 200 may be embedded larger-scale high-temperature apparatus that include, without limitation, high-temperature tools and equipment for exploration of deep oil wells.
The above-described integrated circuits and methods of fabrication may overcome disadvantages of known integrated circuits by defining an isolation barrier within a semiconducting layer between each individual electronic device positioned on the integrated circuit. The isolation barriers can be formed using known methods of patterning and etching. The isolation barriers may include trenches that may be filled with non-conductive materials that do not substantially increase costs of circuit fabrication. The isolation barriers may also includes body wells that may be filled with a doped material that does not substantially increase costs of fabrication. Each isolation barrier may surround a transistor or a resistor, thereby substantially eliminating electrical connectivity between a body terminal of a device and a body terminal of other devices. Such etching may be deep enough to extend through the semiconducting layer that houses the body of transistors and resistors, thus forming islands and isolating each device. Such isolation significantly reduces the body effect, thereby facilitating improvements in circuit performance. Also, such isolation facilitates reducing a complexity of circuit interconnectivity, thereby potentially reducing an associated die area, facilitating an increase in yield per wafer, and facilitating a reduction of cost per die. Moreover, such isolation may facilitate a reduction of voltage variations in the vicinities of each resistor in the integrated circuit, thereby further facilitating improved circuit performance with varying operating conditions and further facilitating simplifying circuit design. Furthermore, decreasing voltage variations facilitates increasing functionality of integrated circuits in apparatus that include a wider tolerance range for varying temperatures, including extended high-temperature operations. Examples of such high-temperature apparatus include high-temperature tools and equipment for exploration of deep oil wells, in some case in conditions in excess of 175 degrees Celsius (° C.) (347 degrees Fahrenheit (° F.)), including temperatures that exceed 300° C. (572° F.), and in some cases, up to 500° C. (932° F.) for extended periods of time.
Example embodiments of integrated circuits and methods for fabricating such integrated circuits are described above in detail. The integrated circuits and fabrication methods are not limited to the specific embodiments described herein, but rather, devices of integrated circuits and/or steps of the fabrication methods may be utilized independently and separately from other devices and/or steps described herein. For example, the integrated circuits and methods may also be used in combination with other electronic devices and fabrication methods, and are not limited to practice with only the integrated circuits as described herein. Rather, the example embodiment can be implemented and utilized in connection with many other electronic system and fabrication applications.
Although specific features of various embodiments of the invention may be shown in some drawings and not in others, this is for convenience only. Moreover, references to “one embodiment” in the above description are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. In accordance with the principles of the invention, any feature of a drawing may be referenced and/or claimed in combination with any feature of any other drawing.
This written description uses examples to disclose the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
