Patent Application
20100081237
Integrated circuits are typically formed into packages, with the packages then being mounted or otherwise connected to other substrates and devices. Many different packaging methods and devices exist for integrated circuits. One exemplary package includes a semiconductor that is attached to another circuit substrate, for example a printed circuit board. The printed circuit board is typically fabricated with conductive traces formed thereon in desired patterns. A layer of a material with properties of an electrical insulator commonly referred to as a solder mask is formed on the circuit substrate above the conductive traces. Such electrically insulating layers are typically patterned to provide access at designated locations to the conductive traces on the surface of the substrate. The solder mask typically prevents solder bridging on the circuit side of the assembly. The semiconductor is typically mounted to the circuit substrate by being adhered to the solder mask with a die attach adhesive. Conductive wire or other bonding is then performed to connect the circuits of the semiconductor with the circuits on the substrate.
In an exemplary packaging process, an insulative material is applied to one side of the substrate over the semiconductor and the underlying solder mask to encapsulate the semiconductor. Such a package can be formed by a transfer molding process whereby a mold having a void or mold cavity is placed against the circuit substrate and an encapsulating material or compound is caused to flow therein. Thereafter, the encapsulating material or encapsulant is allowed to cure or harden and the mold is removed.
The mold 10 is arranged with a channel 12 in a member 11 that faces the substrate 40. An elastic gasket 20 is fixed to a contact surface 14 in the channel 12. The mold 10 is arranged to form a void or cavity 18 of appropriate dimensions to surround the semiconductor device 30.
During a molding procedure, as illustrated in
The above-described degradation leads to lower yields due to leakage of the encapsulant between the mold 10 and the substrate 40. As a direct result of such failures of the elastic gasket 20 to contain the encapsulant, productivity decreases and maintenance costs increase with each subsequent repair or replacement of the elastic gasket 20.
An embodiment of an assembly including an encapsulated semiconductor device is prepared by a process comprising the steps of attaching a semiconductor device to a substrate having a mounting surface and an opposing surface, identifying a contact surface of a mold, the contact surface defining a perimeter of a cavity, generating a pattern having an opening arranged to receive the contact surface when the pattern is in registration with the contact surface, using the pattern to apply a composition to the mounting surface of the substrate, wherein the composition cures to form a compressible layer, arranging the mold and the substrate such that the contact surface compresses the layer to form a seal, filling at least a portion of the volume of the cavity with an encapsulant, permitting the encapsulant to cure and removing the mold from the substrate.
An embodiment of a method for encapsulating a semiconductor device on a substrate includes the steps of applying a composition that cures to form a compressible layer on a mounting surface of a substrate, attaching a semiconductor device to the mounting surface of the substrate, providing a mold having a contact surface that defines a cavity, arranging the mold and the substrate such that the contact surface compresses the layer to form a seal along a perimeter of the cavity, filling at least a portion of the volume of the cavity with an encapsulant, permitting the encapsulant to cure and removing the mold from the substrate.
An embodiment of a method for encapsulating semiconductor devices on a substrate includes the steps of applying a composition to a surface of the substrate, the composition forming a layer, attaching semiconductor devices on the surface of the substrate, arranging a mold forming at least a first cavity and a second cavity in proximity to the substrate such that a contact surface of the mold compresses the layer to enclose respective volumes defined by the first and second cavities and that surrounds respective first and second semiconductor devices attached to the substrate, filling at least a portion of the respective volumes of the first and second cavities with an encapsulant, curing the encapsulant; and removing the mold from the surface of the substrate.
An embodiment of an electro-optical assembly is prepared by a process comprising the steps of applying a composition to a surface of the substrate, the composition forming a layer, arranging a mold forming at least a first cavity and a second cavity in proximity to the substrate such that a contact surface of the mold compresses the layer to enclose respective volumes defined by the first and second cavities and that surrounds respective first and second semiconductor devices attached to the substrate, filling at least a portion of the respective volumes of the first and second cavities with an encapsulant, curing the encapsulant and removing the mold from the surface of the substrate.
An embodiment of a memory device is prepared by a process comprising the steps of applying a composition to a surface of the substrate, the composition curing to form a layer, arranging a mold forming at least a first cavity and a second cavity in proximity to the substrate such that a contact surface of the mold compresses the layer to enclose respective volumes defined by the first and second cavities and that surrounds respective first and second semiconductor devices attached to the substrate, filling at least a portion of the respective volumes of the first and second cavities with an encapsulant, curing the encapsulant and removing the mold from the surface of the substrate.
The figures and detailed description that follow are not exhaustive. The disclosed embodiments are illustrated and described to enable one of ordinary skill to make and use the integrated circuit assemblies and methods for encapsulating a semiconductor device. Other embodiments, features and advantages of the assemblies and methods will be or will become apparent to those skilled in the art upon examination of the following figures and detailed description. All such additional embodiments, features and advantages are within the scope of the assemblies and methods as defined in the accompanying claims.
The integrated circuit assemblies and methods for encapsulating a semiconductor device can be better understood with reference to the following figures. The elements and features within the figures are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of forming a seal for encapsulating a semiconductor device. Moreover, in the figures, like reference numerals designate corresponding parts throughout the different views.
Embodiments of integrated circuit assemblies include a layer applied to a mounting surface of a substrate. The layer is compressible and when a suitably arranged mold contacts the layer, the layer is compressed. The compressed layer forms a temporary seal at the intersection of a contact surface of the mold and the mounting surface of the substrate by filling any discontinuities in the contact surface and the mounting surface of the substrate.
The layer is added during fabrication of the substrate. The layer is formed by applying a composition on the substrate. The composition cures and forms a solid but compressible layer on the surface of the substrate. The layer remains with the substrate and the final assembly after a molding or encapsulation procedure. In this way, a separate and new seal is formed for each molding cycle.
The layer is applied by coating or otherwise applying a composition to select portions of a mounting surface of a circuit substrate. Portions of the mounting surface (including one or more circuit traces or other circuit elements) that are not selected to receive the coating are masked by arranging a stencil or silk screen in registration with a semiconductor device or other features of the circuit substrate and introducing the composition to the openings in the stencil or silk screen. The composition is any liquid, liquefiable compound, or mastic, which after application to a substrate in a thin layer is converted or cured to a compressible solid film. Heretofore, liquid compositions with dyes, commonly referred to as paint, have been applied via a silk screen process to printed circuit boards in a contrasting color to aid in the visual identification of source, circuit elements, hazards, manufacturing details, etc.
The improved integrated circuit assembly includes a compressible layer applied in one or more contiguous layers on a surface of a circuit substrate. The contiguous layers surround a semiconductor device that is to be encapsulated. The composition, which forms the layer, includes a flexible polymer as a binding material, such as, an acrylic resin, polyurethane, or polyester. In addition, the composition may contain one or more pigments in a desired ratio to distinguish the resulting compressible layer or layers from other “information only” labels applied to the circuit substrate.
The one or more contiguous layers may vary in thickness as well as compound characteristics in accordance with one or both of mold design and molding process parameters. Mold processing parameters include, temperature, pressure, time, encapsulant, among others. For example, during mold development, the thickness of the layer may be increased incrementally using a fixed step, or steps of varying thickness and compound characteristics for that matter, until the total thickness of the layer results in a successful seal between the circuit substrate and the mold for a particular molding process. By way of further example, the thickness of the compressible layer may be controlled by applying the composition with a stencil or silk screen with a known thickness to form a base layer. Once the base layer has cured to form a compressible solid film, subsequent layers may be applied on top of the base layer. Statistical analysis can be applied to identify a probability of reaching a desired yield for a particular thickness of the layer(s) for a given molding process.
The illustrated embodiments include single and double cavity molds for simplicity of illustration and clarity of description. The improved integrated circuit assemblies and methods for encapsulating a semiconductor device are not so limited. For example, a multiple cavity mold may be arranged with an array of cavities to encapsulate correspondingly arranged semiconductors attached to a circuit substrate. Furthermore, each individual cavity of a multiple cavity mold may be arranged to encapsulate any number of semiconductor devices as may be desired. The arrangements may include unique arrangements among the various members of a mold array or patterns of repeating arrangements as may be desired.
Reference is now directed to
As shown in
The mold 100 includes a contact surface 120 arranged on a lower most surface of the member 111. The contact surface 120 defines a perimeter of a base area that is arranged to surround the semiconductor 30. The contact surface 120 is arranged to contact a compressible layer 150a. The compressible layer 150a is formed by applying a composition in a liquid, liquefiable, or mastic form, which, after application to the substrate, is converted or cured to a compressible solid film. The composition includes a flexible polymer as a binding material. Flexible polymers include an acrylic resin, polyurethane, or polyester. The member 111 forms a cavity 118 that is defined by a left-side surface 113, a right-side surface 117, a rear surface 115 and an upper surface 119. A front surface (not shown in the cross-sectional view) further defines the cavity 118. The cavity 118 is arranged to surround and enclose a volume that receives a semiconductor device 30 attached to the mounting surface 43 of the substrate 40.
During a molding process, as illustrated in
For clarity of illustration and description, equipment and tooling responsible for the upward and downward external forces as shown in
It should be understood that while the illustrated embodiment shows a single-cavity mold 100 used in a process of encapsulating a semiconductor 30, such a single-cavity mold 100 is not so limited. For example, a single-cavity mold 100 can be arranged to encapsulate additional semiconductor devices. Furthermore, the single cavity mold can be arranged in configurations that enclose three-dimensional volumes that produce alternative final encapsulation surfaces.
In addition, it should be understood that while the illustrated embodiment shows a compressible layer 150a and a compressed layer 150b that extends beyond the contact surface 120 of a corresponding mold 100, the improved seal formed by the compressed layer 150b between the contact surface 120 and the substrate 40 is not so limited. That is, at any location around the perimeter of a cavity, the compressed layer 150b (as well as the compressible layer 150a) may be narrower, the same or wider than the contact surface 120. Furthermore, errors in registration or alignment between the compressed layer 150b and the contact surface 120 are permissible as long as a seal is formed by the contiguous contact between some portion of the compressed layer 150b and the contact surface 120 over the perimeter of a respective cavity.
Moreover, it should also be understood that while the illustrated embodiment shows a single compressible layer 150a and a single compressed layer 150b, the present seal and methods for encapsulating a semiconductor device are not so limited. For example, as described above, a compressible seal can be formed by one or more additional applications of the composition upon a cured base layer. The base layer and any additional layers may be applied using the same or different thicknesses of the composition. Furthermore, the base layer and any additional layers may be applied using different composition. That is, the base layer and any additional layers can be applied via different composition in any one of a liquid, liquefiable, or mastic form which results a unique sandwich layer consists of different flexible polymer.
As shown in
The mold 300 (
For clarity of illustration and description, one or more ports and one or more devices for introducing the encapsulant and or controlling conditions in the first and second cavities are not shown in
It should be understood that while the illustrated embodiment shows a multiple-cavity mold 300 used in a process for forming two encapsulated assemblies, such a multiple-cavity mold is not so limited. For example, a multiple-cavity mold can be arranged to encapsulate additional devices or assemblies arranged on a substrate as may be desired. By way of example, a multiple-cavity mold can be arranged to encapsulate devices arranged in an M×N array. Where M is an integer representing the number of rows in the array and N is an integer representing the number of columns in the array of devices or assemblies.
When the pattern 400 is in registration or in alignment with the substrate of the EOSA 450, the first mask 410 prevents the composition from contacting the substrate in an area 452 (
In the illustrated embodiment, the layer 480 is shown defining rectangular bases or seals with a common leg that separates the first area 460 from the second area 470. In alternative embodiments, each area to be encapsulated is provided with a separate and distinct layer that surrounds the respective area. These separate and distinct layers can be arranged in circles or other shapes having a continuous perimeter, as well as shapes having three legs (i.e., a triangle) or more than four legs as may be desired to encapsulate devices or assemblies.
During a molding process performed during the manufacture of the memory module 500, the layer 580 is compressed by one or more molds configured with respective contact surfaces and recesses to form cavities. The one or more molds are arranged in registration with one or more features of the substrate 510. Features of the substrate 510 suitable for alignment or registration with a mold include but are not limited to an edge of the substrate 510, a hole through the substrate 510, a feature of a device attached to the substrate, a mark or other indicator on a surface of the substrate 510. The one or more molds compress the layer 580 to seal the one or more molds over the semiconductor dies. Once the seals are formed, an encapsulant, such as a thermoset plastic is introduced in a sufficient amount to fill a desired portion of each of the cavities. Thereafter, the environment surrounding the one or more molds and the substrate 510 is controlled to permit the encapsulant to solidify and the one or more molds are removed from the substrate 510. As a result, the semiconductor dies are arranged and encapsulated in an array 530.
In the illustrated embodiment, the memory module 500 includes a rectangular array consisting of two rows of twelve encapsulated cavities with the encapsulant molded into similar shapes. The memory module 500 is not so limited. For example, different arrangements of the semiconductor dies and or other elements to be encapsulated as well as different mold configurations are possible. It should be understood that the number of encapsulated cavities as well as the number and arrangement of semiconductor devices, dies and circuit elements encapsulated therein may vary as may be desired.
Exemplary steps for manufacturing an integrated circuit assembly are illustrated in
The application of the compressible layer on the mounting surface of the substrate eliminates yield loss due to gasket failures, reduces downtime and the costs associated with procuring and installing replacement gaskets. Furthermore, the application of the compressible layer increases yield densities, while still permitting adjacent semiconductor devices to be separately encapsulated, as adjacent semiconductor devices can be arranged closer to each other than previously possible when the devices were encapsulated using a mold that compressed a gasket under a contact surface.
While various embodiments of the integrated circuit assemblies and methods for encapsulating a semiconductor device have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible that are within the scope of this disclosure. Accordingly, the described assemblies and methods are not to be restricted or otherwise limited except in light of the attached claims and their equivalents.
