Patent Application
20080237738
In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of embodiments of the invention. In the following description, various embodiments of the invention are described with reference to the following drawings, in which:
Embodiments of the invention relate generally to an integrated circuit, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module.
In a conventional charge trapping memory cell arrangement, so called buried bit lines may be used. The buried bit lines are formed by implantation of the source/drain regions of the respective charge trapping memory cells of the charge trapping memory cell arrangement.
In this case, the resistance of the source/drain region and the resistance of the respective buried bit line are coupled. If the charge trapping memory cell arrangement is scaled down, shallow junctions may become necessary which may result in a high electrical resistance of the bit lines.
In a conventional charge trapping memory cell arrangement such as, e.g., in an NROM (Nitrided Read Only Memory) memory cell arrangement, e.g., in a Twin Flash memory cell arrangement using a 170 nm process technology, so called buried bit lines are used. The conventional buried bit lines are formed by implantation of the source/drain regions of the charge trapping memory cells.
In this case, the resistance of the source/drain regions and the buried bit line resistance of the respectively coupled buried bit line are coupled. If the charge trapping memory cells are scaled down, shallow junctions may become necessary which may result in a too high bit line resistance.
The memory cell arrangement 100 has a carrier 106, e.g., a substrate 106.
The first charge trapping memory cell 102 includes an active region 108. The active region 108 may be rendered electrically conductive (in other words form a conductive channel) in response to an appropriate voltage application to a gate region and to a first source/drain region and a second source/drain region, which will be described in more detail below. Furthermore, the first charge trapping memory cell 102 includes a gate stack 110 arranged on or above the active region 108. The gate stack 110 includes a gate insulating layer 112, e.g., made of an oxide, e.g., made of silicon oxide (SiO2), being arranged on or above the active region 108. Furthermore, the gate stack 110 includes a charge trapping region being arranged on or above the gate insulating layer 112. In case that the first charge trapping memory cell 102 is an Oxide-Nitride-Oxide (ONO) type charge trapping memory cell, the charge trapping region includes a charge trapping layer 114, e.g., made of a nitride, e.g., made of silicon nitride, being arranged on or above the gate insulating layer 112 and a top oxide layer 116, e.g., made of silicon oxide (SiO2) or aluminum oxide (Al2O3) being arranged on or above the charge trapping layer 114. The gate stack 110 further includes a gate region 118, e.g., made of poly-silicon or any other suitable gate material. The gate region 118 may include one or a plurality of layers, e.g., a layer stack of two or more layers. In one embodiment, the gate region 118 includes two layers, e.g., a layer stack comprising a poly-silicon layer and a tungsten salicide layer on or above the poly-silicon layer. In another embodiment, the layer stack comprises a poly-silicon layer and a tungsten layer on or above the poly-silicon layer. Furthermore, a further nitride layer 120, e.g., made of silicon nitride, is provided on or above the gate region 118.
The second charge trapping memory cell 104 includes an active region 122. The active region 122 may be rendered electrically conductive (in other words form a conductive channel) in response to an appropriate voltage application to a gate region and to a first source/drain region and a second source/drain region, which will be described in more detail below. Furthermore, the second charge trapping memory cell 104 includes a gate stack 124 arranged on or above the active region 122. The gate stack 124 includes a gate insulating layer 126, e.g., made of an oxide, e.g., made of silicon oxide (SiO2), being arranged on or above the active region 122. Furthermore, the gate stack 124 includes a charge trapping region being arranged on or above the gate insulating layer 126. In case that the second charge trapping memory cell 104 is an Oxide-Nitride-Oxide (ONO) type charge trapping memory cell, the charge trapping region includes a charge trapping layer 128, e.g., made of a nitride, e.g., made of silicon nitride, being arranged on or above the gate insulating layer 126 and a top oxide layer 130, e.g., made of silicon oxide (SiO2) or aluminum oxide (Al2O3) being arranged on or above the charge trapping layer 128. The gate stack 124 further includes a gate region 132, e.g., made of poly-silicon or any other suitable gate material. The gate region 132 may include one or a plurality of layers, e.g., a layer stack of two or more layers. In one embodiment, the gate region 132 includes two layers, e.g., a layer stack comprising a poly-silicon layer and a tungsten salicide layer on or above the poly-silicon layer. In another embodiment, the layer stack comprises a poly-silicon layer and a tungsten layer on or above the poly-silicon layer. Furthermore, a further nitride layer 134, e.g., made of silicon nitride, is provided on or above the gate region 132.
The first charge trapping memory cell 102 and the second charge trapping memory cell 104 each comprise a first source/drain region and a second source/drain region. Conventionally, the source/drain regions of the respectively adjacent charge trapping memory cells are common source/drain regions. Furthermore, as shown in
It should be mentioned that in one embodiment of the invention, the described cells as well as the described cell arrangements may be monolithically integrated in one integrated circuit or in a plurality of integrated circuits.
In one embodiment of the invention, the cell 200 is a transistor-type cell. The cell 200 may include a first source/drain region 202 and a second source/drain region 204.
It should be mentioned that in different embodiments of the invention, the cells could be transistor-type (e.g., field effect transistor-type) logic cells and/or transistor-type (e.g., field effect transistor-type) memory cells.
Furthermore, the cell 200 may include an active region 206 in a carrier 208, e.g., a substrate 208. In one embodiment of the invention, the substrate 208 is made of semiconductor material, although in another embodiment of the invention, other suitable materials can also be used, e.g., polymers. In an exemplary embodiment of the invention, the substrate 208 is made of silicon (doped or undoped), in an alternative embodiment of the invention, the substrate 208 is a silicon on insulator (SOI) wafer. As an alternative, any other suitable semiconductor materials can be used for the substrate 208, for example, semiconductor compound material such as gallium arsenide (GaAs), indium phosphide (InP), but also any suitable ternary semiconductor compound material or quaternary semiconductor compound material such as, e.g., indium gallium arsenide (InGaAs).
In one embodiment of the invention, the cell 200 further includes a gate insulating region 210, e.g., a gate insulating layer 210, disposed above the active region 206. Furthermore, a gate region 212, e.g., a gate layer 212, is disposed above the gate insulating region 210.
The active region 206 may be rendered electrically conductive (in other words form a conductive channel) in response to an appropriate voltage application to the gate region 212 and to the first source/drain region 202 and the second source/drain region 204.
As shown in
In one embodiment of the invention, the first source/drain region 202 and the second source/drain region 204 are n-doped regions (in case that the cell 200 is an n-type transistor) or p-doped regions (in case that the cell 200 is a p-type transistor).
In one embodiment of the invention, the at least one metal structure 214 is made of a material that acts as a diffusion barrier with regard to the material of the carrier 208 and/or of a material that acts as a diffusion barrier with regard to the material of the second source/drain region 204, in general with regard to the material of the source drain/region that is disposed above the at least one metal structure 214.
In other words, in one embodiment of the invention, the at least one metal structure 214 is made of a material that acts as a diffusion barrier with regard to the material of the carrier 208.
In case that the material of the at least one metal structure 214 does not act as a diffusion barrier with regard to the material of the source/drain region that is disposed above the at least one metal structure 214, an additional diffusion barrier layer is provided between the at least one metal structure 214 and the respective source/drain region.
In case that the material of the at least one metal structure 214 does act as a diffusion barrier with regard to the material of the source/drain region that is disposed above the at least one metal structure 214, no additional diffusion barrier layer is necessary and the respective source/drain region may be formed directly on or above the at least one metal structure 214.
In another embodiment of the invention, the at least one metal structure 214 is made of a material that acts as a diffusion barrier only with regard to the material of the source/drain region (e.g., the second source/drain region 204) that is disposed above the at least one metal structure 214, but not with regard to the material of the carrier 208. In this case, an additional diffusion barrier layer is provided between the material of the carrier 208 and the at least one metal structure 214, but no diffusion barrier layer is necessary between the respective source/drain region (e.g., the second source/drain region 204) that is disposed above the at least one metal structure 214 and the at least one metal structure 214, as will be described in more detail below.
In one embodiment of the invention, the at least one metal structure 214 illustratively acts as a bit line.
In one embodiment of the invention, the at least one metal structure 214 may be electrically coupled to the respective source/drain region.
In an embodiment, in which an additional diffusion barrier is provided between the at least one metal structure 214 and the respective source/drain region, the material of the additional diffusion barrier may be electrically conductive (e.g., the additional diffusion barrier may be made of tantalum nitride (TaN), thereby providing an electrical coupling between the source/drain region and the at least one metal structure 214.
In one embodiment of the invention, the carrier 208 is made of silicon. In this case, the at least one metal structure 214 is made of a material that acts as a diffusion barrier with regard to silicon. Examples of such a material are titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN), a salicide such as, e.g., tungsten salicide (WSi), cobalt salicide (CoSi), titanium salicide (TiSi), tungsten nitride (WN), hafnium nitride (HfN), zirconium nitride (ZrN), tantalum nitride (TaN), etc.
In an embodiment of the invention, in which the at least one metal structure 214 is made of a material that does not act as a diffusion barrier with regard to the material of the carrier 208 (e.g., silicon), an additional diffusion barrier layer (in the case that silicon is used for the carrier, e.g., made of silicon oxide) may be provided between the carrier 208 and the at least one metal structure 214.
The memory cell 600 is similar to the cell 200 shown in
In one embodiment of the invention, the memory cell 600 is a volatile memory cell.
In one embodiment of the invention, the memory cell 600 is a non-volatile memory cell.
In the context of this description, a “volatile memory cell” may be understood as a memory cell storing data, the data being refreshed during a power supply voltage of the memory system being active, in other words, in a state of the memory system, in which it is provided with power supply voltage. In contrast thereto, a “non-volatile memory cell” may be understood as a memory cell storing data, wherein the stored data is/are not refreshed during the power supply voltage of the memory system being active.
However, a “non-volatile memory cell” in the context of this description includes a memory cell, the stored data of which may be refreshed after an interruption of the external power supply. As an example, the stored data may be refreshed during a boot process of the memory system after the memory system had been switched off or had been transferred to an energy deactivation mode for saving energy, in which mode at least some or most of the memory system components are deactivated. Furthermore, the stored data may be refreshed on a regular timely basis, but not, as with a “volatile memory cell” every few picoseconds or nanoseconds or milliseconds, but rather in a range of hours, days, weeks or months.
In one embodiment of the invention, the memory cell 600 is a charge storage memory cell, e.g., a floating gate memory cell or a charge trapping memory cell.
In the embodiment, in which the memory cell 600 is a floating gate memory cell, the gate insulating region 210 may be a tunnel oxide layer and the charge storage region 602 may include a floating gate region (which may be formed from electrically conductive material such as, e.g., poly-silicon (doped or undoped)) formed on or above the gate insulating region 210 and a gate oxide layer (which may, e.g., be made of silicon oxide or aluminum oxide) formed on or above the floating gate region.
In the embodiment, in which the memory cell 600 is a charge trapping memory cell, a charge trapping layer structure may be provided. The charge trapping layer structure may include a dielectric layer stack including at least two dielectric layers being formed above one another (one dielectric layer of the two dielectric layers may be formed by the gate insulating layer 210 and the other dielectric layer of the two dielectric layers may be included in the charge storage region 602), wherein charge carriers can be trapped in at least one of the at least two dielectric layers. By way of example, the charge trapping layer structure includes a charge trapping layer, which may include or consist of one or more materials being selected from a group of materials that consists of: aluminium oxide (Al2O3), yttrium oxide (Y2O3), hafnium oxide (HfO2), lanthanum oxide (LaO2), zirconium oxide (ZrO2), amorphous silicon (a-Si), tantalum oxide (Ta2O5), titanium oxide (TiO2), and/or an aluminate. An example for an aluminate is an alloy of the components aluminium, zirconium and oxygen (AlZrO). In one embodiment of the invention, the charge trapping layer structure includes a dielectric layer stack including three dielectric layers being formed above one another, e.g., a first oxide layer (e.g., silicon oxide) (e.g., formed by the gate insulating region 210), a nitride layer as charge trapping layer (e.g., silicon nitride) on the first oxide layer, and a second oxide layer (e.g., silicon oxide or aluminium oxide) on the nitride layer. This type of dielectric layer stack is also referred to as ONO layer stack. In an alternative embodiment of the invention, the charge trapping layer structure includes two, four or even more dielectric layers being formed above one another.
The memory cell structures described with reference to
At 702, an active region is formed, e.g., in a carrier such as, e.g., in a substrate 208 (e.g., made of a semiconductor material such as, e.g., silicon).
At 704, a gate insulating region (e.g., a gate insulating layer, e.g., made of silicon oxide) is formed (e.g., deposited using, e.g., a chemical vapour deposition process (CVD) or a physical vapour deposition process (PVD)) on or above the active region.
At 706, a gate region (e.g., including forming one or a plurality of layers including electrically conductive material such as, e.g., poly-silicon) is formed (e.g., deposited using, e.g., a chemical vapour deposition process (CVD) or a physical vapour deposition process (PVD)) on or above the gate insulating region.
At 708, at least one trench is formed (e.g., etched, e.g., anisotropically etched, e.g., using wet etching or dry etching, e.g., using reactive ion etching (RIE)) next to the active region (in one embodiment of the invention respectively between two gate stacks to be formed in the area, in which the source/drain regions should be formed). In one embodiment of the invention, the trench extends into the carrier 208 deeper than the depth of the source/drain regions to be formed. In one embodiment of the invention, the trench extends up to a depth into the carrier 208 (considered from the upper surface of the carrier 208) in the range of about 20 nm to about 150 nm, e.g., in the range of about 40 nm to about 100 nm, e.g., about 50 nm. In one particular embodiment of the invention, the forming of the at least one trench next to the active region includes forming a first trench on one side next to the active region and forming a second trench on the opposite side of the active region next to the active region. In other words, in accordance with this particular embodiment of the invention, two trenches are formed next to each cell, namely a first trench provided for the first source/drain region to be manufactured on the one side of the cell and a second trench provided for the second source/drain region to be manufactured on the other side of the cell, thereby, e.g., providing a transistor-type cell.
At 710, at least one metal structure is formed in the at least one trench (e.g., deposited using, e.g., a chemical vapour deposition process (CVD) or a physical vapour deposition process (PVD)) on or above the exposed carrier 208. In one embodiment of the invention, the at least one metal structure is deposited having a metal structure thickness in the range of about 5 nm to about 100 nm, e.g., in the range of about 20 nm to about 50 nm, e.g., about 30 nm. In one particular embodiment of the invention, the forming of the at least one metal structure in the trench includes forming a first metal structure in the first trench and forming a second metal structure in the second trench.
Then, at 712, a source/drain region is formed (e.g., deposited using, e.g., a chemical vapour deposition process (CVD) or a physical vapour deposition process (PVD)) on or above the at least one metal structure. In one particular embodiment of the invention, the forming the source/drain region above the at least one metal structure includes forming a first source/drain region on or above the first metal structure and forming a second source/drain region on or above the second metal structure.
In one embodiment of the invention, the cell arrangement 800 includes a first cell 802 and a second cell 804. The first cell 802 and the second cell 804 may be any of the cells described above with regard to the various embodiments.
The cells 802, 804 are manufactured in or above a carrier 806 as the cells described above.
The first cell 802 includes a first source/drain region 808 and a second source/drain region 810 and an active region 812 in the carrier 806 between the first source/drain region 808 and the second source/drain region 810. The active region 812 may be rendered electrically conductive (in other words form a conductive channel) in response to an appropriate voltage application to a gate region and to the first source/drain region 808 and the second source/drain region 810, which will be described in more detail below. Furthermore, the first cell 802 includes a gate stack 814 arranged on or above the active region 812. The gate stack 814 includes a gate insulating layer 816, e.g., made of an oxide, e.g., made of silicon oxide (SiO2), being arranged on or above the active region 812. Furthermore, the gate stack 814 includes a gate region 818, e.g., made of poly-silicon or any other suitable gate material. The gate region 818 may include one or a plurality of layers, e.g., a layer stack of two or more layers. In one embodiment, the gate region 818 includes two layers, e.g., a layer stack comprising a poly-silicon layer and a tungsten salicide layer on or above the poly-silicon layer. In another embodiment, the layer stack comprises a poly-silicon layer and a tungsten layer on or above the poly-silicon layer.
The second cell 804 includes a first source/drain region 810 (which in one particular embodiment of the invention is a common (shared) source/drain region with the second source/drain region 810 of the first cell 802), a second source/drain region 820 and an active region 822 in the carrier 806 between the first source/drain region 810 and the second source/drain region 820. The active region 822 may be rendered electrically conductive (in other words form a conductive channel) in response to an appropriate voltage application to a gate region and to the first source/drain region 810 and the second source/drain region 820, which will be described in more detail below. Furthermore, the second cell 804 includes a gate stack 824 arranged on or above the active region 822. The gate stack 824 includes a gate insulating layer 826, e.g., made of an oxide, e.g., made of silicon oxide (SiO2), being arranged on or above the active region 822. Furthermore, the gate stack 824 includes a gate region 828, e.g., made of poly-silicon or any other suitable gate material. The gate region 828 may include one or a plurality of layers, e.g., a layer stack of two or more layers. In one embodiment, the gate region 828 includes two layers, e.g., a layer stack comprising a poly-silicon layer and a tungsten salicide layer on or above the poly-silicon layer. In another embodiment, the layer stack comprises a poly-silicon layer and a tungsten layer on or above the poly-silicon layer.
In one embodiment of the invention, at least one metal structure 830 is provided below the second source/drain region 810 of the first cell 802 and the first source/drain region 810 of the second cell 804 (in one embodiment of the invention below the common source/drain region shared by the first cell 802 and the second cell 804).
All embodiments described with reference to the cells also refer analogously to the various embodiments of the cell arrangement.
At 902, a partial first cell is formed, wherein the partial first cell includes an active region, a gate insulating region disposed above the active region, and a gate region disposed above the gate insulating region.
At 904, a partial second cell is formed, wherein the partial second cell includes an active region, a gate insulating region disposed above the active region, and a gate region disposed above the gate insulating region.
At 906, at least one trench (e.g., etched, e.g., anisotropically etched, e.g., using wet etching or dry etching) is formed between the active region of the partial first cell and the active region of the partial second cell (in one embodiment of the invention respectively between the two gate stacks to be formed in the area, in which the source/drain regions should be formed). In one embodiment of the invention, the trench extends into the carrier 806 deeper than the depth of the source/drain regions to be formed. In one embodiment of the invention, the trench extends up to a depth into the carrier 806 (considered from the upper surface of the carrier 806) in the range of about 20 nm to about 150 nm, e.g., in the range of about 40 nm to about 100 nm, e.g., about 50 mm.
At 908, at least one metal structure is formed in the trench (e.g., deposited using, e.g., a chemical vapour deposition process (CVD) or a physical vapour deposition process (PVD)) on or above the exposed carrier 806. In one embodiment of the invention, the at least one metal structure is deposited having a metal structure thickness in the range of about 5 nm to about 100 nm, e.g., in the range of about 20 nm to about 50 nm, e.g., about 30 nm.
At 910, a source/drain region of the partial first cell and the partial second cell is formed (e.g., deposited using, e.g., a chemical vapour deposition process (CVD) or a physical vapour deposition process (PVD)) on or above the at least one metal structure.
The memory cell arrangement 1000 includes a carrier 1002, e.g., a substrate 1002 such as, e.g., a substrate 1002 made of a material as described above (e.g., a silicon substrate).
As illustrated in
In one embodiment of the invention, to form the memory cell arrangement 1000 shown in
In an alternative embodiment of the invention, in which the memory cells 1004, 1006 are floating gate memory cells 1004, 1006, the also in this case formed first oxide layer 1008 (also referred to as tunnel dielectric in this case) may be formed having a thickness in the range of about 3 nm to about 15 nm.
Then, in the embodiment, in which the memory cells 1004, 1006 are charge trapping memory cells 1004, 1006, a charge trapping layer 1010 (e.g., made of a material as described above) is formed (e.g., deposited using a CVD process or a PVD process) on or above first oxide layer 1008. Next, a second oxide layer 1012 (e.g., made of silicon oxide or aluminum oxide) is formed (e.g., deposited using a CVD process or a PVD process) on or above the charge trapping layer 1010. The first oxide layer 1008, the charge trapping layer 1010 and the second oxide layer 1012 form the so called ONO layer stack.
In the alternative embodiment of the invention, in which the memory cells 1004, 1006 are floating gate memory cells 1004, 1006, a floating gate layer (e.g., made of poly-silicon) is formed (e.g., deposited using a CVD process or a PVD process) on or above the first oxide layer 1008 and a second oxide layer (also referred to as gate dielectric) is formed (e.g., deposited using a CVD process or a PVD process) on or above the floating gate layer.
Then, in both embodiments, a gate layer 1014 (e.g., made of electrically conductive material such as, e.g., poly-silicon) is formed (e.g., deposited using a CVD process or a PVD process) on or above the second oxide layer 1012. Next, the thus formed layer stack is patterned (e.g., using anisotropic etching, e.g., anisotropic wet etching or anisotropic dry etching, e.g., using reactive ion etching (RIE)), thereby forming first trenches 1016 extending through the entire layer stack into the carrier 1002, wherein the first trenches 1016 extend into the carrier 1002 (considered from the upper surface of the carrier 1002) by a depth in the range of about 10 nm to about 100 mm.
Next, a nitride layer 1018 (e.g., made of silicon nitride) is formed on the resulting structure, i.e. on or above the upper surface of the remaining second oxide layer 1012, on or above the sidewalls of the first trenches 1016 and on or above the exposed regions of the carrier 1002.
Then, nitride spacers 1020 are formed by anisotropic etching (e.g., anisotropic wet etching or anisotropic dry etching, e.g., reactive ion etching (RIE)) the nitride layer 1018, thereby again exposing some regions of the carrier 1002 at the bottom of the first trenches 1016.
As shown in
Then, the exposed material (e.g., silicon) of the carrier 1002 within the second trenches 1102 is oxidized (to, e.g., silicon oxide) e.g., by means of rapid thermal processing (RTP), thereby forming a U-shaped oxide layer 1104 (e.g., silixon oxide layer) on sidewalls of the lower portion (below the nitride spacers 1020) of the second trenches 1102 and the bottom of the second trenches 1102.
In an embodiment of the invention, an additional channel stop region is provided around the U-shaped oxide layer 1104 in the substrate 1002 in order to prevent a parasitic device with a parasitic channel region along the U-shaped oxide layer 1104. The additional channel stop region may be formed by means of an out-diffusion of doping atoms or by means of a suitable implantation process (e.g., with a concentration of doping atoms in the range of about 1018 cm−3 to about 5*1018 cm−3). In an embodiment of the invention, in which the devices to be formed are n-channel field effect transistors, boron ions (B or BF2) may be used as doping atoms for forming the channel stop region. In an embodiment of the invention, in which the devices to be formed are p-channel field effect transistors, arsenic ions (As) or phosphorous ions (P) may be used as doping atoms for forming the channel stop region.
As shown in
In one embodiment of the invention, a metal is used for the metal structures 1202 that is a carrier diffusion barrier metal (e.g., a silicon diffusion barrier metal), in other words a metal that acts as a diffusion barrier with regard to the carrier material (e.g., a metal that acts as a diffusion barrier with regard to silicon). In one embodiment of the invention, the metal is a metal selected from a group of metals consisting of titanium nitride (TiN), titanium aluminum nitride (TiAlN), tantalum silicon nitride (TaSiN). In another embodiment of the invention, the metal is a salicide such as, e.g., tungsten salicide (WSi), cobalt salicide (CoSi) or titanium salicide (TiSi), tungsten nitride (WN), hafnium nitride (HfN), zirconium nitride (ZrN), tantalum nitride (TaN). In these embodiments, in which the metal itself is a carrier diffusion barrier metal (e.g., a silicon diffusion barrier metal), the U-shaped oxide layer 1104 (e.g., silixon oxide layer) on sidewalls of the lower portion (below the nitride spacers 1020) of the second trenches 1102 and the bottom of the second trenches 1102 might be omitted.
In an embodiment of the invention, in which a metal (e.g., tungsten (W)) is used for the metal structures 1202, which is not a diffusion barrier metal with regard to the material which is used for forming the source/drain regions (in one embodiment of the invention amorphous silicon for the material used for forming the source/drain regions) (e.g., not a silicon diffusion barrier metal), an additional diffusion barrier layer (e.g., made of tantalum nitride (TaN) is deposited (and recessed) on or above the upper surface of the metal structures 1202 (not shown).
In one embodiment of the invention, the metal structures 1202 have a thickness in the range of about 10 nm to about 50 nm.
As shown in
Next, as shown in
Furthermore, diffusion source material 1302 (e.g., a material, in which the source/drain regions may be formed later on) is deposited in the second trenches 1102 on or above the upper surface of the metal structures 1202 (or, if the metal structures 1202 are not a diffusion barrier with regard to the diffusion source material, on or above the upper surface of the additionally provided diffusion barrier layer), e.g., by means of a CVD process or a PVD process.
In one embodiment of the invention, the diffusion source material 1302 is formed having a thickness in the range of about 20 nm to about 50 nm.
In one embodiment of the invention, the diffusion source material 1302 is electrically conductive material.
In one embodiment of the invention, the diffusion source material 1302 is a material selected from a group of materials consisting of amorphous silicon, poly-silicon, carbon, germanium (e.g., pure germanium), salicide (e.g., cobalt salicide (CoSi)).
As shown in
Then, spacers 1404 are formed on the exposed sidewalls of the second trenches 1102 formed on or above the exposed upper surface of the diffusion source material 1302. The spacers 1404 may be made of an oxide such as, e.g., silicon oxide. In one embodiment of the invention, the spacers 1404 may be formed by depositing (e.g., by means of a CVD process or by means of a PVD process) the spacer material (e.g., silicon oxide) and then carrying out a spacer etching (e.g., an anisotropic etching, e.g., using a reactive ion etching (RIE)).
Then, a further implantation of the still exposed regions of the upper surface of the diffusion source material 1302 is performed, thereby forming source/drain regions 1406 (together with the pocket implants 1402) of the charge trapping memory cells 1004, 1006 (or, in an alternative embodiment of the invention, of floating gate memory cells 1004, 1006).
As shown in
Then, the conventional processes for completing the memory cell arrangement are executed, e.g., Back-End-Of-Line processes (BEOL) such as for wiring, packaging, etc.
In one embodiment of the invention, illustratively, a trench filled with metal under and connected with the source/drain area of the cell is formed.
In one embodiment of the invention, illustratively, a bit line is introduced in a trench. The trench may be filled with a metal and may be connected to the source/drain regions in the following way:
Forming a silicon diffusion barrier over the trench filled with metal; or the metal itself is a silicon diffusion barrier (like for example titanium nitride (TiN)).
Depositing amorphous poly-silicon over the diffusion barrier.
Implanting the source/drain region.
By doing this, the bit line resistance is decoupled from the optimum conditions for the source/drain regions (also referred to as source/drain junctions) to make a small cell. Because a metal is used in the trench, the bit line resistance is low. Secondaries formed by hot electrons will be captured by the metal in the trench, which will suppress the disturb of the next cell.
In one embodiment of the invention, illustratively, a trench is formed and partially filled with metal. Then a connection is made with a diffusion barrier to source/drain junctions from the charge trapping memory cell (or from the floating gate memory cell).
As shown in
As shown in
While embodiments of the invention have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. The scope of the invention is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.
