Patent Application
20060072296
Integrated circuits (IC) may generate heat during use. In particular, discrete devices, such as a heterojunction bipolar transistor (HBT), on integrated circuits may generate heat during use. It may be desirable to dissipate heat generated from the discrete devices during use so as to prolong the life of the devices and so as to improve the working characteristics of the circuit.
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Subcollector layer 32 may include two collector contacts 42 and base layer 36 may include two base contacts 44, also referred to as base fingers 44. A collector connection trench or via 46 may be connected to one of collector contacts 42. A base connection trench or via 48 may be connected to one of base contacts 44. An emitter connection trench or via 50 may be connected to a top surface of emitter contact layer 40. Each of contacts 42 and 44 and emitter contact layer 40 may be manufactured of electrically conductive material such as gold, aluminum, copper or the like. Similarly, each of connection vias 46, 48, 50 may be manufactured of electrically conductive material such as gold, aluminum, copper or the like. In the embodiment shown, each of connection vias 46, 48 and 50 extend upwardly from their corresponding contact and then perpendicularly into the plane of the drawing. Thereafter, connection vias 46, 48 and 50 are connected to other components of circuit 10, as will be understood in the art. In other embodiments, other paths for the vias may be utilized.
Each of devices 14 may be separated by an isolation region 52 positioned between the device substrate 28 and subcollector layer 32 of adjacent devices. An insulative layer, such as a dielectric layer 58 may extend over portions of isolation region 52 as shown. An electrically conductive layer, such as a metal layer 60, may extend over one of collector contacts 42, as shown.
Mesa 30 may define a side surface 64 that may extend around perimeter 24 of mesa 30 of transistor 14, encompassing the components and layers described above. Mesa 30 may further define a top surface 66 positioned opposite mesa 30 from device substrate 28.
Heat dissipation structure 12 may surround mesa 30 on top surface 66 and on two sides 68 of side surface 64. Heat dissipation structure 12 may include a first thermally conductive layer 70, a second thermally conductive layer 72, a third thermally conductive layer 74, a fourth thermally conductive layer 76, a fifth thermally conductive layer 78 and a sixth thermally conductive layer 80. Thermally conductive layer 78 may be referred to as a metal bump and may have a height or thickness 79, for example, in a range of 35 to over 100 micrometers. Thermally conductive layer 80 may be referred to as a solder cap and may be thermally connected to printed circuit board 22.
Thermally conductive layers 70, 72, 76, 78 and 80 may be manufactured of a metal, such as gold, aluminum or copper, such that these layers may also be electrically conductive. In particular, thermally conductive layer 74 may be manufactured of a thermally conductive but electrically non-conductive or insulative material, such as galium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC) and silicon (Si). Layers 70, 72, and 76 may be manufactured of gold. Layer 78 may be copper and layer 80 may be tin. Accordingly, heat dissipation structure 12 of the present invention may provide a fully metallized sidewall structure while still maintaining the electrical continuity of the circuit, i.e., heat dissipation structure 12 may not be in electrical contact with discrete device 14 but may provide a heat dissipation path. In one embodiment, each of layers 70, 72, 74, 76, 78 and 80, and circuit substrate 22, may be sequentially positioned, such as by depositing each of the layers on the preceding layer. For example, layer 70 may be deposited. Layer 72 may then be deposited on layer 70. Layer 74 may then be deposited on layer 72, and the like, such that circuit substrate layer 22 is lastly positioned on layer 80. In another embodiment, layers 70 through 78 may be deposited. Layer 80 may then be deposited on an underside of circuit substrate 22 whereafter layers 80 and 22 are then positioned on layer 78. Such an embodiment may be referred to as a solder printing method.
The number of layers utilized and the position of each of layers 70, 72, 76, 87 and 80 in the present invention are utilized for ease of processing of the particular embodiment shown. However, due to the similar properties of thermally conductive layers 70, 72, 76, 78 and 80, these layers may be deposited as a single layer, of a single material, or as any number of layers or materials as desired. Accordingly, in another embodiment, a thermally conductive and electrically insulative layer 74 may be positioned on top surface 66 of mesa 30 and a single, thermally and electrically conductive layer may be positioned in the areas shown by layers 70, 72, 76, 78 and 80, i.e., along side surfaces 68 of mesa 30 and on top of dielectric layer 74 which may be positioned on top surface 66 of mesa 30.
Mesa 30, therefore, is surrounded on sides 68 and on top surface 66 by thermally conductive material such that heat generated by emitter layer 38 may be thermally shunted to PCB 22 through these layers by thermal dissipation path 82. Thermal dissipation path 82 may extend away from, i.e., in an opposite direction from, base layer 36 and collector layer 34 such that heat may not travel through these layers to be dissipated from device 14. Accordingly, use of a thermal dissipation path 82 that extends in a direction opposite from base layer 36 and collector layer 34 may be more effective than heat dissipation structures of the prior art which may require that heat be dissipated to device substrate 28 in the direction of and through a base and a collector along heat dissipation path 84.
Moreover, circuit substrate 22 may be larger in size than a size of device substrate 28 such that circuit substrate 22 may define a larger heat sink than device substrate 28. Additionally, emitter layer 38, which may generate heat that may be desired to be dissipated, may be positioned closer to heat dissipation structure 12 than to device substrate 28, such that heat dissipation to structure 12 along path 82 may be the path of least resistance, compared with a heat dissipation path 84 that may extend to device substrate 28 through base layer 36 and collector layer 34. Accordingly, by providing a thermally conductive material on side surface 68 and on top surface 66 of mesa 30, heat may be readily dissipated from mesa 30 along path 82 in a direction 86 more effectively than may take place along a heat dissipation path 84 in a direction 88 through device 14 itself.
A method of manufacturing heat dissipation structure 12 will now be described. First, a mesa 30 may be provided having a side surface 68 and a top surface 66. A thermally conductive material, such as layers 74 and 72, may be placed on side surface 68 and on top surface 66. The thermally conductive material may then be thermally connected to a circuit substrate 22 so as to define a path 82 of heat dissipation that extends in a direction opposite from base layer 36, collector layer 34, and device substrate 28.
Other variations and modifications of the concepts described herein may be utilized and fall within the scope of the claims below.
