Claims
- 1. A multilevel interconnect structure, comprising:
- first interconnects arranged within a first elevational plane, said first interconnects being at least partially arranged upon an underlying dielectric layer arranged above a semiconductor substrate;
- a first dielectric layer arranged above said first interconnects;
- a second dielectric layer arranged upon said first dielectric layer;
- a third interconnect arranged within a third elevational plane and upon said second dielectric layer;
- a second interconnect arranged within a second elevational plane and electrically coupled to a first contact, wherein said first contact extends through said first dielectric layer from a first one of said first interconnects to said second interconnect, wherein said second interconnect extends to an upper surface of said second dielectric layer a diagonally spaced distance away from said third interconnect;
- a second contact extending through said pair of dielectric layers between a second one of said first interconnects and said third interconnect; and
- wherein said first interconnects, said first contact, said second interconnect, said second contact, and said third interconnect are arranged within a same cross-sectional plane.
- 2. The multilevel interconnect structure as recited in claim 1, wherein said second contact extends along an axis parallel to another axis through which said first contact extends.
- 3. The multilevel interconnect structure as recited in claim 1, wherein n said second interconnect and said first contact comprise e tungsten.
- 4. The multilevel interconnect structure as recited in claim 1, wherein said first interconnects and said third interconnect comprise aluminum.
- 5. The multilevel interconnect structure as recited in claim 1, wherein said p air of dielectric layers comprise oxide.
- 6. The multilevel interconnect structure as recited in claim 1, wherein said first contact extends between an upper surface of said first one of said first interconnects and a lower surface of said second interconnect.
- 7. The multilevel interconnect structure as recited in claim 1, wherein said second contact is spaced from said second interconnect.
- 8. The multilevel interconnect structure as recited in claim 1, wherein said second contact extends between an upper surface of said second one of said first interconnects and a lower surface of said third interconnect.
- 9. The multilevel interconnect structure of claim 1, wherein a lateral extent of said second interconnect above said semiconductor substrate is greater than a lateral extent of said first contact above said semiconductor substrate.
- 10. The multilevel interconnect structure of claim 1, wherein said second interconnect is arranged upon said second dielectric layer.
- 11. The multilevel interconnect structure of claim 1, wherein said first dielectric layer is further arranged around said first interconnects.
- 12. A multilevel interconnect structure, comprising:
- first interconnects arranged within a first elevational plane, said first interconnects being at least partially arranged upon an underlying dielectric layer arranged above a semiconductor substrate;
- a first dielectric layer arranged above said first interconnects;
- first plugs extending from respective first interconnects through said first dielectric layer;
- second interconnects arranged within a second elevational plane and upon said first dielectric layer, each of said second interconnects being in contact with one of said plugs;
- a second dielectric layer arranged substantially coplanar with said second interconnects;
- an intermediate plug arranged upon one of said first plugs spaced from and substantially coplanar with said second interconnects, said intermediate plug extending through said second dielectric layer;
- a third interconnect arranged within a third elevational plane and upon said second dielectric layer, said third interconnect being in contact with said intermediate plug; and
- wherein said first interconnects, said first plugs, said second interconnects, said inter mediate plug, and said third interconnect are arranged within a same cross-sectional plane.
- 13. The multilevel interconnect structure of claim 12, wherein each of said second interconnects is diagonally spaced from said third interconnect.
- 14. The multilevel interconnect structure of claim 13, wherein said second interconnects extend to an upper surface of said second dielectric layer.
- 15. The multilevel interconnect structure of claim 12, wherein said plugs and said second interconnects comprise tungsten.
- 16. The multilevel interconnect structure of claim 12, wherein said first interconnects and said third interconnect comprise aluminum.
- 17. The multilevel interconnect structure of claim 12, wherein said first and second dielectric layers comprise oxide.
- 18. The multilevel interconnect structure of claim 12, wherein each of said second interconnects are arranged upon one of said respective plugs.
- 19. The multilevel interconnect structure of claim 12, wherein a lateral extent of said third interconnect above said semiconductor substrate is greater than a lateral extent of said intermediate plug above said semiconductor substrate.
- 20. The multilevel interconnect structure of claim 19, wherein a lateral extent of each of said second interconnects above the semiconductor substrate is greater than a lateral extent of each of said plugs above the semiconductor substrate.
- 21. The multilevel interconnect structure of claim 12, wherein said first dielectric layer is further arranged around said first interconnects.
Parent Case Info
This is a division of application Ser. No. 08/655,244, filed Jun. 5, 1996, now U.S. Pat. No. 5,846,876.
US Referenced Citations (19)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0 710 981 |
Aug 1996 |
EPX |
Non-Patent Literature Citations (1)
Entry |
Wolf, Stanley, Ph.D., Silicon Processing for the VLSI Era, vol. 2: Process Integration, 1990 by Lattice Press, pp. 279-287. |
Divisions (1)
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Number |
Date |
Country |
Parent |
655244 |
Jun 1996 |
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