Patent Application
20160056099
The present invention is directed to semiconductor integrated circuits and, more particularly, to a semiconductor die having on-die decoupling capacitors.
Semiconductor processor devices include a variety of types of high-speed (high frequency) interfaces such as Serializer/Deserializer (SerDes) lanes, Peripheral Component Interconnect Express (PCIe) buses, Media Independent Interfaces (MII), and input/output (I/O) interfaces such as RapidIO. Many of these high-speed interfaces are provided with on-die decoupling capacitors (bypass capacitors) to reduce noise on signal lines and power supply lines. Often, a separate, dedicated decoupling capacitor is provided for each high-speed interface of the design in order to avoid incompatibility of connecting the interfaces to a common decoupling capacitor.
While there may be many high-speed interfaces in a semiconductor processor device, in variants (i.e., different device personalities) of the device, several different interfaces may be unused. For example, when packaging one variant of the device, a first interface may be used but a second is unused, while in another variant, the first interface is unused but the second is used. The provision of unused decoupling capacitors represents a waste of die area and unnecessary cost, which it is desirable to avoid.
The present invention, together with objects and advantages thereof, may best be understood by reference to the following description of embodiments thereof shown in the accompanying drawings. Elements in the drawings are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
The contacts 106 are connected to die bonding pads 108 on the active surface of the die 102 with bond wires 110, which make signal and power connections with the external circuitry. As shown in
Referring to
The device 100 illustrated in
In this way, a single decoupling capacitor 502 is shared between the two mutually exclusive interfaces 402 and 404. The value and the die area of the shared capacitor are significantly smaller than the sum of the capacitors 406 and 408 used in the conventional configuration 400. The value of the shared capacitor 502 can be the larger of the values required by the interfaces 402 and 404. It is also possible to use more than one decoupling capacitor 502 for the interfaces 402 and 404, while still reducing the area of the capacitors on the die 102. For example, if self-resonating frequency requirements need different capacitance values for the two interfaces 402 and 404, the value of the shared capacitance whose connection is switched between the interfaces can be less than the larger of the values required by one of the interfaces 402 and 404, and supplemented by a capacitance permanently connected to that interface to obtain the larger value required when that interface is used.
By way of example, positions for capacitor pads 504, 506, 508, 510 and internal connection pads 512, 514 and 516, 518 are shown in dashed lines in
The internal connection members 520, 522 may comprise bond wires that connect the selected internal connection pad(s) 512, 514 or 516, 518 to the capacitor pad(s) 504, 506, 508, 510. The bond wires may be bare or coated (insulated), both of which are commercially available and known by those of skill in the art. The internal connections can then be made during the same wire bonding process as the external connections. Such a process is readily adapted to different packaging requirements for different product variants. It will be appreciated that other connection techniques may be used for the selective bond wires 520, 522 provided that the selective internal connections are made late in the production process, when the product variants are differentiated.
The internal connection member may comprise a bond wire 520, 522 that connects the selected internal connection pad(s) 512, 514 or 516, 518 directly to the capacitor pad 504, 506, 508, 510 as shown in
In another configuration 700, illustrated in
The first and second interfaces 402, 404 may have first and second power distribution lines 524, 526 and 528, 530 respectively, and the first and second internal connection pads 512, 514 or 516, 518 are connected to the first and second power distribution lines 524, 526 and 528, 530 respectively. In this example, the power supply has pairs of buses VDD
The bond wires 110 and 520, 522 for the selected one of the first and the second interfaces 402 and 404 may connect operationally the die bonding pads 108 with the leads 106 of the package 104 and the internal connection pads 512, 514 or 516, 518 with the capacitor pads 504, 506 or 508, 510 of the die 102, and leave floating internal and external connection pads of the other one of the first and the second interfaces 402, 404.
The present invention includes an IC semiconductor die 102 for connection in a device 100 and having at least one decoupling capacitor 502, at least one capacitor pad 504, 506, 508, 510 connected to the decoupling capacitor 502, and first and second internal connection pads 512, 514 and 516, 518 connected respectively to the first and second interfaces 402, 404 for connection by at least one bond wire 520, 522 alternatively to the capacitor pad 512, 514 or 516, 518 for selectively decoupling the first or the second interface 402, 404.
In more detail, the method 800 starts at 802 by identifying high frequency (HF) interfaces such as 402, 404 that need decoupling capacitance such as 502. The die 102 is laid out at 804 with a common decoupling capacitance 502 for a plurality of interfaces 402, 404 that are used alternatively in different variants or personalities of the device 100. At 806, a die 102 is produced with electrically floating connection pads 512, 514516, 518 connected to the first and second interfaces 402 and 404 and electrically floating capacitor pads 504, 506, 508, 510 connecting within the die with the decoupling capacitance 502, and through which selective connections can be made to the capacitance 502.
A decision is taken at 808 whether the first interface 402 is to be used in the device 100. If it is, at 810 the capacitor pads 504, 508 are connected selectively to the first interface 402 through the internal connection pads 512, 514 with bond wires 520, 522, so that the capacitance 502 is connected to decouple the first interface 402. The first interface 402 is then connected with package leads 106 through the die bonding pads 108 at 812.
If at 808 the first interface 402 is not to be used in the device 100, a decision is taken at 814 whether the second interface 404 is to be used in the device 100. If it is, at 816 the capacitor pads 506, 510 are connected selectively to the second interface 404 through the internal connection pads 516, 518 by bond wires 520, 522 so that the capacitor 502 is connected to decouple the first interface 404. The second interface 404 is then connected with package leads 106 through the die bonding pads 108 at 818.
If at 814 the second interface 40 is not to be used in the device 100 either, the capacitor pads 504, 506, 508, 510 are left floating.
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. It will, however, be evident that various modifications and changes may be made therein without departing from the broader spirit and scope of the invention as set forth in the appended claims.
For example, the semiconductor die described herein can be any semiconductor material or combinations of materials, such as gallium arsenide, silicon germanium, silicon-on-insulator (SOI), silicon, monocrystalline silicon, the like, and combinations of the above.
The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice-versa. Also, a plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.
Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
In the claims, the word ‘comprising’ or ‘having’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
