Patent Application
20050239268
Various integrated circuit (“IC”) manufacturing processes may introduce minor structural errors into the circuit. Such errors may comprise, for example, resistances in various parts of the IC that are different than the resistances specified by a designer. A “trim circuit” is a type of circuit that may be used to correct for such errors. In general, a trim circuit is able to adjust various sections of the IC and generally comprises trim pads onto which adjustment signals may be delivered. The adjustment signals electrically manipulate the trim circuit to correct for the errors. Even though the trim pads are used only during manufacturing and prior to packaging of the IC, the trim pads remain on the die, thereby wasting valuable space on the die.
The problems noted above are solved at least in part by a method for reducing chip size by relocating trim pads. One exemplary embodiment may comprise forming a pad in a scribe street adjacent to an integrated circuit (“IC”), electrically connecting the pad to the IC, and sawing the scribe street. In other embodiments, a wafer comprises an IC, a scribe street adjacent to the IC, and a pad formed in the scribe street. The pad is electrically connected to the IC.
For a detailed description of exemplary embodiments of the invention, reference will now be made to the accompanying drawings in which:
a illustrates the layout of a conventional IC;
b illustrates a layout of an IC in accordance with preferred embodiments of the invention;
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, various companies may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . . ” Also, the term “couple” or “couples” is intended to mean either an indirect or direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection by way of other devices and connections.
The following discussion is directed to various embodiments of the invention. Although one or more of these embodiments may be preferred, the embodiments disclosed should not be interpreted, or otherwise used, as limiting the scope of the disclosure, including the claims. In addition, one skilled in the art will understand that the following description has broad application, and the discussion of any embodiment is meant only to be exemplary of that embodiment, and not intended to intimate that the scope of the disclosure, including the claims, is limited to that embodiment.
Various IC layout embodiments are described herein that result in a more efficient use of die surface area. Also described are techniques for enhancing multiprobe testing performance and process monitor capability by using scribe street test pads.
During conventional wafer saw operation, it is undesirable to have metal in the scribe street. Metal in the scribe street tends to clog saw blades and requires slower cutting rates in production. In at least some embodiments, because the trim pads 204 may clog the saw blades, the trim pads 204 may be etched away to clear the scribe street 202 after their use and prior to the saw operation. Such an embodiment may comprise applying an etch-resist over the IC 200 so that only the scribe streets 202, 208 and the trim pads 204 are exposed. Then, at least a portion of the trim pad(s) 204 may be etched away, and subsequently the etch-resist may be removed from the IC 200.
a illustrates a conventional IC layout 100 after a saw operation. In
Applications of the above technique are not limited to trim circuits. In at least some embodiments, placing test pads in a scribe street may enable a designer to add to a layout test geometries and/or process monitor structures that would otherwise occupy a certain amount of space on a chip. Such a technique may be used to enhance process control, expand capability to monitor various circuit components, and/or improve testing capability during a multiprobe testing session. One such embodiment is illustrated in the embodiment of
Linear device test specifications may require various components not already on the IC 200 (e.g., capacitors, diodes, resistors, transistors, inductors) in parametric testing. Such components may be attached to the IC 200 and interfaced to multiprobe testing equipment using the test pads 212-226. For example, the pad pairs 212 and 214, 214 and 216, 218 and 220 may be electrically connected to a diode, resistor, and capacitor, respectively. Further, pads 222-226 may be connected to a transistor such as an NPN transistor. In general, any electrical component may be coupled to the IC 200 for purposes of process monitoring during a multiprobe testing session or experimental measurement session.
The above discussion is meant to be illustrative of the principles and various embodiments of the present invention. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. For example, the techniques described above may apply to diode trim circuits, fuse trim circuits, non-trim circuits and/or any appropriate circuit. The techniques also may be used to provide probe access to device nodes on the chip that would otherwise be unmeasurable. It is intended that the following claims be interpreted to embrace all such variations and modifications.
