Claims
- 1. An integrated circuit comprising:A. a substrate of semiconductor material; B. processor circuits formed on the substrate, the processor circuits including address leads on the substrate, the address leads carrying address signals defining an addressable memory space, the addressable memory space being divided into at least two segments, and the processor circuits including data leads on the substrate coupled to addressable locations in the addressable memory space; and C. wait state register circuits formed on the substrate and coupled to the address leads, the wait state register circuits including at least two registers each containing memory wait state information, one register for each segment of the addressable memory space, the registers being coupled to the data leads to receive the memory wait state information in the form of data signals from the data leads, and the memory wait state information in each register defining a number of memory wait states for each segment.
- 2. The integrated circuit of claim 1 in which the processor circuits include multiplier circuits coupled to arithmetic and logic units circuits.
- 3. The integrated circuit of claim 1 in which each register contains at least four binary bits of information.
- 4. The integrated circuit of claim 1 in which the memory wait state information in each register is a binary number of from zero to fifteen.
- 5. The integrated circuit of claim 1 including decoder circuits coupled to the address leads that decode the address signals to select a register and wait state generator circuits including a logic gate to effect the wait states.
- 6. The integrated circuit of claim 1 including decoder circuits coupled to the address leads and the registers that decode the address signals to select a register and wait state generator circuits coupled to the registers that include binary down counter circuits and a logic gate to effect the wait states.
CROSS REFERENCE TO RELATED APPLICATIONS
This patent is related to co-assigned U.S. Pat. Nos. 5,586,275; 5,072,418; 5,142,677; 5,155,812; 5,829,054; and 5,724,248, all filed contemporaneously herewith and incorporated herein by reference.
This application is a divisional of application Ser. No. 09/360,488, filed Jul. 23, 1999, now pending; which is a divisional of application Ser. No. 08/906,863, filed Aug. 6, 1997, now U.S. Pat. No. 5,946,483; which is a divisional of application Ser. No. 08/293,259, filed Aug. 19, 1994, now U.S. Pat. No. 5,907,714; which is a continuation of application Ser. No. 07/967,942, filed Oct. 28, 1992, now abandoned; which is a continuation of application Ser. No. 07/347,967, filed May 4, 1989, now abandoned.
US Referenced Citations (26)
Non-Patent Literature Citations (5)
Entry |
Second Generation TMS320 User's Guide ; p. 3-6.* |
“DSP56000 Digital Signal Processor's User's Manual”, Motorola, 1986, pp. 2-12-18, 3-2, 7-1-3. |
“DSP96001”, Motorola, 1988, pp. 1, 2, 6, 9, 10. |
Second-Generation TMS320 User's Guide, Texas Instruments, pp. 6-10-26,Dec. 1987. |
First-Generation TMS320 User's Guide, Texas Instruments, pp. 3-9, A-1-20, 6-2-5, Apr. 1988. |
Continuations (2)
|
Number |
Date |
Country |
Parent |
07/967942 |
Oct 1992 |
US |
Child |
08/293259 |
|
US |
Parent |
07/347967 |
May 1989 |
US |
Child |
07/967942 |
|
US |