Embodiments disclosed herein pertain to integrated circuitry, and to methods of forming capacitors including methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array.
Capacitors are one type of component used in the fabrication of integrated circuits, for example in DRAM and other memory circuitry. A capacitor is comprised of two conductive electrodes separated by a non-conducting dielectric region. As integrated circuitry density has increased, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing capacitor area. The increase in density has typically resulted in greater reduction in the horizontal dimension of capacitors as compared to the vertical dimension. In many instances, the vertical dimension of capacitors has increased.
One manner of fabricating capacitors is to initially form an insulative material within which a capacitor storage electrode is formed. For example, an array of capacitor electrode openings for individual capacitors may be fabricated in an insulative support material, with an example material being silicon dioxide doped with one or both of phosphorus and boron. Openings within which some or all of the capacitors are formed are etched into the support material. It can be difficult to etch such openings through the support material, particularly where the openings are deep.
Further and regardless, it is often desirable to etch away most if not all of the capacitor electrode support material after individual capacitor electrodes have been formed within the openings. Such enables outer sidewall surfaces of the electrodes to provide increased area and thereby increased capacitance for the capacitors being formed. However, capacitor electrodes formed in deep openings are often correspondingly much taller than they are wide. This can lead to toppling of the capacitor electrodes, either during etching to expose the outer sidewalls surfaces, during transport of the substrate, and during deposition of the capacitor dielectric layer and/or outer capacitor electrode layer. U.S. Pat. No. 6,667,502 teaches the provision of a brace or retaining structure intended to alleviate such toppling. Other aspects associated in the formation of a plurality of capacitors, some of which include bracing structures, are also disclosed and are:
Fabrication of capacitors in memory circuitry may include forming an array of capacitors within a capacitor array area. Control or other circuitry area is often displaced from the capacitor array area, and the substrate may include an intervening area between the capacitor array area and the control or other circuitry area.
Some embodiments include methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array. Some embodiments include methods of forming capacitors regardless of fabrication of integrated circuitry comprising both array and peripheral areas. Example methods of forming capacitors in accordance with embodiments of the invention are described with reference to
Construction 10 may comprise a capacitor array area 14 and a peripheral circuitry area 16. An example interface line 15 has been used in the drawings to define an interface of capacitor array area 14 and peripheral circuitry area 16. Logic circuitry may be fabricated within peripheral circuitry area 16. Control and/or other peripheral circuitry for operating a memory array may or may not be fully or partially within array area 14, with an example memory array area 14 as a minimum encompassing all of the memory cells of a given memory array/sub-memory array. Further, multiple sub-arrays might also be fabricated and operated independently, in tandem, or otherwise relative one another. As used herein, a “sub-array” or “sub-memory array” may be considered as an array. Various circuit devices (not shown) could be associated with peripheral circuitry area 16, as well as with capacitor array area 14, at the processing stage of
Electrically conductive node locations 18, 20 are shown within memory array area 14, and electrically conductive node locations 22, 24, 26 are shown within peripheral circuitry area 16. Node locations 18, 20, 22, 24, 26 may correspond to, for example, conductively-doped diffusion regions within a semiconductive material of substrate 12, and/or to conductive pedestals associated with substrate 12. Although the node locations are shown to be electrically conductive at the processing stage of
Construction 10 may comprise dielectric material 28 elevationally over (i.e., atop) substrate 12 and/or node locations 18, 20, 22, 24, 26. Dielectric material 28 may be homogenous or non-homogenous, with silicon dioxide and silicon nitride being examples. An example thickness range for dielectric material 28 is from about 50 Angstroms to about 300 Angstroms.
A support material 30 is provided elevationally over substrate 12 within capacitor array area 14 and peripheral circuitry area 18. In one embodiment where dielectric material 28 is provided, support material 30 may be provided directly against dielectric material 28. In this document, a material or structure is “directly against” another when there is at least some physical touching contact of the stated materials or structures relative one another. In contrast, “over” encompasses “directly against” as well as constructions where intervening material(s) or structure(s) result(s) in no physical touching contact of the stated materials or structures relative one another. Regardless, support material 30 is at least one of semiconductive or conductive, and may be homogenous or non-homogenous. For example, support material 30 may be a single homogenous layer of a conductive or semiconductive material, multiple layers of a single homogenous semiconductive or conductive material, or multiple layers of differing compositions of semiconductive and/or conductive materials. An example support material comprises silicon, for example amorphous, monocrystalline, and/or polycrystalline silicon whether doped or undoped. One particular ideal material is polycrystalline silicon which is either undoped to possess semiconductor properties, or lightly doped to possess semiconductor properties. As an alternate example, a polycrystalline silicon support material 30 may be heavily doped sufficiently to be electrically conductive. Additional example conductive materials include gallium nitride and carbon whether alone or in combination. An example thickness range for support material 30 is from about 2,500 Angstroms to about 3 microns.
A dielectric material 32 may be provided elevationally outward of (i.e. atop) semiconductive and/or conductive support material 30, and if provided may be directly against support material 30. Dielectric material 32 may be of the same composition or of different compositions from that of dielectric material 28. Dielectric material 32 may provide a chemical mechanical polishing stop, etch stop, and/or other function. An example thickness for dielectric material 32 is from about 600 Angstroms to about 1,500 Angstroms.
Referring to
Referring to
When both of capacitor openings 40 and antifuse openings 42 are ultimately formed, such may be formed in the same masking step (as shown) or in different masking steps. Regardless, capacitor openings 40 have at least one of semiconductive or conductive sidewalls 44, and antifuse openings 42 have at least one of semiconductive or conductive sidewalls 46. Sidewalls 44 and 46 may comprise both a semiconductive portion and a conductive portion where, for example, support material 30 comprises a semiconductive portion elevationally inward (i.e., downward on the plane of the page upon which
Referring to
Referring to
Insulator 50 may be homogenous or non-homogenous, with an example thickness being from about 10 Angstroms to about 75 Angstroms. In the depicted example, insulator 50 is shown as comprising an insulative material 51 and an insulative material 52 (
A pair of capacitor electrodes having a capacitor dielectric there-between is formed within the capacitor openings laterally of the deposited insulator. A pair of antifuse electrodes having insulative material there-between is formed within the respective antifuse openings laterally of the deposited insulator in the antifuse openings. Such capacitors and antifuses may be formed at the same time or at different times.
Referring to
Appropriate circuitry (not shown) would be associated with electrodes 56 and 64 of antifuses 65 to enable selective programming of individual antifuses 65 (i.e., by breaking down/“blowing” dielectric material 60 within individual openings 42 to cause conductive material to bridge between outer electrode 64 and an individual inner electrode 56). Appropriate circuitry (not shown) would be associated with capacitor electrodes 54 and 62 of capacitors 63 to enable selective operation of individual capacitors 63 that would not include breaking down/“blowing” capacitor dielectric 58 to short electrodes 54 and 62 to one another. In other words, although an antifuse and a capacitor are each an electronic device, antifuses are not capacitors and capacitors are not antifuses in the context of this document. While each may be of the same or similar construction(s) having a pair of electrodes with dielectric there-between, other respective portions of the integrated circuitry would be configured to operate the electronic device either as an antifuse or a capacitor and thereby be determinative of device type. These other respective circuitry portions are not material to embodiments of this invention, and may be existing or later developed circuitry within the skill of the artisan.
Referring to
Referring to
The support material may be considered as having an elevationally outermost (i.e., a top) surface and an elevationally innermost (i.e., a bottom) surface. Some embodiments of the invention comprise providing at least one dielectric layer within conductive and/or semiconductive support material between the elevationally outermost and elevationally innermost surfaces of such support material. An example of such an embodiment is described with reference to
In contradistinction to the embodiment of
Embodiments of the invention include any of the above constructions as shown and/or described independent of method of manufacture.
In some embodiments, methods of forming capacitors comprise providing a support material over a substrate. The support material is at least one of semiconductive or conductive. Openings are formed into the support material. The openings comprise at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective openings is laterally adjacent the deposited insulator.
In some embodiments, methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array comprise providing a support material over a substrate within a capacitor array area and within peripheral circuitry area. The support material is at least one of conductive or semiconductive. Capacitor openings are formed into the support material within the capacitor array area. The capacitor openings comprise at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive capacitor opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective capacitor openings laterally inward of the deposited insulator in the capacitor openings. One of the pair of capacitor electrodes within the respective capacitor openings is laterally adjacent the deposited insulator in the capacitor openings. Contact openings are formed into the support material within the peripheral circuitry area. The contact openings comprise at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive contact opening sidewalls. A conductive contact is formed within the respective contact openings laterally inward of the deposited insulator in the contact openings.
In some embodiments, methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array comprise providing a support material over a substrate within a capacitor array area and within peripheral circuitry area. The support material is at least one of semiconductive or conductive. Capacitor openings are formed into the support material within the capacitor array area. The capacitor openings comprise at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive capacitor opening sidewalls. A pair of capacitor electrodes having capacitor dielectric there-between is formed within the respective capacitor openings laterally inward of the deposited insulator. One of the pair of capacitor electrodes within the respective capacitor openings is laterally adjacent the deposited insulator in the capacitor openings. Antifuse openings are formed into the support material within the peripheral circuitry area. The antifuse openings comprise at least one of semiconductive or conductive sidewalls. An insulator is deposited along the semiconductive and/or conductive antifuse opening sidewalls. A pair of antifuse electrodes having insulative material there-between is formed within the respective antifuse openings laterally inward of the deposited insulator in the antifuse openings. One of the pair of antifuse electrodes within the respective antifuse openings is laterally adjacent the deposited insulator in the antifuse openings.
In some embodiments, integrated circuitry includes a plurality of electronic devices which individually comprise a pair of conductive electrodes having dielectric there-between. The integrated circuitry includes a substrate comprising support material there-over. The support material is at least one of semiconductive or conductive. Electronic device openings extend into the support material, and comprise at least one of semiconductive or conductive sidewalls. An insulator is along the semiconductive and/or conductive electronic device opening sidewalls. Individual electronic devices are within individual of the electronic device openings laterally inward of the insulator that is along the semiconductive and/or conductive electronic device opening sidewalls. The electronic devices individually comprise a pair of conductive electrodes having dielectric there-between. One of the pair of conductive electrodes within the respective electronic device openings is laterally adjacent the deposited insulator.
In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the claims are not limited to the specific features shown and described, since the means herein disclosed comprise example embodiments. The claims are thus to be afforded full scope as literally worded, and to be appropriately interpreted in accordance with the doctrine of equivalents.
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