Patent Application
20200194496
The technical field generally relates to sophisticated semiconductor devices and the manufacturing of such devices, and, more specifically, to integrated circuits with memory structures embedded in metallization layers.
As the density of memory devices in integrated circuits increases, integration of such devices in back end of line (BEOL) processing becomes difficult. For example, placement of memory devices within the metallization layers is challenging.
For magnetoresistive random access memory (MRAM) technology, memory structures such as magnetic tunnel junction (MTJ) stacks may require greater heights than those of the metallization vertical interconnect access (vias) in existing processing. As a result, simple substitution of MTJ stacks at the locations of metallization vias is impractical. Therefore, more complicated arrangements may be utilized to form MTJ stacks during BEOL processing.
Accordingly, it is desirable to provide improved integrated circuits with embedded memory structures, and improved methods for fabricating such structures. It is further desirable to provide a memory structure with improved performance. It is also desirable to provide methods for fabricating integrated circuits with high density memory structures that are less expensive and less time consuming than current methods. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.
Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming from a first metallization layer a first lower conductive interconnect in a first region of a dielectric layer and a second lower conductive interconnect in a second region of the dielectric layer. The method includes forming a memory structure in the first region. Further, the method includes depositing an interlayer dielectric over the first region and over the second region. Also, the method includes forming from a second metallization layer a first upper conductive interconnect over the interlayer dielectric, wherein the first upper conductive interconnect is coupled to the memory structure.
In another embodiment, a method for fabricating an integrated circuit includes forming a lower conductive interconnect in a dielectric layer; depositing a bottom electrode layer over the lower conductive interconnect and the dielectric layer; depositing magnetic tunnel junction (MTJ) layers over the bottom electrode layer; depositing a top electrode layer over the MTJ layers; and etching the top electrode layer, the MTJ layers, the bottom electrode layer, and an upper portion of the dielectric layer to form an MTJ structure, a dielectric pillar, and a trench, wherein the dielectric pillar is surrounded by the trench, and wherein the MTJ structures is disposed directly over the dielectric pillar.
In another embodiment, an integrated circuit is provided and includes a first lower conductive interconnect and second lower conductive interconnect formed a common first metallization layer. Further, the integrated circuit includes a bottom electrode in direct physical contact with the first lower conductive interconnect, a magnetic tunnel junction (MTJ) structure over and in direct physical contact with the bottom electrode, and a top electrode in direct physical contact with the MTJ structure. The integrated circuit also includes a conductive via in direct physical contact with the second lower conductive interconnect. The integrated circuit further includes a first upper conductive interconnect and second upper conductive interconnect formed a common second metallization layer, wherein the first upper conductive interconnect is in direct physical contact with the top electrode, and wherein the second upper conductive interconnect is in direct physical contact with the conductive via.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The various embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely exemplary in nature and is not intended to limit the integrated circuits with embedded memory structures and methods for fabricating such integrated circuits. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or brief summary, or in the following detailed description.
For the sake of brevity, conventional techniques related to conventional device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication memory devices are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. Further, it is noted that integrated circuits with memory structure, include a varying number of components and that single components shown in the illustrations may be representative of multiple components.
As used herein, it will be understood that when an element or layer is referred to as being “over” or “under” another element or layer, it may be directly on the other element or layer, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer. Further, spatially relative terms, such as “upper”, “uppermost”, “over”, “under”, “lower”, “lowest” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “under” can encompass either an orientation of above or below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
Further, as used herein, a layer identified as a “material layer” or as being a “material” includes at least 50 wt. % of the recited material. As used herein, a layer identified as a “primarily material layer” or as being “primarily material” is a layer that includes at least 90 wt. % of the recited material.
As will be readily apparent to those skilled in the art upon a complete reading of the disclosure, the devices disclosed herein may be employed with a variety of technologies, and may be incorporated into a variety of integrated circuit products. With reference to the attached drawings, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail. It should be understood that the various features and layers in the attached drawings may not be to scale.
Embodiments herein are directed towards memory structures, for example magnetoresistive random access memory (MRAM) structures or resistive random access memory (RRAM) structures, arrays of such structures, and various methods of fabricating such structures or arrays. As described herein, an exemplary memory structure is embedded between directly adjacent metallization layers, i.e., a first and a second metallization layer, such that the memory structure does not pass through a plane defined by an unused intermediate metallization layer between the first and second metallization layers. In other words, an exemplary integrated circuit contacts a bottom electrode of an MTJ structure directly to a lower metallization layer (Mx), and contacts a top electrode of the MTJ structure directly to the next highest metallization layer (Mx+1). This structure is unlike conventional processing wherein a memory structure contacted to a lower metallization layer (Mx) by a conductive via is at too great a height to be contacted to the next immediately higher metallization layer (Mx+1).
While not illustrated, semiconductor devices, such as metal oxide field effect transistors (MOSFETs), capacitors, resistors, and the like may be formed over or in the semiconductor substrate below the dielectric layer 14 according to conventional integrated circuit processing. The devices formed during a series of processes that form individual integrated circuit components, e.g., transistors, capacitors, resistors, etc., over substrate may be interconnected into a circuit by means of one or more metal interconnecting layers, i.e., metallization layers.
In an exemplary embodiment, various metal and dielectric layer deposition and etching processes may be performed according to conventional integrated circuit processing to form the dielectric layer 14 with an embedded metallization layer 15 in selective contact with underlying devices. As shown, first lower conductive interconnects 16 are formed from the metallization layer 15 in a first region 11 of the integrated circuit device 10 and second lower conductive interconnects 18 (only one second lower conductive interconnect is illustrated) are formed from the metallization layer 15 in a second region 12 of the integrated circuit device 10. As a result, the first lower conductive interconnects 16 and the second lower conductive interconnects 18 are formed with a common coplanar uppermost surface 17, i.e., the uppermost surface of the first metallization layer 15.
In an exemplary embodiment, the metallization layer 15 is formed utilizing a damascene process. Further, an exemplary metallization layer 15 is copper, though other suitable conductive materials may be used.
In
In an exemplary embodiment, lower sublayer 22 is a passivation layer 22, which is formed on the second lower conductive interconnect 18. An exemplary upper sublayer 24 is an insulator layer 24 formed on the passivation layer 22. In one example, silicon carbide with nitrogen deposited using chemical vapor deposition (CVD) from a trimethylsilane source, which is commercially available from Applied Materials under the tradename of BLOK®, is used as the passivation layer 22. The compound with less nitrogen (N) (less than about 5 mol %), i.e., SiaCbNcHd, is referred to as “BLoK”, and the compound with more N (about 10 mol % to about 25 mol %), i.e., SiwCxNyHz, is referred to as “NBLoK”. BLoK has a lower dielectric constant of less than 4.0, whereas NBLoK has a dielectric constant of about 5.0. While BLoK is not a good oxygen barrier but is a good copper (Cu) barrier, NBLoK is both a good oxygen barrier and a good Cu barrier. In an exemplary embodiment, the passivation layer 22 is or includes NBLoK material. In one example, the insulator layer 24 is formed from silicon oxide. Specifically, the insulator layer 24 may be formed from tetraethyl orthosilicate (TEOS). Formation of the blocking layer 20 may include conventional deposition and lithography processing including masking and etching to remove the passivation layer 22 and insulator layer 24 from the first region 11 and to define the blocking layer 20 in the second region 12 as shown.
After formation of the blocking layer 20, the first region 11 may be cleaned such as by a soft pad touch up process. As shown in
Referring now to
Though not necessary, in certain embodiments the bottom electrode layer 31 and top electrode layer 35 are formed from a same metal material. An exemplary bottom electrode layer 31 is a conductive material, such as a metal, including metal alloys. In an exemplary embodiment, bottom electrode layer 31 is tantalum, tantalum nitride, titanium, tungsten, and/or other commonly used conductive metals. In an exemplary embodiment, the bottom electrode layer 31 is formed by depositing the conductive material by a CVD process. An exemplary top electrode layer 35 is a conductive material, such as a metal or a metal alloy. In an exemplary embodiment, top electrode layer 35 is tantalum, tantalum nitride, titanium, tungsten, and/or other commonly used conductive metals. In an exemplary embodiment, the top electrode layer 35 is formed by depositing the conductive material by a CVD process.
While three exemplary MTJ layers 32, 33, and 34 are illustrated, any number of desired and suitable MTJ layers may be utilized. Exemplary MTJ layers 32, 33 and 34 may include a magnetically fixed layer or polarizer layer, a tunnel barrier layer or layers, a magnetically free layer or storage layer, seed layers, wetting layers, spacer layers, anti-ferromagnetic layers, and the like. It is realized that MTJ layers of many variations may be provided that are within the scope of the present disclosure. The MTJ layers 32, 33 and 34 may be deposited using physical vapor deposition (PVD), CVD and/or ALD techniques.
In
It is noted that the etch process includes removal of the upper portion 13 (shown in
As shown, barrier regions 46 of the upper portion 13 of the dielectric layer 14 that lie directly under the memory structures 40 remain unetched and separate the first lower conductive interconnects 16 from the trenches 44. The barrier regions 46 form dielectric pillars on which the memory structures 40 are disposed.
Referring now to
After formation of the encapsulation layer 50, the interlayer dielectric 60 is formed over the first and second regions 11 and 12. The interlayer dielectric 60 may include several distinct layers. In an exemplary embodiment, the interlayer dielectric 60 is silicon oxide. In an exemplary embodiment, the interlayer dielectric 60 is deposited by a flowable CVD process. As a result, the interlayer dielectric 60 may fill gaps between adjacent memory structures 40 formed in array of memory structures 40. The method may further include annealing the interlayer dielectric 60 and planarizing the interlayer dielectric 60.
The method may continue in
As shown, the etch process includes etching the interlayer dielectric 60 over the memory structures 40 and removing the encapsulation layer 50 from over the memory structures 40. During the metallization process, i.e., the deposition of the second metallization layer 80, a conductive material such as a metal is deposited over the interlayer dielectric 60, into the etched trenches and into direct contact with the memory structures 40 to form the first upper conductive interconnects 86. Thus, after formation, the first upper conductive interconnects 86 are in direct physical contact with the top electrode of the respective memory structures 40.
Likewise, the conductive via 82 may be formed by patterning a via hole into a lower portion of the interlayer dielectric 60 and through the blocking layer 20 before filling the via hole with a conductive material, such as from the metallization layer 80. In an exemplary embodiment, the metallization process fills the via hole and the trench overlying the via hole to form the conductive via 82 and second upper conductive interconnect 88 from the second metallization layer 80.
In an exemplary embodiment, metallization layer 80 is formed from the same metal as the first metallization layer 15. For example, the metal may be copper. In an exemplary embodiment, the metallization layer 80 is formed by metal deposited by a sputtering process, an electroplating process, an electroless process or other suitable process. In
As a result of the processing described in
The described processing may provide for formation of memory structures 40 between adjacent metallization layers at technology nodes with increased scaling. For example, by eliminating the conductive via from the lower metallization layer to the memory structure, the memory structure is provided with sufficient vertical space to include a bottom electrode having a thickness (vertical) of about 10 nm, a stack of MTJ layers with a total thickness of about 40 nm, and a top electrode having a thickness of about 30 nm.
As described herein, an exemplary integrated circuit is provided with a memory structure, such as an MRAM structure like an MTJ stack, embedded between metallization layers. The exemplary memory structure is formed in direct physical contact with the underlying and overlying metallization layers. The metallization layers are vertically adjacent to one another such that no other metallization layers are disposed therebetween, whether in the first region or elsewhere on the semiconductor chip. The methods described herein provide for the integration of logic and memory structures seamlessly. Also, while often described in the context of MRAM, the method employed herein may be used in RRAM technology. Further, the processes described herein are similar to processes in conventional CMOS processing such that necessary process equipment and actions are available.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration as claimed in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope herein as set forth in the appended claims and the legal equivalents thereof.
