Patent Application
20240405024
Substrate parasitic leakage and voltage are challenges when devices are integrated into or on a same integrated circuit (IC) die. Various techniques have been developed to address such leakage and voltage. However, challenges may still persist, particularly for certain applications, such as high voltage applications.
This Summary is provided to introduce a brief selection of disclosed concepts in a simplified form that are further described below in the Detailed Description including the drawings provided. Various disclosed devices and methods may be beneficially applied to integrated devices with a conductive barrier structure. While such embodiments may be expected to provide electrical isolation of such devices from a substrate voltage, no particular result is a requirement unless explicitly recited in a particular claim.
An example described herein is a semiconductor device. The semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, and a gate. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The gate is over the barrier layer opposing the channel layer.
Another example is a semiconductor device. The semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, an isolation structure, a first gate, a first electrical contact, a second gate, and a second electrical contact. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is of a second semiconductor material and is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The isolation structure is between a respective first portion of the barrier layer, the channel layer, and the conductive barrier structure and a respective second portion of the barrier layer, the channel layer, and the conductive barrier structure. The first gate is over the first portion of the barrier layer opposing the channel layer. The first electrical contact is on a surface of the first portion of the barrier layer opposing the channel layer. The second gate is over the second portion of the barrier layer opposing the channel layer. The second electrical contact is on a surface of the second portion of the barrier layer opposing the channel layer, and the second electrical contact is electrically coupled to the first electrical contact. The isolation structure can be in the form of a trench, a doped region, an implanted region (e.g., of a neutral species), or a depletion region.
A further example is a semiconductor device. The semiconductor device includes a substrate, a conductive barrier structure, a channel layer, a barrier layer, a first gate, a second gate, a first electrical contact, and a second electrical contact. The substrate is of a first semiconductor material. The conductive barrier structure is on the substrate. The channel layer is on the conductive barrier structure. The barrier layer is on the channel layer, and the channel layer is between the barrier layer and the conductive barrier structure. The first gate and the second gate are over the barrier layer opposing the channel layer. The first electrical contact and the second electrical contact are on a surface of the barrier layer, and the first gate and the second gate are between the first electrical contact and the second electrical contact.
The foregoing summary outlines rather broadly various features of examples of the present disclosure in order that the following detailed description may be better understood. Additional features and advantages of such examples will be described hereinafter. The described examples may be readily utilized as a basis for modifying or designing other examples that are within the scope of the appended claims.
The drawings, and accompanying detailed description, are provided for understanding of features of various examples and do not limit the scope of the appended claims. The examples illustrated in the drawings and described in the accompanying detailed description may be readily utilized as a basis for modifying or designing other examples that are within the scope of the appended claims. Identical reference numerals may be used, where possible, to designate identical elements that are common among drawings. The figures are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale.
Various features are described hereinafter with reference to the figures. An illustrated example may not have all the aspects or advantages shown. An aspect or an advantage described in conjunction with a particular example is not necessarily limited to that example and can be practiced in any other examples even if not so illustrated or if not so explicitly described. Further, methods described herein may be described in a particular order of operations, but other methods according to other examples may be implemented in various other orders (e.g., including different serial or parallel performance of various operations) with more or fewer operations.
The present disclosure relates to integrated devices with a conductive barrier structure. Various devices are described in which a conductive barrier structure is implemented to provide isolation or shielding from a substrate voltage. The conductive barrier structure may decouple the substrate voltage from a device, which may permit more robust functionality of the device and integration of, e.g., multiple switching devices (such as high electron mobility transistors (HEMTs)) in an integrated circuit (IC) die. Other benefits and advantages may be achieved.
A conductive barrier structure is configured to conduct charges of a polarity, which may be an opposite polarity of charges that a channel of a device is configured to conduct. For example, a channel of an HEMT may include a two dimensional electron gas (2DEG), and the conductive barrier structure may include a two dimensional hole gas (2DHG). The conductive barrier structure may instead or also include a quantum well. The conductive barrier structure may include one or more materials that achieve band energy bending to achieve such conductivity, such as a 2DHG or quantum well. In some examples, a conductive barrier structure includes a confinement layer and a low bandgap energy material layer. In further examples, the conductive barrier structure includes a repeated unit of a confinement layer and a low bandgap energy material layer to achieve, for example, a combination of layers that have a series of 2DHGs and/or 2DEGs, a mini-superlattice structure, or a superlattice structure.
With such a conductive barrier structure, various techniques may be implemented to populate the conductive barrier structure with charge carriers of a particular polarity/conductivity type, such as holes. In some examples, a conductive barrier structure, and more particularly, a confinement layer (e.g., in which a 2DHG or quantum well is formed), may be populated with charge carriers by doping the confinement layer during fabrication. In such examples, the conductive barrier structure (e.g., the confinement layer) may be doped with a uniform doping concentration or with a lateral dopant gradient concentration. In some examples, charge carrier may be injected into a conductive barrier structure (e.g., a confinement layer) by a hybrid drain, a hybrid source, or hybrid gate technique. In a hybrid drain technique, a drain electrical contact is formed electrically coupled to an injection layer at the drain region of a switching device. In a hybrid source technique, a source electrical contact is formed electrically coupled to an injection layer at the source region of a switching device. In a hybrid gate technique, a gate layer may be selectively electrically coupled (e.g., by an active circuit) to a high potential node when the switching device of the gate layer is in an off state. In such techniques, charge carriers may be injected from the injection layer or gate layer to the conductive barrier structure when the device is in an off state, which may populate the conductive barrier structure with the charge carriers. In some examples, charge carriers may be injected into a conductive barrier structure (e.g., a confinement layer) by forming a conductive structure (e.g., an electrical contact) to the conductive barrier structure. The conductive structure may electrically couple the conductive barrier structure to a potential that is a source of charge carriers. Any one of the above techniques or any combination of two or more of the techniques may be implemented in various examples.
Additionally, a conductive structure electrically coupled to the conductive barrier structure may permit biasing the conductive barrier structure. The conductive barrier structure may be biased at a voltage that allows a switching device to change states (e.g., from off to on) faster. A substrate voltage proximate a gate of a switching device may modulate or affect switching of the switching device. By biasing the conductive barrier structure, the substrate voltage can be in a state that permits faster switching.
The example techniques described herein can be used in HEMTs for different applications, such as low voltage applications (e.g., with an operating voltage below 200V), medium voltage devices (e.g., with an operating voltage between 200-650V), high voltage devices (e.g., with an operating voltage above 650V), high frequency (RF and mm-wave) applications, etc. The example techniques described herein can also be used in other devices, such as Schottky diode, resistor, capacitor, etc., and integrate different devices on a same semiconductor die while providing isolation between each device.
Various examples are described herein. Although the specific examples may illustrate various aspects of the above generally described features, examples may incorporate any combination of the above generally described features (which are described in more detail in examples below). Three dimensional x-y-z axes are illustrated in some figures for ease of reference.
The first switching device 110 includes a first drain terminal D1, a first source terminal S1, and a first gate terminal G1. The second switching device 112 includes a second drain terminal D2, a second source terminal S2, and a second gate terminal G2. The first drain terminal D1 is electrically coupled to a first input terminal VIN1 of the IC die 104. The first source terminal S1 is electrically coupled to the second drain terminal D2 and can form a switching terminal. The second source terminal S2 is electrically coupled to a second input terminal VIN2 of the IC die 104. In a case where the half bridge circuit 102 is part of a power converter, the first input terminal VIN1 can be electrically coupled to a power source, and the second input terminal VIN2 can be electrically coupled to ground. The first gate terminal G1 is electrically coupled to a first control terminal CT1 of the IC die 104, which is electrically coupled to a first output terminal O1 of the first driver circuit 106. The second gate terminal G2 is electrically coupled to a second control terminal CT2 of the IC die 104, which is electrically coupled to a second output terminal O2 of the second driver circuit 108. The first driver circuit 106 and second driver circuit 108 may be or include any circuit to selectively drive the respective gate terminal G1, G2 of the switching device 110, 112, including any logic circuit, buffer circuit, or the like.
Integrating first switching device 110 and second switching device 112 on a same IC die 104, versus having each switching device in a standalone die, can reduce the parasitic at the interconnects between first switching device 110 and second switching device 112 (e.g., the switching terminal) and the overall footprint of the half bridge circuit. Also, in some examples, IC die 104 can include multiple first switching devices 110 and second switching devices 112 forming multiple half bridge circuits to support various power converter topologies, such as totem pole topologies, which can further reduce the footprint of such power converter topologies.
While it is advantageous to integrate first switching device 110 and second switching device 112 on the same IC die, the integration can present challenge. For example, the first input terminal VIN1 can receive a high voltage (e.g., 600 V), while the gate terminal G2 of second switching device 112 may receive a low voltage (e.g., 5V) for turning on second switching device 112. The high voltage received by first switching device 110 can propagate through the substrate of IC die 104 to second switching device 112. The high voltage in the substrate may modulate the channel below gate terminal G2, which can prevent or otherwise slow down the switching of second switching device 112. As to be described below, switching circuit 100 can include a conductive back barrier layer to shield second switching device 112 from the high voltage received by first switching device 110, which facilitates the switching of second switching device 112 while first switching device 110 receives a high voltage, and allows first switching device 110 and second switching device 112 to be integrated on a same IC die.
The conductive barrier structure 206 includes a confinement layer and a low bandgap energy material layer. For example, the low bandgap energy material layer may be over the semiconductor substrate 202 and the transition layer(s) 204, and the confinement layer may be over and on the low bandgap energy material layer. The conductive barrier structure 206 (e.g., the confinement layer) is configured to conduct and confine charge carriers within two dimensions. In some examples, the charge carriers that the conductive barrier structure 206 is configured to conduct and confine are holes. A confinement layer may be configured to conduct and confine charge carriers based on band energy bending, which may, at least in part, be a function of materials adjoining the confinement layer. The conductive barrier structure 206 is configured to include a two-dimensional hole gas (2DHG), quantum well, or the like in various examples. The confinement layer and a low bandgap energy material layer may be a repeated unit (e.g., repeated two or more times) in the conductive barrier structure 206, which may form a combination of layers that have a series of 2DHGs and/or 2DEGs, a mini-superlattice structure, or a superlattice structure.
In some examples, the conductive barrier structure 206 includes, e.g., as a confinement layer, an aluminum gallium nitride (AlGaN) layer, an aluminum nitride (AlN) layer, or aluminum indium nitride (AlInN) layer, and includes, e.g., as a low bandgap energy material layer, a gallium nitride (GaN) layer. In examples in which the conductive barrier structure 206 includes a gallium nitride (GaN) layer, the conductive barrier structure 206 may be referred to as a conductive GaN barrier structure 206. Other materials may be implemented for one or more layers of the conductive barrier structure 206.
In some examples, the material of the conductive barrier structure 206 is or includes intrinsic (e.g., undoped) material. In some examples, material(s) of the conductive barrier structure 206 includes a doped material. In some examples, a confinement layer and a low bandgap energy material layer may be doped with carbon, magnesium, or the like. In some examples, a confinement layer may be doped with magnesium, and a low bandgap energy material layer may be doped with carbon. Other dopants may be implemented in the conductive barrier structure 206. A confinement layer may be doped with a uniform dopant concentration or, as described in detail subsequently, may be doped with a lateral dopant gradient concentration (e.g., having a concentration gradient along the x or y axes), to introduce IR drop and charge depletion. Various examples of a conductive barrier structure 206 are described subsequently.
The channel layer 208 is configured, possibly in conjunction with the barrier layer 210, to conduct and confine charge carriers within two dimensions. In some examples, the charge carriers that the channel layer 208 is configured to conduct and confine are electrons. The channel layer 208 is configured to include a two-dimensional electron gas (2DEG) in various examples. More generally, the channel layer 208 is configured to conduct a charge of a first polarity that is opposite from a second polarity of a charge that the conductive barrier structure 206 is configured to conduct. In some examples, the channel layer 208 includes a gallium nitride (GaN) layer and, in such examples, may be referred to as a GaN channel layer 208 or GaN layer 208. In some examples, the material of the channel layer 208 is or includes an unintentionally doped material, such as a material doped by diffusion of dopants from another layer. The barrier layer 210, in some examples, may be or include an aluminum nitride (AlN) layer.
The foregoing description of the semiconductor substrate 202, transition layer(s) 204, conductive barrier structure 206, channel layer 208, and barrier layer 210 applies to subsequent figures in which such components are illustrated. Description of those components like above is omitted for brevity with respect to those subsequent figures.
The first switching device 110 is formed in the first region 212, and the second switching device 112 is formed in the second region 214, and trench 216 can facilitate isolation between first switching device 110 and second switching device 112 by, for example, interrupting the flow of electrons across the channel layer 208 between first switching device 110 and second switching device 112. A first gate layer 220 is over and on an upper surface of the barrier layer 210 in the first region 212 (e.g., the first portion of the barrier layer 210). A second gate layer 222 is over and on an upper surface of the barrier layer 210 in the second region 214 (e.g., the second portion of the barrier layer 210). A first gate barrier layer 224 is over and on the first gate layer 220, and a second gate barrier layer 226 is over and on the second gate layer 222. The gate layers 220, 222 may be or include, in some examples, a p-doped gallium nitride (pGaN) layer. The gate barrier layers 224, 226 may be or include, in some examples, aluminum nitride (AlN). The first gate layer 220, first gate barrier layer 224, and first gate electrical contact 232 form a Schottky contact (e.g., non-ohmic contact) with an underlying layer(s), and the second gate layer 222, second gate barrier layer 226, and second gate electrical contact 234 form a Schottky contact (e.g., non-ohmic contact) with an underlying layer(s).
The first switching device 110 includes a first drain region D1, a first channel region C1, a first source region S1, and a first gate structure G1. The second switching device 112 includes a second drain region D2, a second channel region C2, a second source region S2, and a second gate structure G2. The first gate structure G1 includes the first gate layer 220 and the first gate barrier layer 224. The first channel region C1 is in the channel layer 208 underlying the first gate structure G1. The first channel region C1 is laterally between the first drain region D1 and the first source region S1, which are also in the channel layer 208. The second gate structure G2 includes the second gate layer 222 and the second gate barrier layer 226. The second channel region C2 is in the channel layer 208 underlying the second gate structure G2. The second channel region C2 is laterally between the second drain region D2 and the second source region S2, which are also in the channel layer 208. The first drain region D1, first source region S1, first gate structure G1, second drain region D2, second source region S2, and second gate structure G2 correspond to the first drain terminal D1, first source terminal S1, first gate terminal G1, second drain terminal D2, second source terminal S2, and second gate terminal G2, respectively, of
Although the devices of
In
Also, a first gate electrical contact 232 extends through the first dielectric layer 230 and contacts the first gate barrier layer 224, and a second gate electrical contact 234 extends through the first dielectric layer 230 and contacts the second gate barrier layer 226. A metal line 236 in a first metal layer is over and on the first gate electrical contact 232 and an upper surface of the first dielectric layer 230, and a metal line 238 in the first metal layer is over and on the second gate electrical contact 234 and the upper surface of the first dielectric layer 230. The gate electrical contacts 232, 234 may include one or more metal-barrier and/or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof) conformally in a respective opening through the first dielectric layer 230, and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), the like, or a combination thereof). The metal lines 236, 238 may each include one or more metal-barrier and/or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof) and a bulk metal (e.g., aluminum (Al), copper (Cu), the like, or a combination thereof).
A second dielectric layer 240 is over and on the first dielectric layer 230 and the metal lines 236, 238. The second dielectric layer 240 may include multiple dielectric layers of a same dielectric material or different dielectric materials. For example, the second dielectric layer 240 may include a silicon oxide-based material, such as a PSG, and may further include one or more etch stop layers, such as silicon nitride (SiN) or the like.
A first drain electrical contact 242 extends through the second dielectric layer 240 and first dielectric layer 230 and contacts the barrier layer 210 on the first drain region D1, and a first source electrical contact 244 extends through the second dielectric layer 240 and first dielectric layer 230 and contacts the barrier layer 210 on the first source region S1. A second drain electrical contact 246 extends through the second dielectric layer 240 and first dielectric layer 230 and contacts the barrier layer 210 on the second drain region D2, and a second source electrical contact 248 extends through the second dielectric layer 240 and first dielectric layer 230 and contacts the barrier layer 210 on the second source region S2. Metal lines 252, 254, 256, 258 in a second metal layer are over and on the electrical contacts 242, 244, 246, 248, respectively, and an upper surface of the second dielectric layer 240. The electrical contacts 242, 244, 246, 248 may include one or more metal-barrier and/or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof) conformally in a respective opening through the dielectric layers 230, 240, and a fill metal (e.g., tungsten (W), copper (Cu), aluminum (Al), the like, or a combination thereof). The metal lines 252, 254, 256, 258 may each include one or more metal-barrier and/or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), the like, or a combination thereof) and a bulk metal (e.g., aluminum (Al), copper (Cu), the like, or a combination thereof).
In some examples, the electrical contacts 242, 244, 246, 248 can each include an ohmic contact in direct contact with barrier layer 210. Each ohmic contact can include a Ti/Al-based stack. Each of electrical contacts 242, 244, 246, and 248 may include another metal layer coupled between the ohmic contact and one or more of metal lines 252, 254, 256, and 258. The metal layer may include, for example, Nickel (Ni), gold (Au), TiN, Tungsten Titanium (TiW), a stack of Ti and TiW, etc.
Additional dielectric layers and metal layers may be formed on and over the second dielectric layer 240. The first dielectric layer 230, second dielectric layer 240, additional dielectric layers, first metal layer, second metal layer, and additional metal layers may form an interconnect structure. Metal lines in neighboring metal layers may be electrically coupled by metal vias.
The metal line 252 is electrically coupled to the first input/output terminal of the IC die 104 through the interconnect structure. The metal lines 254, 256 are electrically coupled together through the interconnect structure. The metal line 258 is electrically coupled to the second input/output terminal of the IC die 104 through the interconnect structure.
In the illustrated example of
As shown, the trench 216 separates the first portion of the conductive barrier structure 206 in the first region 212 from the second portion of the conductive barrier structure 206 in the second region 214. The respective portions of the conductive barrier structure 206 decouples the respective portions of the channel layer 208 (e.g., channel regions C1, C2) from the transition layer(s) 204 and semiconductor substrate 202. The respective portions of the conductive barrier structure 206 shield the respective portions of the channel layer 208 (e.g., channel regions C1, C2) from the high voltages in transition layer(s) 204 and semiconductor substrate 202 (collectively parasitic substrate voltages) originating from, for example, VIN1. Specifically, conductive barrier structure 206 can confine charges (e.g., holes). As to be described below, conductive barrier structure 206 can be biased at a particular voltage (e.g., the high voltage from VIN1) using various structures, such as hybrid drain/source contact and gate on barrier layer 210, deep drain contact and other conduction structures that penetrate through channel region 208 and reach conductive barrier structure 206, etc. The bias voltage also experiences an IR drop across conductive barrier structure 206, so that channel layer 208 can be exposed to a reduced voltage. For example, in
In some examples, the implant region 260 can be formed by a deep implantation process. The implant region 260 can have a shorter lateral length (e.g., along the x-axis) than trench 216, which allows shrinking of the pitch of half bridge circuit 200. Reducing the pitch of half bridge circuit 200 can lead to a smaller device footprint and reduced routing parasitic, which is advantageous for high frequency applications such as radio frequency/mm-wave operations. Further, in a case where no trench 216 is formed, the surface of channel region 208 between source electrical contact 244 and drain electrical contact 246 can be more planar, which can facilitate the metallization process to form a metal interconnect between source electrical contact 244 and drain electrical contact 246, such as metal lines 254 and 256.
In some examples, half bridge circuit 200 includes a bias circuit electrically coupled to semiconductor substrate 202 to set its electrical potential. The electrical potential of semiconductor substrate 202 can provide a ground reference for half bridge circuit 200, or for any other circuit that needs the ground reference for proper operation. Having a bias circuit to set the potential of semiconductor substrate 202 can provide a more accurate ground reference voltage.
The monolithic half bridge circuit 300 includes a first injection layer 302 and a second injection layer 304. The first injection layer 302 is over and on the first portion of the barrier layer 210, and more particularly, over the first drain region D1, and the second injection layer 304 is over and on the second portion of the barrier layer 210, and more particularly, over the second drain region D2. A first barrier layer 306 is on and over the first injection layer 302, and a second barrier layer 308 is on and over the second injection layer 304. The injection layers 302, 304 may be or include a same material as the gate layers 220, 222, and the barrier layers 306, 308 may be or include a same material as the gate barrier layers 224, 226.
A first drain electrical contact 310 extends through the first dielectric layer 230 and contacts the barrier layer 210 on the first drain region D1, and a first injection electrical contact 312 extends through the first dielectric layer 230 and contacts the first barrier layer 306. A second drain electrical contact 314 extends through the first dielectric layer 230 and contacts the barrier layer 210 on the second drain region D2, and a second injection electrical contact 316 extends through the first dielectric layer 230 and contacts the second barrier layer 308. The electrical contacts 310, 312, 314, 316 can be or include the same material as described above with respect to the gate electrical contacts 232, 234. A metal line 318 in the first metal layer is over and on the first drain electrical contact 310, the first injection electrical contact 312, and the upper surface of the first dielectric layer 230, and a metal line 320 in the first metal layer is over and on the second drain electrical contact 314, the second injection electrical contact 316, and the upper surface of the first dielectric layer 230. The metal lines 318, 320 may be or include the same material as described above with respect to the metal lines 236, 238.
A first hybrid drain contact includes the first injection layer 302, the first barrier layer 306, the first drain electrical contact 310, the first injection electrical contact 312, and the metal line 318. A second hybrid drain contact includes the second injection layer 304, the second barrier layer 308, the second drain electrical contact 314, the second injection electrical contact 316, and the metal line 320. Although the first injection layer 302 and the first drain electrical contact 310 of the first hybrid drain contact are shown in the same x-z plane of
An electrical contact 322 extends through the second dielectric layer 240 and contacts the metal line 318, and an electrical contact 324 extends through the second dielectric layer 240 and contacts the metal line 320. The electrical contacts 322, 324 may be or include the same material as described above with respect to the source electrical contacts 244, 248. The metal lines 252, 256 in the second metal layer are over and on the electrical contacts 322, 324, respectively, and the upper surface of the second dielectric layer 240.
In the illustrated example of
The conductive barrier structure 206 in
In some examples, the hybrid drain contact can be replaced with a hybrid source contact, where electrical contact 248 is coupled to a barrier layer and an injection layer, and the hybrid source contact is coupled to a ground reference.
The monolithic half bridge circuit 400 includes a first deep drain electrical contact 402 and a second deep drain electrical contact 404. The first deep drain electrical contact 402 extends through the second dielectric layer 240 and the first dielectric layer 230 and, in the first drain region D1, through the barrier layer 210, through the channel layer 208, and into (and possibly, through) the conductive barrier structure 206. In some examples, the first deep drain electrical contact 402 extends at least to contact a confinement layer in the conductive barrier structure 206. The first deep drain electrical contact 402 includes (i) a first conductive structure 402a that extends from the upper surface of the barrier layer 210 into the conductive barrier structure 206 and (ii) a first drain electrical contact portion 402b that extends through the second dielectric layer 240 and the first dielectric layer 230 to the upper surface of the barrier layer 210. The first conductive structure 402a and the first drain electrical contact portion 402b may be formed by separate processes (and hence, may be separate components connected together) to form the first deep drain electrical contact 402, or may be formed by a same process(es) (and hence, may be a unitary component) to form the first deep drain electrical contact 402.
The second deep drain electrical contact 404 extends through the second dielectric layer 240 and the first dielectric layer 230 and, in the second drain region D2, through the barrier layer 210, through the channel layer 208, and into (and possibly, through) the conductive barrier structure 206. In some examples, the second deep drain electrical contact 404 extends at least to contact a confinement layer in the conductive barrier structure 206. The second deep drain electrical contact 404 includes (i) a second conductive structure 404a that extends from the upper surface of the barrier layer 210 into the conductive barrier structure 206 and (ii) a second drain electrical contact portion 404b that extends through the second dielectric layer 240 and the first dielectric layer 230 to the upper surface of the barrier layer 210. The second conductive structure 404a and the second drain electrical contact portion 404b may be formed by separate processes (and hence, may be separate components connected together) to form the second deep drain electrical contact 404, or may be formed by a same process(es) (and hence, may be a unitary component) to form the second deep drain electrical contact 404.
In the illustrated example of
The conductive barrier structure 206 in
The first switching device 510 includes a first source terminal S1 and a first gate terminal G1. The second switching device 512 includes a second source terminal S2 and a second gate terminal G2. The first switching device 510 and the second switching device 512 share a common drain DC. The first source terminal S1 is electrically coupled to a first input/output terminal VIO1 of the IC die 504. The second source terminal S2 is electrically coupled to a second input/output terminal VIO2 of the IC die 504. The first gate terminal G1 is electrically coupled to a first control terminal CT1 of the IC die 504. The second gate terminal G2 is electrically coupled to a second control terminal CT2 of the IC die 504.
The first driver circuit 506 includes a first input/output terminal IO1 and a second output terminal O2. The first input/output terminal IO1 is electrically coupled to the first input/output terminal VIO1 of the IC die 504, and hence to the first source terminal S1. The second output terminal O2 is electrically coupled to the first control terminal CT1 of the IC die 504, and hence to the first gate terminal G1. The second driver circuit 508 includes a third input/output terminal IO3 and a fourth output terminal O4. The third input/output terminal IO2 is electrically coupled to the second input/output terminal VIO2 of the IC die 504, and hence to the second source terminal S2. The fourth output terminal O4 is electrically coupled to the second control terminal CT2 of the IC die 504, and hence to the second gate terminal G2. The first driver circuit 506 and second driver circuit 508 may be or include any circuit to selectively drive the respective gate terminal G1, G2 of the switching device 510, 512, including any logic circuit, buffer circuit, or the like and may be or include any circuit to selectively electrically couple a respective source terminal S1, S2 to the respective gate terminal G1, G2. Driver circuits 506 and 508 can set the respective first switches 510 and 512 in the same state (e.g., on state, off state), or in different states (e.g., one in the on state and the other in the off state) to support various applications including alternating current (AC) signals, such as rectifier circuits (e.g., Vienna rectifier, direct matrix converter for AC-AC motor drive, etc.)
A first gate layer 602 is over and on an upper surface of the barrier layer 210, and a second gate layer 604 is over and on an upper surface of the barrier layer 210. A first gate barrier layer 606 is over and on the first gate layer 602, and a second gate barrier layer 608 is over and on the second gate layer 604. The gate layers 602, 604 may be like the gate layers 220, 222 of
The first switching device 510 includes a first source region S1, a first channel region C1, a common drain region DC, and a first gate structure G1. The second switching device 112 includes a second source region S2, a second channel region C2, the common drain region DC, and a second gate structure G2. The first gate structure G1 includes the first gate layer 602 and the first gate barrier layer 606. The first channel region C1 is in the channel layer 208 underlying the first gate structure G1. The first channel region C1 is laterally between the first source region S1 and the common drain region DC, which are also in the channel layer 208. The second gate structure G2 includes the second gate layer 604 and the second gate barrier layer 608. The second channel region C2 is in the channel layer 208 underlying the second gate structure G2. The second channel region C2 is laterally between the second source region S2 and the common drain region DC, which are also in the channel layer 208. The common drain region DC is laterally between (i) the first gate structure G1 and first channel region C1 and (ii) the second gate structure G2 and second channel region C2. The first source region S1, first gate structure G1, common drain region DC, second source region S2, and second gate structure G2 correspond to the first source terminal S1, first gate terminal G1, common drain DC, second source terminal S2, and second gate terminal G2, respectively, of
A first dielectric layer 610 is over and on the barrier layer 210 and gate barrier layers 606, 608 and along sidewalls of the gate layers 602, 604 and gate barrier layers 606, 608. The first dielectric layer 610 may be like the first dielectric layer 230 of
A second dielectric layer 620 is over and on the first dielectric layer 610 and the metal lines 616, 618. The second dielectric layer 620 may be like the second dielectric layer 240 of
Additional dielectric layers and metal layers may be formed on and over the second dielectric layer 620. The first dielectric layer 610, second dielectric layer 620, additional dielectric layers, first metal layer, second metal layer, and additional metal layers may form an interconnect structure. Metal lines in neighboring metal layers may be electrically coupled by metal vias.
The metal line 626 is electrically coupled to the first input/output terminal VIO1 of the IC die 504 through the interconnect structure. The metal line 628 is electrically coupled to the second input/output terminal VIO2 of the IC die 504 through the interconnect structure. The metal line 616 is electrically coupled to the first control terminal CT1 of the IC die 504 through the interconnect structure. The metal line 618 is electrically coupled to the second control terminal CT2 of the IC die 504 through the interconnect structure.
In operation, in conjunction with
To set switching devices 510, 512 in the off state, the respective driver circuit 506, 508 set the voltages at the respective gate terminal G1, G2 (e.g., gate structure G1, G2) to be equal to the voltages of the corresponding respective source terminal S1, S2 (e.g., source region S1, S2, and terminals IO1/IO2), so that the respective gate-to-source voltages (VGS) of switching devices 510 and 512 become zero. Also, with a source terminal (e.g., S1 or S2, or both) at a high voltage, the corresponding gate structure (e.g., G1 or G2, or both) can be driven to that high voltage to set the switch in the off state, and to inject charge carriers (e.g., holes) into the conductive barrier structure 206. The high voltage at the gate terminal can also propagate through barrier layer 210 and channel layer 208 (and experiencing an IR drop along the way) and reach conductive barrier structure 206. The reduced voltage can provide a bias voltage for conductive barrier structure 206. As an example, assume that the first input/output terminal VIO1 is at a high voltage (e.g., 600 V), that the first source region S1 is electrically coupled to the first gate structure G1 (e.g., VG1S1=0V) such that the first switching device 510 is in an off state, and that the voltage difference between the second source region S2 and the second gate structure G2 is 5V (e.g., VG2S2=5V) such the second switching device 512 is in an on state. Under such conditions, the first gate structure G1 is driven to inject holes into the conductive barrier structure 206.
The conductive barrier structure 206 in
The monolithically integrated bidirectional switch 700 includes a conductive structure 702 extending from an upper surface of the barrier layer 210 into (and possibly, through) the conductive barrier structure 206 in the common drain region DC. In some examples, the conductive structure 702 extends at least to contact the channel layer 208 and a confinement layer in the conductive barrier structure 206, thereby electrically coupling the channel layer 208 and the confinement layer. In some examples, the conductive structure may further extend through the first dielectric layer 610, and in further examples, may further extend through the second dielectric layer 620 and the first dielectric layer 610 (similar to a deep drain electrical contact of
The third switching device 816 includes a first source terminal S1, a first gate terminal G1, and a first body terminal B1. The fourth switching device 818 includes a second source terminal S2, a second gate terminal G2, and a second body terminal B2. The third switching device 816 and the fourth switching device 818 share a common drain DC. The first source terminal S1 is electrically coupled to a first input/output terminal VIO1 of the IC die 804. The second source terminal S2 is electrically coupled to a second input/output terminal VIO2 of the IC die 804. The first gate terminal G1 is electrically coupled to a first control terminal CT1 of the IC die 804. The second gate terminal G2 is electrically coupled to a second control terminal CT2 of the IC die 804. The first body terminal B1 is electrically coupled to a first body injection terminal BI1 of the IC die 804. The second body terminal B2 is electrically coupled to a second body injection terminal BI2 of the IC die 804.
The first driver circuit 806 includes a first input/output terminal IO1 and a second output terminal O2. The first input/output terminal IO1 is electrically coupled to the first input/output terminal VIO1 of the IC die 804, and hence to the first source terminal S1. The second output terminal O2 is electrically coupled to the first control terminal CT1 of the IC die 804, and hence to the first gate terminal G1. The second driver circuit 808 includes a third input/output terminal IO3 and a fourth output terminal O4. The third input/output terminal IO3 is electrically coupled to the second input/output terminal VIO2 of the IC die 804, and hence to the second source terminal S2. The fourth output terminal O4 is electrically coupled to the second control terminal CT2 of the IC die 804, and hence to the second gate terminal G2. The first driver circuit 806 and second driver circuit 808 may be or include any circuit to selectively drive the respective gate terminal G1, G2 of the switching device 816, 818, including any logic circuit, buffer circuit, or the like and may be or include any circuit to selectively electrically couple a respective source terminal S1, S2 to the respective gate terminal G1, G2.
The first switching device 812 includes a first source/drain terminal SD1, a third gate terminal G3, and a second source/drain terminal SD2. The second switching device 814 includes a third source/drain terminal SD3, a fourth gate terminal G4, and a fourth source/drain terminal SD4. The first source/drain terminal SD1 is electrically coupled to the first input/output terminal VIO1 of the IC die 804, and hence, further to the first source terminal S1. The second source/drain terminal SD2 is electrically coupled to the first body injection terminal BI1 of the IC die 804. The third gate terminal G3 is electrically coupled to a third output terminal O3 of the selection circuit 810. The third source/drain terminal SD3 is electrically coupled to the second input/output terminal VIO2 of the IC die 804, and hence, further to the second source terminal S2. The fourth source/drain terminal SD4 is electrically coupled to the second body injection terminal BI2 of the IC die 804. The fourth gate terminal G4 is electrically coupled to a fourth output terminal O4 of the selection circuit 810. The selection circuit 810 may be or include any circuit to selectively drive the respective gate terminal G3, G4 of the switching device 812, 814, including any logic circuit, buffer circuit, or the like.
A first gate layer 912 is over and on an upper surface of the first portion of the barrier layer 210, and a second gate layer 914 is over and on an upper surface of the first portion of the barrier layer 210. A first gate barrier layer 916 is over and on the first gate layer 912, and a second gate barrier layer 918 is over and on the second gate layer 914. The gate layers 912, 914 may be like the gate layers 220, 222 of
The third switching device 816 includes a first source region S1, a first channel region C1, a common drain region DC, a first gate structure G1, and a first body region B1. The fourth switching device 818 includes a second source region S2, a second channel region C2, the common drain region DC, a second gate structure G2, and a second body region B2. The first gate structure G1 includes the first gate layer 912 and the first gate barrier layer 916. The first channel region C1 is in the first portion of the channel layer 208 underlying the first gate structure G1. The first channel region C1 is laterally between the first source region S1 and the common drain region DC, which are also in the first portion of the channel layer 208. The second gate structure G2 includes the second gate layer 914 and the second gate barrier layer 918. The second channel region C2 is in the first portion of the channel layer 208 underlying the second gate structure G2. The second channel region C2 is laterally between the second source region S2 and the common drain region DC, which are also in the first portion of the channel layer 208. The common drain region DC is laterally between (i) the first gate structure G1 and first channel region C1 and (ii) the second gate structure G2 and second channel region C2. The first body region B1 is in the conductive barrier structure 206 in the first region 902 (e.g., underlying the common drain region DC, the first channel region C1, and the first source region S1) and extends into the second region 904. The second body region B2 is in the conductive barrier structure 206 in the first region 902 (e.g., underlying the common drain region DC, the second channel region C2, and the second source region S2) and extends into the third region 906. The first source region S1, first gate structure G1, first body region B1, common drain region DC, second source region S2, second gate structure G2, and second body region B2 correspond to the first source terminal S1, first gate terminal G1, first body terminal B1, common drain DC, second source terminal S2, second gate terminal G2, and second body terminal B2, respectively, of
A first dielectric layer 920 is over and on the barrier layer 210 and gate barrier layers 916, 918 and along sidewalls of the gate layers 912, 914 and gate barrier layers 916, 918. The first dielectric layer 920 also fills the trenches 908, 910 and contacts sidewalls of the barrier layer 210 and channel layer 208 and an upper surface of the conductive barrier structure 206 that define the trenches 908, 910. In some examples, a different dielectric material may fill the trenches 908, 910, such as in a STI. The first dielectric layer 920 may be like the first dielectric layer 230 of
A second dielectric layer 930 is over and on the first dielectric layer 920 and the metal lines 926, 928. The second dielectric layer 930 may be like the second dielectric layer 240 of
Additional dielectric layers and metal layers may be formed on and over the second dielectric layer 930. The first dielectric layer 920, second dielectric layer 930, additional dielectric layers, first metal layer, second metal layer, and additional metal layers may form an interconnect structure. Metal lines in neighboring metal layers may be electrically coupled by metal vias.
The metal line 940 is electrically coupled to the first input/output terminal VIO1 of the IC die 804 through the interconnect structure. The metal line 942 is electrically coupled to the second input/output terminal VIO2 of the IC die 804 through the interconnect structure. The metal line 926 is electrically coupled to the first control terminal CT1 of the IC die 804 through the interconnect structure. The metal line 928 is electrically coupled to the second control terminal CT2 of the IC die 804 through the interconnect structure. The metal line 944 is electrically coupled to the first body injection terminal BI1 of the IC die 804 through the interconnect structure. The metal line 946 is electrically coupled to the second body injection terminal BI2 of the IC die 804 through the interconnect structure.
In operation, in conjunction with
The conductive barrier structure 206 in
The bidirectional switching device 1002 includes a first source terminal S1, a second source terminal S2, a gate terminal G1, and a body B1. The first source terminal S1 is electrically coupled to a first input/output terminal VIO1 of the IC die 1004. The second source terminal S2 is electrically coupled to a second input/output terminal VIO2 of the IC die 1004. The gate terminal G1 is electrically coupled to a control terminal CT1 of the IC die 1004 and to the body B1.
The driver circuit 1006 includes a first input/output terminal IO1, a second input/output terminal IO2, and a third output terminal O3. The first input/output terminal IO1 is electrically coupled to the first input/output terminal VIO1 of the IC die 1004, and hence to the first source terminal S1. The second input/output terminal IO2 is electrically coupled to the second input/output terminal VIO2 of the IC die 1004, and hence to the second source terminal S2. The third output terminal O3 is electrically coupled to the control terminal CT1 of the IC die 1004, and hence to the first gate terminal G1. The driver circuit 1006 may be or include any circuit to selectively drive the gate terminal G1 of the bidirectional switching device 1002, including any logic circuit, buffer circuit, or the like and may be or include any circuit to selectively electrically couple a respective source terminal S1, S2 to the gate terminal G1.
A gate layer 1102 is over and on an upper surface of the barrier layer 210. A gate barrier layer 1104 is over and on the gate layer 1102. The gate layer 1102 may be like the first gate layer 220 of
A first dielectric layer 1110 is over and on the barrier layer 210 and gate barrier layer 1104 and along sidewalls of the gate layer 1102 and gate barrier layer 1104. The first dielectric layer 1110 may be like the first dielectric layer 230 of
A second dielectric layer 1120 is over and on the first dielectric layer 1110 and the metal line 1116. The second dielectric layer 1120 may be like the second dielectric layer 240 of
Additional dielectric layers and metal layers may be formed on and over the second dielectric layer 1120. The first dielectric layer 1110, second dielectric layer 1120, additional dielectric layers, first metal layer, second metal layer, and additional metal layers may form an interconnect structure. Metal lines in neighboring metal layers may be electrically coupled by metal vias.
The metal line 1126 is electrically coupled to the first input/output terminal VIOL of the IC die 1004 through the interconnect structure. The metal line 1128 is electrically coupled to the second input/output terminal VIO2 of the IC die 1004 through the interconnect structure. The metal line 1116 is electrically coupled to the control terminal CT1 of the IC die 1004 through the interconnect structure.
The monolithically integrated bidirectional switch 1100 of
The conductive barrier structure 206 in
In the example shown in
The deep electrical contact 1400 extends through a second dielectric layer 1420, a first dielectric layer 1410, the barrier layer 210, and the channel layer 208 and into (and possibly, through) the conductive barrier structure 206 (e.g., contacting a confinement layer). The deep electrical contact 1400 includes (i) a conductive structure 1402 that extends from the upper surface of the barrier layer 210 into the conductive barrier structure 206 and (ii) an electrical contact portion 1404 that extends through the second dielectric layer 1420 and the first dielectric layer 1410 to the upper surface of the barrier layer 210. A lateral dimension 1412 of the conductive structure 1402 along a first lateral direction (e.g., a y-direction) is less than a lateral dimension 1414 of the electrical contact portion 1404 along a second lateral direction (e.g., a y-direction) parallel to the first lateral direction. The electrical contact portion 1404 therefore may be considered as having a flange portion that extends laterally beyond the conductive structure 1402. The electrical contact portion 1404 contacts the upper surface of the barrier layer 210 because the lateral dimension 1414 is greater than the lateral dimension 1412. The conductive structure 1402 and the electrical contact portion 1404 may be formed by separate processes (and hence, may be separate components connected together) to form the deep electrical contact 1400, or may be formed by a same process(es) (e.g., a damascene process) (and hence, may be a unitary component) to form the deep electrical contact 1400.
In some examples, the low bandgap energy material layer 1602 is or includes gallium nitride (GaN), and the confinement layer 1604 is or includes an aluminum gallium nitride (AlGaN) layer, an aluminum nitride (AlN) layer, or aluminum indium nitride (AlInN) layer. In some examples, the layers 1602, 1604 may each be undoped. In some examples, the low bandgap energy material layer 1602 and confinement layer 1604 may each be doped, such as by a p-type dopant, such as carbon (C), magnesium (Mg), or the like. In some examples, one of the low bandgap energy material layer 1602 and confinement layer 1604 may be doped, while the other of the low bandgap energy material layer 1602 and confinement layer 1604 may be undoped. The confinement layer (or conductive barrier structure 206) can be formed by epitaxial growth on the silicon substrate 202, followed by doping (e.g., diffusion, implantation, etc.) in some examples.
In some examples, the confinement layer 1604 is p-doped with a lateral dopant gradient concentration.
In some examples, the low bandgap energy material layers 1902, 1906 each is or includes gallium nitride (GaN), and the confinement layers 1904, 1908 is or includes an aluminum gallium nitride (AlGaN) layer, an aluminum nitride (AlN) layer, or aluminum indium nitride (AlInN) layer. In some examples, the layers 1902, 1904, 1906, 1908 may each be undoped. In some examples, the low bandgap energy material layers 1902, 1906 and confinement layers 1904, 1908 may each be doped, such as by a p-type dopant, such as carbon (C), magnesium (Mg), or the like. In some examples, some of the layers 1902, 1904, 1906, 1908 may be doped, while some others of the layers 1902, 1904, 1906, 1908 may be undoped. Doping may be with a uniform dopant concentration or with a lateral dopant gradient concentration, as described above.
In this description, the term “couple” may cover connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action: (a) in a first example, device A is coupled to device B by direct connection; or (b) in a second example, device A is coupled to device B through intervening component C if intervening component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via the control signal generated by device A.
Also, in this description, the recitation “based on” means “based at least in part on.” Therefore, if X is based on Y, then X may be a function of Y and any number of other factors.
A device that is “configured to” perform a task or function may be configured (e.g., programmed and/or hardwired) at a time of manufacturing by a manufacturer to perform the function and/or may be configurable (or reconfigurable) by a user after manufacturing to perform the function and/or other additional or alternative functions. The configuring may be through firmware and/or software programming of the device, through a construction and/or layout of hardware components and interconnections of the device, or a combination thereof.
As used herein, the terms “terminal”, “node”, “interconnection”, “pin” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean an interconnection between or a terminus of a device element, a circuit element, an integrated circuit, a device or other electronics or semiconductor component.
A circuit or device that is described herein as including certain components may instead be adapted to be coupled to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors, and/or inductors), and/or one or more sources (such as voltage and/or current sources) may instead include only the semiconductor elements within a single physical device (e.g., a semiconductor die and/or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and/or the sources to form the described structure either at a time of manufacture or after a time of manufacture, for example, by an end-user and/or a third-party.
While the use of particular transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, a field effect transistor (“FET”) (such as an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT—e.g., NPN transistor or PNP transistor), an insulated gate bipolar transistor (IGBT), and/or a junction field effect transistor (JFET) may be used in place of or in conjunction with the devices described herein. The transistors may be depletion mode devices, drain-extended devices, enhancement mode devices, natural transistors or other types of device structure transistors. Furthermore, the devices may be implemented in/over a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN) or a gallium arsenide substrate (GaAs).
References may be made in the claims to a transistor's control input and its current terminals. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.
References herein to a FET being “on” or “enabled” means that the conduction channel of the FET is present and drain current may flow through the FET. References herein to a FET being “off” or “disabled” means that the conduction channel is not present so drain current does not flow through the FET. An “off” FET, however, may have current flowing through the transistor's body-diode.
Circuits described herein are reconfigurable to include additional or different components to provide functionality at least partially similar to functionality available prior to the component replacement. Components shown as resistors, unless otherwise stated, are generally representative of any one or more elements coupled in series and/or parallel to provide an amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may instead be multiple resistors or capacitors, respectively, coupled in series between the same two nodes as the single resistor or capacitor.
While certain elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all of the features illustrated as being external to the integrated circuit may be included in the integrated circuit and/or some features illustrated as being internal to the integrated circuit may be incorporated outside of the integrated. As used herein, the term “integrated circuit” means one or more circuits that are: (i) incorporated in/over a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated into the same module; and/or (iv) incorporated in/on the same printed circuit board.
Uses of the phrase “ground” in the foregoing description include a chassis ground, an Earth ground, a floating ground, a virtual ground, a digital ground, a common ground, and/or any other form of ground connection applicable to, or suitable for, the teachings of this description.
In this description, unless otherwise stated, “about,” “approximately” or “substantially” preceding a parameter means being within +/−10 percent of that parameter or, if the parameter is zero, a reasonable range of values around zero.
Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.
Although various examples have been described in detail, it should be understood that various changes, substitutions, and alterations can be made therein without departing from the scope defined by the appended claims.
This application is a continuation-in-part of U.S. application Ser. No. 18/326,698, titled “INTEGRATED DEVICES WITH CONDUCTIVE BARRIER STRUCTURE”, filed on May 31, 2023, the entirety of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 18326698 | May 2023 | US |
| Child | 18534056 | US |
