Claims
- 1. An integrated test circuit in an integrated circuit (1) for testing a plurality of internal voltages (V0, V1, V2, . . . Vn) of the integrated circuit, comprising:
a switching device (4) configured to select one of the internal voltages (V0, V1, V2, . . . Vn) in accordance with a selection signal for the purpose of testing; a reference voltage terminal for inputting a reference voltage from an external device; and a comparator device (5) configured to compare a measurement voltage, corresponding to the selected internal voltage (V0, V1, V2, . . . Vn), with the externally provided reference voltage and in order to output an error signal as a result of the comparison.
- 2. The test circuit of claim 1, wherein the corresponding measurement voltage equals the selected internal voltage and the reference voltage provided by the external device is different for each selected internal voltage.
- 3. The test circuit of claim 1, further comprising a voltage divider for at least one internal voltage to be tested, in order to generate the measurement voltage as a predetermined fraction of the internal voltage to be tested.
- 4. The test circuit of claim 1, further comprising a voltage divider for each of the internal voltages, the voltage dividers being configured so that the measurement voltage corresponding to the respective internal voltage has the same potential at each voltage divider.
- 5. The test circuit of claim 4, wherein the reference voltage used to test each internal voltage is the same for each internal voltage.
- 6. The test circuit of claim 1, further comprising a control circuit configured to selectively connect each one of the plurality of voltage dividers to the comparator device.
- 7. An integrated test circuit in an integrated circuit for testing a plurality of internal voltages of the integrated circuit, comprising:
a switching device (4) configured to select one of the internal voltages (V0, V1, V2, . . . Vn) in accordance with a selection signal; a comparator device (5) configured to compare a measurement voltage, corresponding to the selected internal voltage (V0, V1, V2, . . . Vn), with an externally provided reference voltage (Vref) and in order to output an error signal as a result of the comparison; and a storage element in communication with the comparator device to store the error signal.
- 8. The test circuit of claim 7, wherein the switching device is a multiplexer.
- 9. The test circuit of claim 7, further comprising a voltage divider for each of the internal voltages, the voltage dividers being configured so that the measurement voltage corresponding to the respective internal voltage has the same potential at each voltage divider.
- 10. The test circuit of claim 7, further comprising a signal terminal and a switching element operable to selectively connect the signal terminal to the storage element, whereby the error signal may be read out by an external device connected to the signal terminal.
- 11. The test circuit of claim 10, wherein the switching element is further operable to selectively connect the comparator device to the signal terminal to apply the reference voltage to the comparator device.
- 12. The test circuit of claim 11, wherein the switching element is further operable to selectively connect the signal terminal to an internal input/output signal line of the integrated circuit.
- 13. The test circuit of claim 12, further comprising a control circuit configured to issue test control signals to the switching device and the switching element.
- 14. A method for testing an integrated circuit using an on-board test circuit integrated with integrated circuit, comprising:
(a) selecting an internal voltage of a plurality of internal voltages of the integrated circuit; (b) receiving a reference voltage from an external source connected to a signal terminal of the on-board test circuit; (c) comparing a measurement voltage corresponding to the selected internal voltage with the reference voltage; (d) outputting an error signal as the result of the comparison; and (e) repeating (a)-(d) for each of the plurality of internal voltages.
- 15. The method of claim 14, further comprising dividing the selected internal voltage to generate the measurement voltage as a predetermined fraction of the selected internal voltage.
- 16. The method of claim 14, wherein the dividing is done by a plurality of dividers, one divider corresponding to each internal voltage; and wherein the voltage dividers are configured so that the respective measurement voltage has the same potential at each voltage divider.
- 17. The method of claim 14, wherein the comparing is done by a comparator device.
- 18. The method of claim 14, further comprising storing the error signal in a storage element.
- 19. The method of claim 18, further comprising selectively connecting the signal terminal to the storage element, whereby the error signal may be read out by an external reading device.
- 20. The method of claim 18, further comprising alternatively connecting the signal terminal to the storage element and a comparator device which receives the reference voltage as input.
- 21. The method of claim 18, further comprising:
during a test mode, alternatively connecting the signal terminal to the storage element and a comparator device which receives the reference voltage as input; and during an operation mode, connecting the signal terminal to an internal input/output signal line of the integrated circuit.
- 22. The method of claim 18, further comprising issuing control signals from a control circuit of the on-board test circuit to a selector device responsive to the control signals to selectively connect the signal terminal to one of:
the storage element; a comparator device which receives the reference voltage as input; and an internal input/output signal line of the integrated circuit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
103 06 620.9-35 |
Feb 2003 |
DE |
|
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims foreign priority benefits under 35 U.S.C. §119 to co-pending German patent application number 103 06 620.9-35, filed Feb. 18, 2003. This related patent application is herein incorporated by reference in its entirety.