The invention is directed, in general, to semiconductor devices, and more specifically, multi-gate devices and their method of manufacture.
As the dimensions of semiconductor devices, e.g., field effect transistors (FET), continue to decrease, it is increasingly difficult to deal with short channel effects, increased on-currents, current leakage and threshold voltage control. For planar single-gate transistor devices, in addition to the gate controlling the channel, fringe fields from the source, drain or substrate also can affect the channel. These fringe fields can lower the threshold voltage and cause drain-induced barrier lowering, which in turn, increases the leakage current of the transistor. In addition, coupling between the source and channel degrades the sub-threshold current such that the ratio of the drive current when the device in the on-state (Ion), versus the sub-threshold current when the device is in the off-state (Ioff), is lowered.
Multi-gate devices provide improved control of the channel, and thus superior Ion:Ioff ratio relative to planar single-gate transistor structures. Nevertheless, there are challenges to overcome if multi-gate devices are to be used in a broad range of application in integrated circuits. Typically, for ease of fabrication and uniformity of optimized transistor characteristics, the dimensions of all the multi-gate devices in a circuit are the same. This choice, however, can compromise the performance of multi-gate devices intended for specialized applications, such delivering a high drive current (e.g., high Ion), or operating with a low leakage current (e.g., low Ioff).
Accordingly, what is needed is a multi-gate device, and its method of manufacture, that addresses the drawbacks of the prior art methods and devices.
The invention provides a semiconductor device, comprising a first multi-gate device and second multi-gate device on a semiconductor substrate. The first multi-gate device comprises a first gate structure and the second multi-gate a second gate structure. An effective width of the first gate structure is greater than an effective width of the second gate structure.
Another embodiment is an integrated circuit. The integrated circuit comprises the above-described first and second multi-gate devices. Fins of a first channel region of the first multi-gate device are taller than fins of a second channel region of the second multi-gate device, thereby causing the effective width of the first gate structure to be greater than the effective width of the second gate structure.
Another embodiment comprises a method of manufacturing the above-described semiconductor device. Forming the first and second multi-gate devices comprises forming first and second channel regions and enclosing the channel regions with first and second gate structures, respectively, such that the effective width of the first gate structure is greater than an effective width of the second gate structure.
FIGS. 4 to 13 illustrate cross-section views of selected steps in an example method of manufacturing a semiconductor device of the invention.
It has been found that by constructing multi-gate devices having different Weff in the same integrated circuit, the operating characteristics of devices for specific applications can be improved. The drive current and leakage current of a multi-gate device can be tailored by adjusting the effective gate width (Weff) of individual multi-gate devices. E.g., for high power applications, by increasing the height of the fins of the channel region, the effective gate width (Weff) is increased, thereby increasing the Ion. For low power, low leakage current applications, decreasing the height of the fins decreases Weff, thereby reducing Ioff. Additionally, the reduction in Ioff is a result of a stronger top gate control of the channel region at shorter gate lengths.
Constructing such multi-gate devices in the same circuit can be problematic. Performing photolithography on a semiconductor substrate having two or more segments with different heights is a serious obstacle to device manufacturability. In particular, having segments on a substrate with different heights present depth-of-focus problems for photolithography. It can be difficult to e.g., define a channel region comprising fins that are separated from each other by a pitch that is at, or near, the limits of photolithograph resolution. The invention also provides a method of manufacturing multi-gate devices that avoids the need to perform photolithography on different heights.
One aspect of the invention is a semiconductor device having multi-gate devices with differing Weff.
The first multi-gate device 105 has a first channel region 120 enclosed by a first gate structure 122. The second multi-gate device 110 has a second channel region 125 enclosed by a second gate structure 127. The term multi-gate device as used herein refers to a semiconductor device comprising a channel region made of one or more raised portions (e.g. fins) that are enclosed on at least two sides by a gate structure.
Double-gate is one form of multi-gate in which the gate structure comprises two gates, one each on opposing sides of the channel region. Tri-gate is another form of multi-gate. In tri-gate, the gate structure comprises three gates, two on opposing sides of the channel region and one (e.g., a top gate) adjacent to the two opposing gate. Those skilled in the art would be familiar with other configurations of multi-gate devices such as omega-gates or pi-gates.
The term, Weff, the effective width of the gate, as used herein refers to the total distance of gate structure lying between the source and drain of a multi-gate device. E.g., for a tri-gate whose channel region comprises a single fin, Weff equals about two times the height of fin plus the fin's lateral thickness. If the channel region comprises more than one fin, then Weff equals the sum of two times the height of each fin plus each fin's lateral thickness.
As shown in
The maximum amount of Ion that a multi-gate device can operate at is directly proportional to the device's Weff. When the multi-gate device is used to transmit a high Ion, then it is desirable to increase Weff. The minimum amount of Ioff that a multi-gate device can operate at is inversely proportional to the device's Weff. When multi-gate device is operated at a low Ioff, then it is desirable to decrease Weff.
Consider when the first multi-gate device 105 is designed to transmit a higher Ion than the second multi-gate device 107. It is preferable for the Weff 130 of the first gate structure 122 to be greater than the Weff 140 of the second gate structure 127. In some cases the Weff 130 for the first gate structure 122 is at least about 1.3 times (30%) greater than the Weff 140 of the second gate structure 127. This can be desirable for e.g., static random access memory (SRAM) cells, where a pMOS multi-gate FET (e.g., the second multi-gate device 107) is designed to operate at a lower Ion than an nMOS FET (e.g., the first multi-gate device 105). A low Beta ratio, (e.g., an Ion (nMOS)/Ion (pMOS) ratio of about 1 or less) can be cause problems with memory access during the write cycle of SRAM cells. Therefore in some preferred embodiment to keep the Beta ratio greater than 1.0, and more preferably 1.5 or greater, Weff 130 is at least about 2 times (100%) greater than Weff 140. This configuration can be especially desirable when one or more transistor is used in a high power application to transmit a signal to e.g., a remote location on an integrated circuit, or to an array of SRAM cells.
Weff can be increased or decreased by adjusting the number of fins of the channel region or the lateral thickness of each fin. To minimize short channel effects and maximize Ion, it is desirable to form the maximum number fins in the area of substrate available for the device, by e.g., minimizing the lateral thickness 134, 144 of each fin and minimizing a gap 210 between the fins. In some embodiments, the number of fins, a fin-to-fin pitch 215, or both, are made constant for several, and in some cases all, of the multi-gate devices 105, 107 of the semiconductor device 100.
The dimensions of the fins may be constrained by factors other than the target Ion or Ioff. To retain the improvements over short channel effects compared to planar single-gate transistors, it is desirable for the ratio of the height 132, 142 to lateral thickness 134, 144 of the fins 136, 146 to be equal to or greater than 1:1. To avoid the formation of fragile fins, it advantageous for the height-to-lateral-thickness ratio for each fin to be less than 10:1. For the same reason, it is beneficial for the each fin's lateral thickness 134, and length 220, 225 covered by the gate 122, 127 (
In some cases it is preferable to adjust Weff, and hence Ion and Ioff, without having to alter the number of fins or pitch 215 between fins, because the these features may already be optimized to decrease short-channel effects. In such cases, preferably only the fin heights are altered to accomplish a change in Weff for one multi-gate device versus another multi-gate device. In some cases, the height 132 of the fins 135 of the first channel region 120 is defined by a target Ion and Ioff for the first multi-gate device 105, and a height 142 of the fins 146 of the second channel region 125 is defined by a different target Ion and Ioff for the second multi-gate device 107.
For the example device 100, a greater Weff 130, and hence greater Ion, of the first multi-gate device 105, compared to the Weff 140 of the second multi-gate device 107 can be due to a greater height 132 of the first-fins 136 as compared to the height 142 of the second-fins 146. E.g., to achieve an about 30 percent greater Ion in the first multi-gate device 105 compared to the second multi-gate device 107, the height 132 of the first-fins 136 is preferably at least about 10 percent greater than the height 142 of the second-fins 146.
Consider when a target Ion for the first multi-gate transistor device 105 is greater than or equal to about 1.5 mA per micron of a lateral dimension 230 of the substrate 110 occupied by the first channel region 120. At a 32-nanometer technology node, such an Ion is considered to be a high drive current. In some cases, each of the first-fins 136 of the channel region 120 can have a first height 132 ranging from about 20 to 60 nanometers and a first lateral thickness 134 ranging from about 10 to 20 nanometers. Even more preferably, a ratio of the height 132 to thickness 134 ranges from about 3:1 to 6:1, with the upper ratio limited by manufacturability of the fins.
Consider when a target Ioff for the second multi-gate transistor device 107 is less than or equal to about 0.1 nA per micron of a lateral dimension 235 of the substrate 110 occupied by the second channel region 125. E.g., at a 32-nanometer technology node, such an Ioff is considered to be a low leakage current. In such cases, preferred embodiments of the second-fins 146 each have a second height 132 ranging from about 10 nanometers to 20 nanometers and a second lateral thickness 144 ranging from about 10 to 20 nanometers. Even more preferably, a ratio of the height 142 to thickness 144 ranges from about 1:1 to 3:1, and more preferably, about 1:1 to 2:1. One skilled in the art would understand that these dimensions, as well as the Ion and Ioff values that are considered to be high and low currents, would vary according to the technology node of interest.
In some preferred embodiments, the substrate 110 comprises an SOI substrate, and the fins 136, 146 of the channel regions 120, 125 are formed from a silicon layer 112 of the SOI substrate. As shown in
In some cases, the fins 136, 146 of the first and second channel regions 120, 125 each have a long lateral axis 250 (
In other cases, however, the long lateral axis 250 of the fins 136, 146 is aligned with an (100) orientation plane of the silicon layer 112. This is desirable when both multi-gate devices 105, 107 are configured as either pMOS or nMOS transistors in e.g., a SRAM cell. The multi-gate devices 105, 107 configured as nMOS transistors are designed to operate at a higher Ion than the multi-gate devices 105, 107 configured as pMOS transistors.
In other cases, however, the higher Ion for the nMOS multi-gate transistors can be achieved solely by increasing the Weff of these transistors, as compared to the pMOS multi-gate transistors. This eliminates the need for the long axis 250 of the fins 136, 146 to be aligned with an (100) orientation plane of the layer 112. Having the long lateral axis 220 of the fins of the multi-gate devices in SRAM cells to be constructed in alignment with the same (e.g., (110)) orientation plane as other multi-gate devices located in other areas of the semiconductor device 100 (e.g., area for logic or high power circuits) can advantageously simplify device construction.
In some embodiments, the semiconductor device is configured as an integrated circuit.
As shown in
The integrated circuit 300 further includes one or more dielectric layers 310, 315, 320 located over the multi-gate devices 105, 107 and interconnects 330, 335, 340 formed in and over the dielectric layers 310, 315, 320. The interconnects electrically couple the multi-gate device 105, 107 to each other, other multi-gate devices, or planar-single transistors 350, to complete the circuit. One or more of the multi-gate devices 105, 107 can comprise transistors in any or all of logic circuits, such as a complementary metal oxide semiconductor (CMOS) circuits, SRAM cells, higher power circuits or other conventional circuits used in integrated circuits.
Another aspect of the invention is a method of manufacturing a semiconductor device. Any of the above-described embodiments of devices discussed in the context of
The method comprises forming first and second multi-gate devices on a semiconductor substrate. Forming the devices comprises multi-gate devices forming first and second channel regions. Preferably forming the first and second channel regions comprises forming one or more fins from the substrate.
In some preferred embodiments, the epitaxial silicon layer 610 is deposited such that its thickness 620 plus the thickness 410 of the silicon layer 112 is substantially equal to a height of one or more fins of a channel region. E.g., the total thickness 630 of these two layers 112, 610 equals the height 132 of the first fins 136. In other cases, if e.g., excessive quantities of epitaxial material are deposited, the layer's thickness 620 can be reduced to substantially equal the thickness 525 of the hardmask 520 (
Other embodiments of the method can include variations in the above-described processes to form the channel regions 120, 125. For instance, the hardmask 520 can be removed before depositing and patterning the photoresist layer 710. However, it can be difficult to accurately pattern a photoresist layer 710 formed on two different thicknesses of silicon. Inaccurate patterning, in turn, can lead to poorly defined fins when the silicon layer 170 and the epitaxial silicon layer 175 are etched. This has a disadvantage over the process shown in
Alternatively, a hardmask 520 without openings can be left on to protect one segment 510 (e.g., the segment with no epitaxial silicon layer 610), while the other segment 530 is etched to form the tall fins 136. The tall fins 136 can then be protected with e.g., another hardmask, while the segment 510 having only the silicon layer 112 is etched to form the short fins 146.
Providing a substrate 110 having a thick silicon layer 112 (e.g. a thickness 910 of about 20 nm or greater) is desirable because it is easier to fabricate uniform thicknesses 910 of silicon across a whole wafer substrate 110 than a thin silicon layer (e.g., a thickness of less than about 20 nm). This can be advantageous over the process discussed above in the context of
A remainder of the unoxidized silicon layer 112 in the segment 1030 has a thickness 1130 that is substantially equal to a height of one or more fins of the channel region. E.g., the thickness 1130 of the remaining silicon later 112 of the segment 1030 is substantially the same as the height 142 of the second fins 146 of the second channel region 125 (
The device 900 constructed in
Enclosing the first and second channel regions 120, 125 with the gate structures 122, 127 also comprises depositing a metal electrode 155 over the fins 136, 146. E.g., in some preferred embodiments, a metal electrode 155 comprising titanium nitride or silicon nitride can be deposited by a technique that can provide a uniform metal layer on the fins 136, 146, such as CVD or ALD. However, other deposition techniques such as physical vapor deposition (PVD) can also be used.
It is preferable for the thicknesses of the dielectric layer 150 and the metal electrode 155 to be kept to a minimum so that the gap 210 between fins can be minimized (
Those skilled in the art to which the invention relates will appreciate that other and further additions, deletions, substitutions and modifications may be made to the described example embodiments, without departing from the invention.