Claims
- 1. A method of forming an integrated circuit device on a substrate, comprising the steps of:providing a first patterned layer of electrically conductive material, the pattern containing trenches; filling the trenches of said first patterned layer with a first insulating material, wherein said first insulating material has a thermal conductivity that effectively dissipates heat during processing and during flow of electricity through said electrically conductive material and a mechanical strength that will maintain structural integrity; planarizing said first insulating material; and depositing a second insulating material over said first patterned layer.
- 2. A method of forming an integrated circuit device on a substrate as in claim 1, further comprising the step of depositing a second layer of electrically conductive material on said second insulating material.
- 3. A method of forming an integrated circuit device on a substrate as in claim 2 further comprising the step of forming a pattern in said second layer of electrically conductive material.
- 4. A method of forming an integrated circuit device on a substrate as in claim 3, further comprising the step of depositing said first insulating material over the patterned second layer of electrically conductive material.
- 5. A method of forming an integrated circuit device on a substrate as in claim 1, further comprising the steps of:opening vias within said second insulating material; filling said vias with an electrically conductive material; and forming a second layer of electrically conductive material onto said second insulating material so that said second layer is electrically connected to said first patterned layer of electrically conductive material.
- 6. A method of forming an integrated circuit device on a substrate as in claim 1, further comprising the step of providing a planarization mask directly over the top surface of said first patterned layer of electrically conductive material.
- 7. A method of forming an integrated circuit device on a substrate as in claim 6, wherein said planarization mask comprises silicon dioxide.
- 8. A method of forming an integrated circuit device on a substrate as in claim 1, wherein said step of planarizing said first insulating material comprises chemical mechanical polishing.
- 9. A method of forming an integrated circuit device on a substrate as in claim 1, further comprising the step of depositing a protective coating over said first insulating material.
- 10. A method of forming an integrated circuit device on a substrate as in claim 9, wherein said protective coating is selected from the group comprising silicon nitride or silicon carbide.
- 11. A method of fabricating an integrated circuit structure, comprising the steps of:providing a first layer of electrically conductive material; depositing a masking layer on said first layer; forming a pattern within said first layer and said masking layer, the pattern having trenches; filling the trenches of said pattern with a first insulating material having a first dielectric constant, wherein said first insulating material has a thermal conductivity that effectively dissipates heat during processing and during flow of electricity through said electrically conductive material and a mechanical strength that will maintain structural integrity; planarizing said first insulating material; and a second insulating material over said pattern, said second insulating material having a dielectric constant that is higher than said first dielectric constant.
- 12. A method as in claim 11, further comprising the step of forming a protective coating over said first insulating material prior to depositing said second insulating material.
- 13. A method as in claim 11, wherein said first insulating material comprises an organic polymer.
- 14. A method as in claim 11, wherein said first insulating material is selected from the group consisting of fluorinated silicon dioxide, hexagonal boron nitride, or silicon carbide.
- 15. A method as in claim 11, wherein said second insulating material comprises silicon dioxide.
Parent Case Info
This is a divisional application of Ser. No.: 08/769,549 filed Dec. 12, 1996 now U.S. Pat. No. 6,040,628.
US Referenced Citations (7)