Claims
- 1. A method of invalidating storage of a computing environment, said method comprising:
specifying, via an instruction, a unit of storage to be invalidated, said unit of storage comprising a plurality of pages of storage; and invalidating the unit of storage.
- 2. The method of claim 1, wherein the specifying comprises providing location information of a data structure associated with the unit of storage.
- 3. The method of claim 2, wherein the location information comprises an origin of the data structure.
- 4. The method of claim 3, wherein the location information further comprises an index of an entry of the data structure, said entry corresponding to the unit of storage.
- 5. The method of claim 4, wherein the invalidating comprises setting an invalid indicator of the entry to invalidate the unit of storage.
- 6. The method of claim 2, wherein the unit of storage comprises one of a segment of storage and a region of storage, and wherein said data structure comprises one of a segment data structure and a region data structure.
- 7. The method of claim 1, wherein the invalidating is performed via the instruction.
- 8. The method of claim 1, wherein the invalidating comprises setting an invalid indicator associated with the unit of storage.
- 9. The method of claim 8, wherein the invalid indicator is located within a data structure associated with the unit of storage.
- 10. The method of claim 9, wherein the data structure comprises a plurality of entries, and wherein the invalidating further comprises employing an index to obtain the entry associated with the unit of storage to be invalidated, said entry having the invalid indicator.
- 11. The method of claim 1, wherein the unit of storage comprises a segment of storage, said segment of storage comprising a plurality of pages of storage.
- 12. The method of claim 1, wherein the unit of storage comprises a region of storage, said region of storage comprising a plurality of segments of storage, a segment of storage comprising a plurality of pages of storage.
- 13. The method of claim 1, wherein the specifying comprises specifying a plurality of units of storage, and the invalidating comprises invalidating the plurality of units of storage.
- 14. The method of claim 13, further comprising clearing one or more buffer entries associated with at least one of one or more units of storage of the plurality of units of storage and another unit of storage.
- 15. The method of claim 1, further comprising clearing one or more entries of one or more buffers associated with at least one of the unit of storage and another unit of storage.
- 16. The method of claim 15, wherein at least one buffer of the one or more buffers is a multi-level buffer.
- 17. The method of claim 15, wherein one or more entries of at least one buffer of the one or more buffers remain uncleared.
- 18. The method of claim 15, wherein the one or more buffers include one or more translation lookaside buffers.
- 19. The method of claim 15, wherein the invalidating and clearing are performed via the instruction.
- 20. The method of claim 1, wherein the storage comprises virtual storage.
- 21. The method of claim 1, wherein the instruction is implemented in at least one of hardware, firmware and software.
- 22. The method of claim 1, wherein the instruction is executed by a processing unit emulating an architecture of the instruction.
- 23. A method of invalidating storage of a computing environment, said method comprising:
specifying a unit of storage to be invalidated, said unit of storage comprising a plurality of pages of storage, and wherein said specifying comprises providing a descriptor of the unit of storage; and invalidating the unit of storage.
- 24. The method of claim 23, wherein the unit of storage comprises one of a segment of storage and a region of storage, said segment of storage comprising a plurality of pages of storage and said region of storage comprising a plurality of segments of storage.
- 25. The method of claim 23, further comprising clearing one or more buffer entries associated with at least one of the unit of storage and another unit of storage.
- 26. The method of claim 25, wherein at least one of the unit of storage and the another unit of storage is specified via an instruction, said instruction facilitating the invalidating and the clearing.
- 27. A method of facilitating the clearing of buffers of a computing environment, said method comprising:
identifying a unit of storage for which clearing of one or more entries of one or more buffers is to be performed, wherein the unit of storage comprises a plurality of pages of storage; and clearing one or more entries of the one or more buffers associated with the identified unit of storage, wherein one or more entries associated with another unit of storage are not cleared.
- 28. The method of claim 27, wherein the clearing is facilitated by an instruction, said instruction comprising an indication of the unit of storage for which clearing is to be performed.
- 29. The method of claim 28, wherein the instruction is executed by a processing unit emulating an architecture of the instruction, said architecture of the instruction being different than an architecture of the processing unit.
- 30. The method of claim 27, wherein the unit of storage comprises a segment of storage, said segment of storage comprising a plurality of pages of storage.
- 31. The method of claim 27, wherein the unit of storage comprises a region of storage, said region of storage comprising a plurality of segments of storage, and wherein a segment of storage comprises a plurality of pages of storage.
- 32. The method of claim 27, wherein the unit of storage is associated with an address space.
- 33. The method of claim 27, wherein at least one buffer of the one or more buffers is a multi-level buffer.
- 34. The method of claim 27, wherein the one or more buffers comprise a plurality of buffers on a plurality of processing units.
- 35. The method of claim 27, wherein the one or more buffers comprise one or more translation lookaside buffers.
- 36. An instruction to be executed within a computing environment, said instruction comprising:
an operation code to identify an instruction to be executed; an invalidation designation to specify information associated with a unit of storage to be invalidated, the unit of storage comprising a plurality of pages of storage; another designation to specify additional information for use by the instruction; and a clearing designation to specify information associated with one of the unit of storage and another unit of storage for which one or more entries of one or more buffers are to be cleared, wherein one or more components of one or more of the invalidation designation, the another designation and the clearing designation are configurable as no-operations.
- 37. The instruction of claim 36, wherein the operation code comprises a code specifying an invalidate dynamic address translation table entry instruction.
- 38. The instruction of claim 36, wherein the information comprises an origin of a data structure associated with the unit of storage to be invalidated.
- 39. The instruction of claim 38, wherein the information further comprises an indicator specifying a type of the data structure.
- 40. The instruction of claim 39, wherein the indicator specifies one of a region data structure and a segment data structure.
- 41. The instruction of claim 38, wherein the additional information comprises an index of an entry of the data structure, the entry corresponding to the unit of storage to be invalidated.
- 42. The instruction of claim 36, wherein the additional information comprises an indication of whether one or more 36 units of storage are to be invalidated.
- 43. The instruction of claim 36, wherein the additional information comprises a clearing indicator indicating whether clearing is to be provided.
- 44. The instruction of claim 36, wherein the clearing designation comprises an origin of a data structure associated with one of the unit of storage and the another unit of storage for which clearing is to take place.
- 45. The instruction of claim 36, wherein the unit of storage comprises a segment of storage, said segment of storage comprising a plurality of pages of storage.
- 46. The instruction of claim 36, wherein the unit of storage comprises a region of storage, said region of storage comprising a plurality of segments of storage, wherein a segment of storage comprises a plurality of pages of storage.
- 47. The instruction of claim 36, wherein the configuring of the clearing designation as a no-operation indicates that clearing is not to be performed.
- 48. The instruction of claim 36, wherein the configuring of the invalidation designation as a no-operation indicates that invalidation is not to be performed.
- 49. The instruction of claim 48, wherein at least one component of the another designation is ignored, in response to configuring the invalidation designation as a no-operation.
- 50. The instruction of claim 36, wherein the computing environment comprises a processing unit to execute the instruction.
- 51. The instruction of claim 50, wherein the processing unit emulates an architecture of the instruction.
- 52. An instruction to be executed within a computing environment, said instruction comprising:
an operation code to identify an instruction to be executed; and at least one of the following:
a first invalidation designation to specify information associated with a unit of storage to be invalidated, the unit of storage comprising a plurality of pages of storage; a second invalidation designation to specify additional information associated with the unit of storage to be invalidated; and a clearing designation to specify information associated with one of the unit of storage and another unit of storage for which one or more entries of one or more buffers are to be cleared, wherein the information specified by the clearing designation is not associated with at least one other unit of storage for which one or more entries are not to be cleared.
- 53. A system of invalidating storage of a computing environment, said system comprising:
means for specifying, via an instruction, a unit of storage to be invalidated, said unit of storage comprising a plurality of pages of storage; and means for invalidating the unit of storage.
- 54. The system of claim 53, wherein the means for specifying comprises means for providing location information of a data structure associated with the unit of storage, said data structure to be employed in the invalidation.
- 55. The system of claim 54, wherein the means for invalidating comprises means for setting an invalid indicator in an entry of the data structure corresponding to the unit of storage.
- 56. The system of claim 53, wherein the means for invalidating employs the instruction.
- 57. The system of claim 56, wherein the instruction is implemented by an emulator emulating an architecture of the instruction.
- 58. The system of claim 53, wherein the means for invalidating comprises means for setting an invalid indicator associated with the unit of storage.
- 59. The system of claim 53, wherein the means for specifying comprises means for specifying a plurality of units of storage, and the means for invalidating comprises means for invalidating the plurality of units of storage.
- 60. The system of claim 53, further comprising means for clearing one or more entries of one or more buffers associated with at least one of the unit of storage and another unit of storage.
- 61. The system of claim 60, wherein one or more entries of at least one buffer of the one or more buffers remain uncleared.
- 62. A computing environment comprising:
a processing unit to execute an instruction to invalidate a unit of storage specified within the instruction, said unit of storage comprising a plurality of pages of storage.
- 63. The computing environment of claim 62, wherein the instruction is executed to clear one or more entries of one or more buffers associated with at least one of the unit of storage and another unit of storage.
- 64. The computing environment of claim 62, wherein the processing unit is of one architecture and executes the instruction of another architecture via emulation.
- 65. A system of facilitating the clearing of buffers of a computing environment, said system comprising:
means for identifying a unit of storage for which clearing of one or more entries of one or more buffers is to be performed, wherein the unit of storage comprises a plurality of pages of storage; and means for clearing one or more entries of the one or more buffers associated with the identified unit of storage, wherein one or more entries associated with another unit of storage are not cleared.
- 66. The system of claim 65, wherein the means for clearing employs an instruction, said instruction comprising an indication of the unit of storage for which clearing is to be performed.
- 67. The system of claim 66, wherein the instruction is implemented by an emulator of the computing environment emulating an architecture of the instruction.
- 68. A computing environment comprising:
a processing unit to execute an instruction, said instruction comprising:
an operation code to identify an instruction to be executed; an invalidation designation to specify information associated with a unit of storage to be invalidated, the unit of storage comprising a plurality of pages of storage; another designation to specify additional information for use by the instruction; and a clearing designation to specify information associated with one of the unit of storage and another unit of storage for which one or more entries of one or more buffers are to be cleared, wherein one or more components of one or more of the invalidation designation, the another designation and the clearing designation are configurable as no-operations.
- 69. The instruction of claim 68, wherein the processing unit emulates an architecture of the instruction.
- 70. A computing environment comprising:
a memory to store an instruction to perform at least one of an invalidate of a unit of storage, said unit of storage comprising a plurality of pages of storage, and a clearing of one or more buffer entries associated with at least one of the unit of storage and another unit of storage; an instruction fetch unit to fetch the instruction from memory; an instruction decode unit to decode the instruction of the instruction fetch unit; and an instruction execution unit to execute the decoded instruction.
- 71. The computing environment of claim 70, wherein one or more of the instruction fetch unit, the instruction decode unit and the instruction execution unit are implemented as one or more routines of an emulator.
- 72. At least one program storage device readable by a machine embodying at least one program of instructions executable by the machine to perform a method of invalidating storage of a computing environment, said method comprising:
specifying, via an instruction, a unit of storage to be invalidated, said unit of storage comprising a plurality of pages of storage; and invalidating the unit of storage.
- 73. The at least one program storage device of claim 72, wherein the specifying comprises providing location information of a data structure associated with the unit of storage.
- 74. The at least one program storage device of claim 72, wherein the invalidating is performed via the instruction.
- 75. The at least one program storage device of claim 72, wherein the invalidating comprises setting an invalid indicator associated with the unit of storage.
- 76. The at least one program storage device of claim 72, wherein the specifying comprises specifying a plurality of units of storage, and the invalidating comprises invalidating the plurality of units of storage.
- 77. The at least one program storage device of claim 72, wherein said method further comprises clearing one or more entries of one or more buffers associated with at least one of the unit of storage and another unit of storage.
- 78. The at least one program storage device of claim 77, wherein one or more entries of at least one buffer of the one or more buffers remain uncleared.
- 79. The at least one program storage device of claim 77, wherein the invalidating and clearing are performed via the instruction.
- 80. The at least one program storage device of claim 79, wherein the instruction is emulated by the machine.
- 81. At least one program storage device readable by a machine embodying at least one program of instructions executable by the machine to perform a method of facilitating the clearing of buffers of a computing environment, said method comprising:
identifying a unit of storage for which clearing of one or more entries of one or more buffers is to be performed, wherein the unit of storage comprises a plurality of pages of storage; and clearing one or more entries of the one or more buffers associated with the identified unit of storage, wherein one or more entries associated with another unit of storage are not cleared.
- 82. The at least one program storage device of claim 81, wherein the clearing is facilitated by an instruction, said instruction comprising an indication of the unit of storage for which clearing is to be performed.
- 83. The at least one program storage device of claim 82, wherein the instruction is emulated by the machine.
- 84. An article of manufacture, comprising:
at least one computer usable medium having computer readable program code logic to facilitate execution of an instruction, said instruction comprising: an operation code to identify an instruction to be executed; an invalidation designation to specify information associated with a unit of storage to be invalidated, the unit of storage comprising a plurality of pages of storage; another designation to specify additional information for use by the instruction; and a clearing designation to specify information associated with one of the unit of storage and another unit of storage for which one or more entries of one or more buffers are to be cleared, wherein one or more components of one or more of the invalidation designation, the another designation and the clearing designation are configurable as no-operations.
- 85. The article of manufacture of claim 84, wherein the computer readable program code logic includes logic to emulate execution of the instruction.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application contains subject matter which is related to the subject matter of the following applications, each of which is assigned to the same assignee as this application. Each of the below listed applications is hereby incorporated herein by reference in its entirety:
[0002] “FILTERING PROCESSOR REQUESTS BASED ON IDENTIFIERS,” Slegel et al., (IBM Docket No. POU920030047US1), Ser. No. ______, filed herewith;
[0003] “BLOCKING PROCESSING RESTRICTIONS BASED ON PAGE INDICES,” Slegel et al., (IBM Docket No. POU920030048US1), Ser. No. ______, filed herewith; and
[0004] “BLOCKING PROCESSING RESTRICTIONS BASED ON ADDRESSES,” Slegel et al., (IBM Docket No. POU920030049US1), Ser. No.______, filed herewith.