Patent Grant
8946057
1) Field
Embodiments of the present invention pertain to the field of semiconductor processing and, in particular, to methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.
2) Description of Related Art
In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. These materials are doped, deposited and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual regions containing integrated circuits known as dice.
Following the integrated circuit formation process, the wafer is “diced” to separate the individual die from one another for packaging or for use in an unpackaged form within larger circuits. The two main techniques that are used for wafer dicing are scribing and sawing. With scribing, a diamond tipped scribe is moved across the wafer surface along pre-formed scribe lines. These scribe lines extend along the spaces between the dice. These spaces are commonly referred to as “streets.” The diamond scribe forms shallow scratches in the wafer surface along the streets. Upon the application of pressure, such as with a roller, the wafer separates along the scribe lines. The breaks in the wafer follow the crystal lattice structure of the wafer substrate. Scribing can be used for wafers that are about 10 mils (thousandths of an inch) or less in thickness. For thicker wafers, sawing is presently the preferred method for dicing.
With sawing, a diamond tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along the streets. The wafer is mounted on a supporting member such as an adhesive film stretched across a film frame and the saw is repeatedly applied to both the vertical and horizontal streets. One problem with either scribing or sawing is that chips and gouges can form along the severed edges of the dice. In addition, cracks can form and propagate from the edges of the dice into the substrate and render the integrated circuit inoperative. Chipping and cracking are particularly a problem with scribing because only one side of a square or rectangular die can be scribed in the <110> direction of the crystalline structure. Consequently, cleaving of the other side of the die results in a jagged separation line. Because of chipping and cracking, additional spacing is required between the dice on the wafer to prevent damage to the integrated circuits, e.g., the chips and cracks are maintained at a distance from the actual integrated circuits. As a result of the spacing requirements, not as many dice can be formed on a standard sized wafer and wafer real estate that could otherwise be used for circuitry is wasted. The use of a saw exacerbates the waste of real estate on a semiconductor wafer. The blade of the saw is approximate 15 microns thick. As such, to insure that cracking and other damage surrounding the cut made by the saw does not harm the integrated circuits, three to five hundred microns often must separate the circuitry of each of the dice. Furthermore, after cutting, each die requires substantial cleaning to remove particles and other contaminants that result from the sawing process.
Plasma dicing has also been used, but may have limitations as well. For example, one limitation hampering implementation of plasma dicing may be cost. A standard lithography operation for patterning resist may render implementation cost prohibitive. Another limitation possibly hampering implementation of plasma dicing is that plasma processing of commonly encountered metals (e.g., copper) in dicing along streets can create production issues or throughput limits.
Embodiments of the present invention are directed to laser and plasma etch wafer dicing using UV-curable adhesive films.
In an embodiment, a method includes forming a mask above the semiconductor wafer. The semiconductor wafer is coupled to a carrier substrate by a UV-curable adhesive film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The UV-curable adhesive film is then irradiated with ultra-violet (UV) light. The singulated integrated circuits are then detached from the carrier substrate.
In an embodiment, a system for dicing a semiconductor wafer having a plurality of integrated circuits includes a factory interface. A laser scribe apparatus is coupled with the factory interface. A plasma etch chamber is coupled with the factory interface. An ultra-violet (UV) irradiation station is coupled with the factory interface. The UV irradiation station is configured to weaken a UV-curable adhesive film.
In an embodiment, a method of dicing a semiconductor wafer having a plurality of integrated circuits includes forming a mask above a silicon substrate coupled to a carrier substrate by a UV-curable adhesive film. The mask covers and protects integrated circuits disposed on the silicon substrate. The integrated circuits include a layer of silicon dioxide disposed above a layer of low K material and a layer of copper. The method further includes patterning the mask, the layer of silicon dioxide, the layer of low K material, and the layer of copper with a laser scribing process to expose regions of the silicon substrate between the integrated circuits. The silicon substrate is then etched through the exposed regions to form singulated integrated circuits. The UV-curable adhesive film is irradiated with ultra-violet (UV) light. The method also includes detaching the singulated integrated circuits from the carrier substrate.
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as laser and plasma etch wafer dicing approaches using UV-curable adhesive films, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects, such as integrated circuit fabrication, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
A hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch may be implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. The plasma etch portion of the dicing process may then be employed to etch through the bulk of the wafer or substrate, such as through bulk single crystalline silicon, to yield die or chip singulation or dicing.
In a hybrid wafer or substrate dicing process, a wafer is specifically handled for both dicing and separated die harvest. The wafer to be diced typically should be kept on a carrier such as a dicing tape or a carrier wafer. The carrier should ensure the cleanliness of separated dies for subsequent die pick. For example, a device wafer may be mounted on the dicing tape. The wafer together with the tape and frame is subjected to a plasma etching process. However, such an approach may put specific requirements on the dicing tape to be used.
One or more embodiments of the present invention include the use of a glass wafer as a carrier wafer. A device wafer is mounted on a dicing tape and then onto the glass wafer. As such, a tape frame is not involved in the plasma etching phase. Following the etching, the device side of the wafer is mounted onto a dicing tape for protection. Subsequently, the glass carrier wafer and the backside dicing tape are removed and the wafer is mounted onto dicing tape with a frame. A front protective tape is then removed. Accordingly, individual dies may be picked for subsequent packaging and assembly operations.
Advantages of the above approach including use of a transparent or glass wafer may include, but are not limited to, one or more of (1) the ability to bypass use of a tape frame inside a plasma chamber. This may avoiding concerns regarding potential degradation of dicing tape during plasma etching and any accompanying changes of chamber configuration to adapt large sized tape frame. (2) Currently used wafer loading and unloading apparatuses for plasma operations may still be used including the wafer storage cassette, robot, or transportation hardware. (3) Both dicing tapes and protective tapes may use UV-curable materials so that they may be readily detached with UV curing. In an embodiment, a suitable wafer thickness for the above approach is approximately 120 microns or thicker.
For IC memory chips, as memory capacity increases, multichip functions and continuous packaging miniaturization may require ultra thin wafer dicing. For logic device chips/processsors, major challenges lie in IC performance increase, low k materials and other material adoption. Wafer thickness reduction in such cases may not be a major driver and, typically, wafer thicknesses in the range of approximately 100 microns to 760 microns are used for major applications to ensure sufficient chip integrity. Processor chip designers/chip makers may place test element groups (TEGs or test patterns) as well as alignment patterns in wafer streets. On one hand, such test patterns may be completely removed during a chip singulation process. On the other hand, the complexity of the test patterns may dictate that the dimensions of the test patterns remain relatively large, typically in the 50 micron to 100 micron range perpendicular to the wafer street. A kerf width approximately in the range of 50 microns to 100 microns, at least at the top surface of the wafer, may thus be needed to completely remove the test patterns. As such, for logic device wafer singulation, a major focus is to achieve delamination-free and efficient dicing processes.
For diamond saw cutting based pure mechanical approach, when applied to low k wafer dicing, even with drastic speed reductions (e.g., down to 2 to 3 mm/sec from typically 40-100 mm/sec), chipping and delamination/crack formation due to mechanical stresses are typically unavoidable in most low-k wafer dicing. Pure laser ablation based dicing technology faces great challenges in throughput improvement, maintaining required die strength and side wall roughness, as well as reducing chances of delamination and chipouts when high power is used to address required throughput. Several hybrid technologies combine laser and the conventional dicing saw to address the low k wafers. First, a laser scribes through the top passivation and metal structures within the street, which the mechanical dicing saw has difficulties to cut through. Next, the saw is used to cut through the actual silicon (Si) substrate. Such a hybrid process may be very slow and typical mechanical sawing problems remain. For example, the wafer backside chipping inherent to the mechanical stress from diamond saw dicing still remains.
Furthermore, mitigation of laser induced front side chipping and delamination associated with low k dielectric stacks has been attempted. For example, a sealing ring has been placed surrounding each die to function as a barrier to propagation of interlayer dielectric and metal layers peeling/delamination. Also, copper grids of certain copper density (e.g., typically 20-80%) in the form of squares called dummies or tiling is added under the passivation layer in the streets wherever there is an absence of alignment or test patterns. Such approaches have aided in suppressing the delamination and chipping. For wafers of 100 microns or thicker, when being diced, the rigidity may be sufficient to directly place the wafers on mounting tapes without die attach film (DAF) such that no DAF cutting process is involved.
Embodiments described herein may address dicing applications of IC wafers, especially with processor chips that have a thickness approximately in the range of 100 microns to 800 microns, and more particularly approximately in the range of 100 microns to 600 microns thickness, and an acceptable dicing kerf width approximately in the range of 50 microns to 200 microns, and more particularly approximately in the range of 50 microns to 100 microns, measured on wafer front surface (e.g., corresponding typical kerf width measured from back side of wafer is approximately 30-50 microns in a laser/saw hybrid process). One or more embodiments are directed to a hybrid laser scribing plus plasma etching approach to dice wafers as described above.
Referring to operation 102 of Flowchart 100, and corresponding
In accordance with an embodiment of the present invention, forming the mask 202 includes forming a layer such as, but not limited to, a photo-resist layer or an I-line patterning layer. For example, a polymer layer such as a photo-resist layer may be composed of a material otherwise suitable for use in a lithographic process. In one embodiment, the photo-resist layer is composed of a positive photo-resist material such as, but not limited to, a 248 nanometer (nm) resist, a 193 nm resist, a 157 nm resist, an extreme ultra-violet (EUV) resist, or a phenolic resin matrix with a diazonaphthoquinone sensitizer. In another embodiment, the photo-resist layer is composed of a negative photo-resist material such as, but not limited to, poly-cis-isoprene and poly-vinyl-cinnamate.
In an embodiment, semiconductor wafer or substrate 204 is composed of a material suitable to withstand a fabrication process and upon which semiconductor processing layers may suitably be disposed. For example, in one embodiment, semiconductor wafer or substrate 204 is composed of a group IV-based material such as, but not limited to, crystalline silicon, germanium or silicon/germanium. In a specific embodiment, providing semiconductor wafer 204 includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, semiconductor wafer or substrate 204 is composed of a material such as, e.g., a material substrate used in the fabrication of light emitting diodes (LEDs).
In an embodiment, semiconductor wafer or substrate 204 has disposed thereon or therein, as a portion of the integrated circuits 206, an array of semiconductor devices. Examples of such semiconductor devices include, but are not limited to, memory devices or complimentary metal-oxide-semiconductor (CMOS) transistors fabricated in a silicon substrate and encased in a dielectric layer. A plurality of metal interconnects may be formed above the devices or transistors, and in surrounding dielectric layers, and may be used to electrically couple the devices or transistors to form the integrated circuits 206. Conductive bumps and/or passivation layers may be formed above the interconnects layers. Materials making up the streets 207 may be similar to or the same as those materials used to form the integrated circuits 206. For example, streets 207 may be composed of layers of dielectric materials, semiconductor materials, and metallization. In one embodiment, one or more of the streets 207 includes test devices similar to the actual devices of the integrated circuits 206.
Referring to operation 104 of Flowchart 100, and corresponding
In an embodiment, patterning the mask 202 with the laser scribing process includes using a laser having a pulse width in the femtosecond range. Specifically, a laser with a wavelength in the visible spectrum or the ultra-violet (UV) or infra-red (IR) ranges (the three totaling a broadband optical spectrum) may be used to provide a femtosecond-based laser, i.e., a laser with a pulse width on the order of the femtosecond (10−15 seconds). In one embodiment, ablation is not, or is essentially not, wavelength dependent and is thus suitable for complex films such as films of the mask 202, the streets 207 and, possibly, a portion of the semiconductor wafer or substrate 204.
Laser parameters selection, such as pulse width, may be critical to developing a successful laser scribing and dicing process that minimizes chipping, microcracks and delamination in order to achieve clean laser scribe cuts. The cleaner the laser scribe cut, the smoother an etch process that may be performed for ultimate die singulation. In semiconductor device wafers, many functional layers of different material types (e.g., conductors, insulators, semiconductors) and thicknesses are typically disposed thereon. Such materials may include, but are not limited to, organic materials such as polymers, metals, or inorganic dielectrics such as silicon dioxide and silicon nitride.
A street between individual integrated circuits disposed on a wafer or substrate may include the similar or same layers as the integrated circuits themselves. For example,
Referring to
Under conventional laser irradiation (such as nanosecond-based or picosecond-based laser irradiation), the materials of street 300 may behave quite differently in terms of optical absorption and ablation mechanisms. For example, dielectrics layers such as silicon dioxide, is essentially transparent to all commercially available laser wavelengths under normal conditions. By contrast, metals, organics (e.g., low K materials) and silicon can couple photons very easily, particularly in response to nanosecond-based or picosecond-based laser irradiation. In an embodiment, however, a femtosecond-based laser process is used to pattern a layer of silicon dioxide, a layer of low K material, and a layer of copper by ablating the layer of silicon dioxide prior to ablating the layer of low K material and the layer of copper. In a specific embodiment, pulses of approximately less than or equal to 400 femtoseconds are used in a femtosecond-based laser irradiation process to remove a mask, a street, and a portion of a silicon substrate.
In accordance with an embodiment of the present invention, suitable femtosecond-based laser processes are characterized by a high peak intensity (irradiance) that usually leads to nonlinear interactions in various materials. In one such embodiment, the femtosecond laser sources have a pulse width approximately in the range of 10 femtoseconds to 500 femtoseconds, although preferably in the range of 100 femtoseconds to 400 femtoseconds. In one embodiment, the femtosecond laser sources have a wavelength approximately in the range of 1570 nanometers to 200 nanometers, although preferably in the range of 540 nanometers to 250 nanometers. In one embodiment, the laser and corresponding optical system provide a focal spot at the work surface approximately in the range of 3 microns to 15 microns, though preferably approximately in the range of 5 microns to 10 microns.
The spacial beam profile at the work surface may be a single mode (Gaussian) or have a shaped top-hat profile. In an embodiment, the laser source has a pulse repetition rate approximately in the range of 200 kHz to 10 MHz, although preferably approximately in the range of 500 kHz to 5 MHz. In an embodiment, the laser source delivers pulse energy at the work surface approximately in the range of 0.5 uJ to 100 uJ, although preferably approximately in the range of 1 uJ to 5 uJ. In an embodiment, the laser scribing process runs along a work piece surface at a speed approximately in the range of 500 mm/sec to 5 m/sec, although preferably approximately in the range of 600 mm/sec to 2 m/sec.
The scribing process may be run in single pass only, or in multiple passes, but, in an embodiment, preferably 1-2 passes. In one embodiment, the scribing depth in the work piece is approximately in the range of 5 microns to 50 microns deep, preferably approximately in the range of 10 microns to 20 microns deep. The laser may be applied either in a train of single pulses at a given pulse repetition rate or a train of pulse bursts. In an embodiment, the kerf width of the laser beam generated is approximately in the range of 2 microns to 15 microns, although in silicon wafer scribing/dicing preferably approximately in the range of 6 microns to 10 microns, measured at the device/silicon interface.
Laser parameters may be selected with benefits and advantages such as providing sufficiently high laser intensity to achieve ionization of inorganic dielectrics (e.g., silicon dioxide) and to minimize delamination and chipping caused by underlayer damage prior to direct ablation of inorganic dielectrics. Also, parameters may be selected to provide meaningful process throughput for industrial applications with precisely controlled ablation width (e.g., kerf width) and depth. As described above, a femtosecond-based laser is far more suitable to providing such advantages, as compared with picosecond-based and nanosecond-based laser ablation processes. However, even in the spectrum of femtosecond-based laser ablation, certain wavelengths may provide better performance than others. For example, in one embodiment, a femtosecond-based laser process having a wavelength closer to or in the UV range provides a cleaner ablation process than a femtosecond-based laser process having a wavelength closer to or in the IR range. In a specific such embodiment, a femtosecond-based laser process suitable for semiconductor wafer or substrate scribing is based on a laser having a wavelength of approximately less than or equal to 540 nanometers. In a particular such embodiment, pulses of approximately less than or equal to 400 femtoseconds of the laser having the wavelength of approximately less than or equal to 540 nanometers are used. However, in an alternative embodiment, dual laser wavelengths (e.g., a combination of an IR laser and a UV laser) are used.
Referring to operation 106 of Flowchart 100, and corresponding
In an embodiment, etching the semiconductor wafer 204 includes using a plasma etching process. In one embodiment, a through-silicon via type etch process is used. For example, in a specific embodiment, the etch rate of the material of semiconductor wafer 204 is greater than 25 microns per minute. An ultra-high-density plasma source may be used for the plasma etching portion of the die singulation process. An example of a process chamber suitable to perform such a plasma etch process is the Applied Centura® Silvia™ Etch system available from Applied Materials of Sunnyvale, Calif., USA. The Applied Centura® Silvia™ Etch system combines the capacitive and inductive RF coupling, which gives much more independent control of the ion density and ion energy than was possible with the capacitive coupling only, even with the improvements provided by magnetic enhancement. This combination enables effective decoupling of the ion density from ion energy, so as to achieve relatively high density plasmas without the high, potentially damaging, DC bias levels, even at very low pressures. This results in an exceptionally wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystalline silicon substrate or wafer 204 at an etch rate greater than approximately 40% of conventional silicon etch rates while maintaining essentially precise profile control and virtually scallop-free sidewalls. In a specific embodiment, a through-silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, which generally is a fluorine-based gas such as SF6, C4F8, CHF3, XeF2, or any other reactant gas capable of etching silicon at a relatively fast etch rate.
Referring again to
Accordingly, referring again to Flowchart 100 and
Referring to
In an embodiment, the UV-curable adhesive film is a double-sided tape including a carrier film disposed between two adhesive layers. In one such embodiment, the carrier film is composed of polyvinyl chloride and the two adhesive layers are acrylic-based adhesive layers. In an embodiment, the UV-curable adhesive film is composed of a material or stack of materials with an adhesive property that weakens upon exposure to UV light. In an embodiment, the UV-curable adhesive film is sensitive to approximately 365 nm UV light. In one such embodiment, this sensitivity enables use of LED light to perform a cure.
Referring to
Referring to
In an embodiment, irradiating the UV-curable adhesive film with UV light includes reducing an adhesiveness of the UV-curable adhesive film by at least approximately 90%. In an embodiment, the carrier substrate 408 is transparent to UV light. Irradiating the UV-curable adhesive film with UV light includes irradiating through the carrier substrate to the UV-curable adhesive film. In one such embodiment, the transparent substrate is a glass substrate.
Referring to
Thus, in accordance with an embodiment of the present invention, a UV-curable adhesive film is applied to a device wafer for singulation. The UV-curable adhesive film attach film is applied onto a carrier tape or carrier wafer. After the laser scribing and subsequent silicon etch processes, the dies are singulated while portions of the UV-curable adhesive film along the wafer streets are exposed. The singulated device wafer is then, in one embodiment, released from the UV-curable adhesive film upon irradiation of the UV-curable adhesive film with UV light.
Referring again to
A single process tool may be configured to perform many or all of the operations in a hybrid laser ablation and plasma etch singulation process including the use of a UV-curable adhesive film. For example,
Referring to
In an embodiment, the laser scribe apparatus 510 houses a laser. In one such embodiment, the laser is a femtosecond-based laser. The laser is suitable for performing a laser ablation portion of a hybrid laser and etch singulation process including the use of a mask, such as the laser ablation processes described above. In one embodiment, a moveable stage is also included in laser scribe apparatus 500, the moveable stage configured for moving a wafer or substrate (or a carrier thereof) relative to the laser. In a specific embodiment, the laser is also moveable. The overall footprint of the laser scribe apparatus 1210 may be, in one embodiment, approximately 2240 millimeters by approximately 1270 millimeters, as depicted in
In an embodiment, the plasma etch chamber 508 is configured for etching a wafer or substrate through the gaps in a patterned mask to singulate a plurality of integrated circuits. In one such embodiment, the plasma etch chamber 508 is configured to perform a deep silicon etch process. In a specific embodiment, the plasma etch chamber 508 is an Applied Centura® Silvia™ Etch system, available from Applied Materials of Sunnyvale, Calif., USA. The plasma etch chamber 508 may be specifically designed for a deep silicon etch used to create singulate integrated circuits housed on or in single crystalline silicon substrates or wafers. In an embodiment, a high-density plasma source is included in the plasma etch chamber 508 to facilitate high silicon etch rates. In an embodiment, more than one plasma etch chamber is included in the cluster tool 506 portion of process tool 500 to enable high manufacturing throughput of the singulation or dicing process.
The factory interface 502 may be a suitable atmospheric port to interface between an outside manufacturing facility with laser scribe apparatus 510 and cluster tool 506. The factory interface 502 may include robots with arms or blades for transferring wafers (or carriers thereof) from storage units (such as front opening unified pods) into either cluster tool 506 or laser scribe apparatus 510, or both.
Cluster tool 506 may include other chambers suitable for performing functions in a method of singulation. For example, in one embodiment, in place of an additional etch chamber, a deposition chamber 512 is included. The deposition chamber 512 may be configured for mask deposition on or above a device layer of a wafer or substrate prior to laser scribing of the wafer or substrate. In one such embodiment, the deposition chamber 512 is suitable for depositing a photo-resist layer.
In an embodiment, an ultra-violet (UV) irradiation station 514, e.g., including a UV light source, is included for weakening a UV-curable adhesive film. In one such embodiment, the UV irradiation station is configured to reduce an adhesiveness of the UV-curable adhesive film by at least approximately 90%. In an embodiment, a metrology station is also included as a component of process tool 500.
Embodiments of the present invention may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to embodiments of the present invention. In one embodiment, the computer system is coupled with process tool 1200 described in association with
The exemplary computer system 600 includes a processor 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 618 (e.g., a data storage device), which communicate with each other via a bus 630.
Processor 602 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 602 may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processor 602 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. Processor 602 is configured to execute the processing logic 626 for performing the operations described herein.
The computer system 600 may further include a network interface device 608. The computer system 600 also may include a video display unit 610 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse), and a signal generation device 616 (e.g., a speaker).
The secondary memory 618 may include a machine-accessible storage medium (or more specifically a computer-readable storage medium) 631 on which is stored one or more sets of instructions (e.g., software 622) embodying any one or more of the methodologies or functions described herein. The software 622 may also reside, completely or at least partially, within the main memory 604 and/or within the processor 602 during execution thereof by the computer system 600, the main memory 604 and the processor 602 also constituting machine-readable storage media. The software 622 may further be transmitted or received over a network 620 via the network interface device 608.
While the machine-accessible storage medium 631 is shown in an exemplary embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.
In accordance with an embodiment of the present invention, a machine-accessible storage medium has instructions stored thereon which cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits. The method includes forming a mask above the semiconductor wafer. The semiconductor wafer is coupled to a carrier substrate by a UV-curable adhesive film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The UV-curable adhesive film is then irradiated with ultra-violet (UV) light. The singulated integrated circuits are then detached from the carrier substrate.
Thus, laser and plasma etch wafer dicing using UV-curable adhesive films has been disclosed. In accordance with an embodiment of the present invention, a method includes forming a mask above the semiconductor wafer. The semiconductor wafer is coupled to a carrier substrate by a UV-curable adhesive film. The mask covers and protects the integrated circuits. The mask is patterned with a laser scribing process to provide a patterned mask with gaps. The patterning exposes regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then etched through the gaps in the patterned mask to form singulated integrated circuits. The UV-curable adhesive film is then irradiated with ultra-violet (UV) light. The singulated integrated circuits are then detached from the carrier substrate. In one embodiment, irradiating the UV-curable adhesive film with UV light comprises reducing an adhesiveness of the UV-curable adhesive film by at least approximately 90%.
This application claims the benefit of U.S. Provisional Application No. 61/637,506, filed Apr. 24, 2012, and U.S. Provisional Application No. 61/663,397, filed Jun. 22, 2012, the entire contents of which are hereby incorporated by reference herein.
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