The present invention relates to a pulse jitter reduction circuit which is employed as a last stage synchronizer for synchronizing a pulser circuit for a time-of-flight (TOF) mass spectrometer with the data acquisition circuits to improve the signal resolution of the spectrometer.
A TOF mass spectrometer relies upon precise timing between the high voltage acceleration pulse applied to the flight tube to accelerate ions along the flight tube and the subsequent detection of the time of arrival of the ions by the data acquisition system. The high voltage pulse employed for accelerating the ions, therefore, must be synchronized with the data acquisition timing, such that ions corresponding to particular elements can be accurately identified. The more precise the timing relationship of the respective signals, the more precise and higher the resolution of the mass spectrometer. With conventional pulse-trigger systems employed to provide the high voltage pulses to the flight tube, inherent uncertainty exists in the pulse initiation. This inherent fluctuation in the pulse initiation time is referred to as “jitter” and is a limiting factor of the resolution of a TOF mass spectrometer. Jitter as high as 100 pico seconds (ps) or higher is common and adversely affects the resolution of a mass spectrometer, particularly where samples having closely grouped elemental ions are involved.
Thus, there exists a need for an improved triggering circuit which eliminates or greatly reduces jitter existing in conventional triggering circuits.
A pulse jitter reduction circuit employs a low jitter system clock coupled to a pulse generator and an ultra low jitter flip-flop to generate substantially jitter-free trigger signals employed to generate high voltage pulses for the flight tube of a TOF mass spectrometer. By eliminating time fluctuations due to jitter in the triggering signal, the predictability of the arrival time of ions at the detector in a flight tube of a TOF mass spectrometer is greatly improved, thereby improving the resolution of the mass spectrometer.
These and other features, objects and advantages of the present invention will become apparent upon reading the following description thereof together with reference to the accompanying drawings.
Referring to
The circuit for generating an ultra low jitter trigger pulse includes an ultra low jitter clock 20 coupled to a pulse generator 22 which can be of conventional design and incorporated into a field programmable gate array (FPGA) to provide raw trigger pulses 52 (shown in
As illustrated by pulses 54 in
The pulser circuit 14 applies high voltage pulses 56 to the ion chamber to accelerate ions down the flight tube 12 to the detector 16. The output of detector 16 is an analog signal 58 which is applied to a switched preamplifier 18 having an output coupled to the input of an analog-to-digital (A/D) converter 30. The signals 59 from the A/D converter 30 are synchronized with the high voltage pulses from pulser 14 by the ultra low jitter clock signals 50 from clock 20.
Pulses identical to the raw trigger pulses 52 shown in
The pulse generator, including the FPGA 22, is coupled to an external PC 40, which is conventionally programmed to receive data from the A/D converter 30 and FPGA 22 representing the ions detected by detector 16. In addition, however, the FPGA controls the preamplifier 18 to look at either the signals from detector 16 or from the test pulse output from circuit 28. By employing a test signal, the data acquisition system can be calibrated to great precision to assure the detected ions are accurately identified with their elements. The signals from the circuit shown in
The subsequent low jitter trigger 54 from the ultra low jitter flip-flops 24, 26, and 28 are substantially jitter-free, as shown in
The data output signal from preamplifier 18 is shown by analog waveform diagrams 58 in
The PC 40 is programmed as in prior Leco Corporation TOF mass spectrometers, such as Leco Model No. Pegasus® IV, to receive the data and provide an output to a printer and/or monitor for analytical samples under test. The PC 40 also applies control signals via conductor 23 to the FPGA 22 for initiating the test pulses and calibrating the instrument. The details of one embodiment of the ultra low jitter pulse generator is shown in
In
The ultra low jitter trigger pulses from the Q output of circuit 24, represented by signals 54 in
The FPGA 22 is programmed via an external computer, such as PC 40, to generate a repetitive raw trigger signal 52 (
It will become apparent to those skilled in the art that various modifications to the preferred embodiment of the invention as described herein can be made without departing from the spirit or scope of the invention as defined by the appended claims.
This application claims priority under 35 U.S.C. § 119(e) on U.S. Provisional Application No. 60/719,128 entitled LAST STAGE SYNCHRONIZER SYSTEM, filed on Sep. 21, 2005, by Timothy A. Hall, the entire disclosure of which is incorporated herein by reference.
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Number | Date | Country | |
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20070063139 A1 | Mar 2007 | US |
Number | Date | Country | |
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60719128 | Sep 2005 | US |