Patent Application
20230307539
The present disclosure relates to transistor structures, and more specifically, to lateral diffusion field effect transistor (LDFET) structures.
A lateral diffusion field effect transistor (LDFET) is a field effect transistor that includes a drift region between the gate conductor and the drain region, and the drift region avoids forming a high electric field at the drain junction, which is the p-n junction between the body and the drain region. With LDFETs a large portion of the voltage is consumed within the drift region, which prevents the electric field generated across the gate dielectric from causing breakdown of the gate dielectric.
Field plates can be used with LDFETs to improve control of the field generated by the gate conductor. Field plates are conductive elements, which are placed over the drift region to enhance the performance of a high voltage transistor device by manipulating the electric fields (e.g., reducing peak electric fields) generated by the gate electrode. By manipulating the electric field generated by the gate electrode, the high voltage transistor device can achieve higher breakdown voltages.
An exemplary structure herein has a substrate, a drift region within the substrate, a semiconductor-on-insulator structure on the substrate adjacent to the drift region, a gate insulator layer having a first portion on the substrate and a second portion extending over the semiconductor-on-insulator structure, a gate conductor on the first portion, and a field plate on the gate conductor and the second portion.
Another exemplary transistor structure herein has a body region within a substrate. The body region has a first conductivity type. The transistor structure further includes a blocking region within the substrate and a drift region within the substrate. The blocking region is between the body region and the drift region. The transistor structure further includes a source region within the body region. The source region has a second conductivity type. The transistor structure further includes a gate insulator on the blocking region and a gate conductor on the gate insulator. The gate conductor is insulated from the source region. The gate insulator is between the blocking region and the gate conductor. The transistor structure further includes a silicon structure on the drift region. The gate conductor is between the source region and the silicon structure. The transistor structure further includes a drain region within the drift region. The drain region has the second conductivity type. The silicon structure is between the gate conductor and the drain region. The transistor structure further includes a field plate on the gate insulator. A portion of the silicon structure is between the field plate and the drift region. The silicon structure has a buried oxide layer and a silicon layer. The buried oxide layer is between the drift region and the silicon layer.
An additional exemplary transistor structure has a body region within a substrate. The body region has a first conductivity type. The transistor structure further includes a blocking region laterally adjacent (in a lateral direction) the body region within the substrate and a drift region laterally adjacent the blocking region within the substrate. The blocking region is laterally between the body region and the drift region. The transistor structure further includes a source region within the body region. The source region has a second conductivity type. The transistor structure further includes a gate insulator positioned vertically on the blocking region (in a vertical direction perpendicular to the lateral direction) and a gate conductor vertically on the gate insulator. The gate conductor is insulated from the source region. The gate insulator is vertically between the blocking region and the gate conductor. The transistor structure further includes a silicon structure vertically on the drift region. The gate conductor is positioned laterally between the source region and the silicon structure. The transistor structure further includes a drain region within the drift region. The drain region has the second conductivity type. The silicon structure is laterally between the gate conductor and the drain region. The transistor structure further includes a field plate vertically on the gate insulator. A portion of the silicon structure is vertically between the field plate and the drift region. The silicon structure has a buried oxide layer and a silicon layer. The buried oxide layer is vertically between the drift region and the silicon layer.
The embodiments herein will be better understood from the following detailed description with reference to the drawings, which are not necessarily drawn to scale and in which:
As mentioned above, field plates can be used with LDFETs to improve control of the field generated by the gate conductor. By manipulating the electric field generated by the gate electrode, the high voltage transistor device can achieve higher breakdown voltages. However, the limits on drain voltages are still an item that can be improved. In view of such issues, the structures herein utilize a silicon-on-insulator structure between the drift region and the field plate to support higher drain voltages.
The transistor structure 100 further includes a blocking region 106 laterally adjacent (in a lateral direction C shown in
Further, a drift region 104 is laterally adjacent the blocking region 106 within the substrate 102. The drift region 104 has the opposite conductivity type from the body region 108. Thus, if the body region 108 has a P-type dopant, the drift region 104 has an N-type dopant (and vice versa). Positionally, the blocking region 106 is laterally between the body region 108 and the drift region 104.
The transistor structure 100 also includes a source region 110 within the body region 108 and a drain region 126 within the drift region 104. Silicides 116, 128 on the source region (110) and drain region (126) are also shown in
A gate insulator 134 contacts the source region 110 and is positioned vertically (e.g., in a vertical direction B that is perpendicular to the lateral direction C) on the blocking region 106. A gate conductor 120 is vertically on the gate insulator 134. An insulator sidewall spacer 118 is positioned laterally between the gate conductor 120 and the source region 110 and its associated silicide 116. The gate conductor 120 is insulated from the source region 110 by the sidewall spacer 118. The gate insulator 134 also can extend vertically between the blocking region 106 and the gate conductor 120 or an individually formed sidewall spacer can be used.
The transistor structure 100 additionally includes a silicon-on-insulator structure 124, 132 (which is sometimes more referred to herein as a “silicon-on-insulator structure,” an “SOT structure,” a “semiconductor-on-insulator structure,” or simply a “silicon structure”) vertically on the drift region 104. The silicon structure 124, 132 has a silicon layer 132 (a semiconductor) vertically on a buried oxide layer 124 (an insulator).
The silicon layer 132 is a semiconductor and can be fully depleted (undoped) partially depleted (partially) doped, etc. As shown in
Also, a conductive field plate 122 (e.g., metal, polysilicon, etc.) is vertically on (e.g., immediately adjacent to, in direct contact with, contacting, etc.) the gate conductor 120 and the gate insulator 134. The field plate 122 enhances the performance of high voltage transistors by manipulating electric fields (e.g., reducing peak electric fields) generated by the gate conductor 120. By manipulating the electric field generated by the gate conductor 120, the high voltage transistor devices can achieve higher breakdown voltages. Further, the silicon structure 124, 132 electrically isolates the drain region 126 which supports higher drain voltages.
As shown in
In the structure shown in
Differently, in the example shown in
While
In the example shown in
Differently, in the structure shown in
Further, the buried oxide layer 124 and silicon layer 132 are formed/patterned on the substrate 102.
The foregoing structures can be used within a PCell (parameterized cell). PCells have a set of parameters that define the actual implementation of the cell. For example, two instances of a particular PCell could be placed, such that each instance has difference parameters. Each instance would have the same basic function, but they would have different performance and difference sizes.
For purposes herein, a “semiconductor” material has an electrical conductivity value falling between that of a conductor, such as metallic copper, and an insulator, such as glass. A dopant or an impurity is a trace element deliberately added to a semiconductor. Some examples of semiconductors are silicon, germanium, gallium arsenide, and elements near the so-called “metalloid staircase” on the periodic table. As used herein, “implantation processes” can take any appropriate form (whether now known or developed in the future) and can be, for example, ion implantation, etc. Epitaxial growth occurs in a heated (and sometimes pressurized) environment that is rich with a gas of the material that is to be grown.
For purposes herein, an “insulator” is a relative term that means a material or structure that allows substantially less (<95%) electrical current to flow than does a “conductor.” The dielectrics (insulators) mentioned herein can, for example, be deposited (e.g., deposited silicon dioxide) and/or grown from either a dry oxygen ambient or steam and then patterned. Alternatively, the dielectrics herein may be formed (grown or deposited) from any of the many candidate low dielectric constant materials (low-K (where K corresponds to the dielectric constant of silicon dioxide) materials such as fluorine or carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, spin-on silicon or organic polymeric dielectrics, etc.) or high dielectric constant (high-K) materials, including but not limited to silicon nitride, silicon oxynitride, a gate dielectric stack of SiO2 and Si3N4, hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO2), zirconium dioxide (ZrO2), hafnium silicon oxynitride (HfSiON), hafnium aluminum oxide compounds (HfAlOx), other metal oxides like tantalum oxide, etc. The thickness of dielectrics herein may vary contingent upon the required device performance.
The conductors mentioned herein can be formed of any conductive material, such as polycrystalline silicon (polysilicon), amorphous silicon, a combination of amorphous silicon and polysilicon, and polysilicon-germanium, rendered conductive by the presence of a suitable dopant. Alternatively, the conductors herein may be one or more metals, such as tungsten, hafnium, tantalum, molybdenum, titanium, or nickel, or a metal silicide, any alloys of such metals, and may be deposited using physical vapor deposition, chemical vapor deposition, or any other technique known in the art.
There are various types of transistors, which have slight differences in how they are used in a circuit. For example, a bipolar transistor has terminals labeled base, collector, and emitter. A small current at the base terminal (that is, flowing between the base and the emitter) can control, or switch, a much larger current between the collector and emitter terminals. Another example is a field-effect transistor, which has terminals labeled gate, source, and drain. A voltage at the gate can control a current between source and drain. Within such transistors, a semiconductor (channel region) is positioned between the conductive source region and the similarly conductive drain (or conductive source/emitter regions), and when the semiconductor is in a conductive state, the semiconductor allows electrical current to flow between the source and drain, or collector and emitter. The gate is a conductive element that is electrically separated from the semiconductor by a “gate oxide” (which is an insulator); and current/voltage within the gate changes makes the channel region conductive, allowing electrical current to flow between the source and drain. Similarly, current flowing between the base and the emitter makes the semiconductor conductive, allowing current to flow between the collector and emitter.
A positive-type transistor “P-type transistor” uses impurities such as boron, aluminum or gallium, etc., within an intrinsic semiconductor substrate (to create deficiencies of valence electrons) as a semiconductor region. Similarly, an “N-type transistor” is a negative-type transistor that uses impurities such as antimony, arsenic or phosphorous, etc., within an intrinsic semiconductor substrate (to create excessive valence electrons) as a semiconductor region.
Generally, transistor structures, in one example, can be formed by depositing or implanting impurities into a substrate to form at least one semiconductor channel region, bordered by shallow trench isolation regions below the top (upper) surface of the substrate. A “substrate” herein can be any material appropriate for the given purpose (whether now known or developed in the future) and can be, for example, silicon-based wafers (bulk materials), ceramic materials, organic materials, oxide materials, nitride materials, etc., whether doped or undoped. The “shallow trench isolation” (STI) structures are generally formed by patterning openings/trenches within the substrate and growing or filling the openings with a highly insulating material (this allows different active areas of the substrate to be electrically isolated from one another).
While only one or a limited number of transistors are illustrated in the drawings, those ordinarily skilled in the art would understand that many different types transistor could be simultaneously formed with the embodiment herein and the drawings are intended to show simultaneous formation of multiple different types of transistors; however, the drawings have been simplified to only show a limited number of transistors for clarity and to allow the reader to more easily recognize the different features illustrated. This is not intended to limit this disclosure because, as would be understood by those ordinarily skilled in the art, this disclosure is applicable to structures that include many of each type of transistor shown in the drawings.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the foregoing. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, as used herein, terms such as “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, “upper”, “lower”, “under”, “below”, “underlying”, “over”, “overlying”, “parallel”, “perpendicular”, etc., are intended to describe relative locations as they are oriented and illustrated in the drawings (unless otherwise indicated) and terms such as “touching”, “in direct contact”, “abutting”, “directly adjacent to”, “immediately adjacent to”, etc., are intended to indicate that at least one element physically contacts another element (without other elements separating the described elements). The term “laterally” is used herein to describe the relative locations of elements and, more particularly, to indicate that an element is positioned to the side of another element as opposed to above or below the other element, as those elements are oriented and illustrated in the drawings. For example, an element that is positioned laterally adjacent to another element will be beside the other element, an element that is positioned laterally immediately adjacent to another element will be directly beside the other element, and an element that laterally surrounds another element will be adjacent to and border the outer sidewalls of the other element.
Embodiments herein may be used in a variety of electronic applications, including but not limited to advanced sensors, memory/data storage, semiconductors, microprocessors and other applications. A resulting device and structure, such as an integrated circuit (IC) chip can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The description of the present embodiments has been presented for purposes of illustration and description but is not intended to be exhaustive or limited to the embodiments in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the embodiments herein. The embodiments were chosen and described in order to best explain the principles of such, and the practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated.
While the foregoing has been described in detail in connection with only a limited number of embodiments, it should be readily understood that the embodiments herein are not limited to such disclosure. Rather, the elements herein can be modified to incorporate any number of variations, alterations, substitutions or equivalent arrangements not heretofore described, but which are commensurate with the spirit and scope herein. Additionally, while various embodiments have been described, it is to be understood that aspects herein may be included by only some of the described embodiments. Accordingly, the claims below are not to be seen as limited by the foregoing description. A reference to an element in the singular is not intended to mean “one and only one” unless specifically stated, but rather “one or more.” All structural and functional equivalents to the elements of the various embodiments described throughout this disclosure that are known or later, come to be known, to those of ordinary skill in the art are expressly incorporated herein by reference and intended to be encompassed by this disclosure. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the foregoing as outlined by the appended claims.
