Patent Application
20060292885
1. Field of the Invention
The present invention relates to etching processes during semiconductor device fabrication. More particularly, the present invention relates methods for reducing the effects of etch-related photoresist shrinkage during semiconductor device fabrication.
2. Background of the Invention
Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). When using the various tools, a mask can be used that includes a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g., comprising one or more dies) on a substrate, such as a silicon or other wafer comprising a semiconductor, that has been coated with a layer of radiation-sensitive material, such as a photoresist. The photoresist is selectively exposed to radiation, such as ultraviolet light, and then developed to form a patterned resist. The patterned resist should ideally respond to an exposing radiation such that the mask image is replicated in the resist. The patterned resist should also ideally protect the underlying material during subsequent processing steps, such as etching.
As semiconductor devices have continued to shrink in size, smaller wavelength optical lithography (“photolithography”) techniques have been developed. For example, 193 nm technology (technology using a radiation source having a wavelength of 193 nm to develop the photoresist) is being used to extend optical lithography to the dimensions required for the manufacture of 1 gigabyte DRAM and advanced CMOS microprocessors with 140-180 nm minimum feature sizes. Moreover, work is currently underway to develop the next generation of photolithography techniques that use 157 nm technology.
While 193 nm technology allows the resist to be patterned with smaller structures, problems arise because the resist suffers from shrinkage when exposed to wet or dry etching.
Thus, there is a need to overcome these and other problems of the prior art and to provide a method to reduce the effects of photoresist shrinkage during etching.
According to various embodiments, the present teachings include a method for fabricating a semiconductor device with reduced line bending. The method can include forming a first layer and depositing a photoresist layer on the first layer. The photoresist layer can be patterned, wherein the patterning comprises at least one support feature disposed adjacent to an outside of a corner feature.
According to various other embodiments, the present teachings include a method for forming a semiconductor device having reduced line bending. The method can include forming a first layer and forming a patterned mask layer on the first layer, wherein the patterned mask layer has a mask pattern comprising at least one support feature disposed at an outside of a corner feature. The method can further include etching the first layer to replicate the mask pattern in the first layer.
According to still further various embodiments, the present teachings include a semiconductor device including a first layer and a patterned mask layer on the first layer. The patterned mask layer can define a corner structure and define at least one support structure disposed adjacent to an outside of the corner structure.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.
In the following description, reference is made to the accompanying drawings that form a part thereof, and in which is shown by way of illustration specific exemplary embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the invention. The following description is, therefore, not to be taken in a limited sense.
Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the invention are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Moreover, all ranges disclosed herein are to be understood to encompass any and all sub-ranges subsumed therein. For example, a range of “less than 10” can include any and all sub-ranges between (and including) the minimum value of zero and the maximum value of 10, that is, any and all sub-ranges having a minimum value of equal to or greater than zero and a maximum value of equal to or less than 10, e.g., 1 to 5.
The term mask, as used herein, can be broadly interpreted as referring to generic pattern means that can be used to endow an incoming beam with a patterned cross-section, corresponding to a target pattern that is to be created in a target portion of the substrate, including, but not limited to photoresists.
As used herein and unless otherwise specified, the term “feature” refers to a pattern(s) defined by a mask. For example, a gate structure can be defined in a mask image by a gate feature.
As used herein and unless otherwise specified, the term “structure” refers to patterns formed in a layer underlying the patterned mask. For example, a gate structure can be a gate formed by etching a layer, such as a polysilicon layer, underlying the patterned resist.
Referring to the top view of
Fabrication of corner feature 250 is shown in
Mask 251 can be then used to replicate the pattern of mask 251 in layer 210. Referring to
According to various embodiments, support features can be used to reduce line bending during formation of any corner structure having a having an angle of less than 180°. For example, corner structures having angles of 90° or 135° can be formed using a patterned photoresist that includes support features. The support features can be positioned in the patterned photoresist at an outside of the comer features that define the corner structure.
While an exemplary embodiment has been described with reference to a gate poly-Si etch, one of ordinary skill in the art will understand that other embodiments are envisioned including, but not limited to, a shallow-trench isolation etch and an interconnect trench etch.
One of ordinary skill in the art will understand that other geometries can be used as support features to define support structures. For example,
While the invention has been illustrated with respect to one or more implementations, alterations and/or modifications can be made to the illustrated examples without departing from the spirit and scope of the appended claims. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular function. Furthermore, to the extent that the terms “including”, “includes”, “having”, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
As used herein, the term “one or more of” with respect to a listing of items such as, for example, A and B, means A alone, B alone, or A and B.
Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.
