Claims
- 1. A semiconductor device on a doped silicon semiconductor substrate with a pair of gate conductor stacks formed thereon, said gate conductor stacks comprising a gate oxide layer, a gate electrode layer and a dielectric cap layer, and a contact opening formed over a contact region, said device comprising:
- lightly doped regions in the surface of said substrate, said lightly doped regions being self-aligned with said gate conductor stacks, first dielectric spacers of a first dielectric material are formed on the sidewalls of said gate conductor stacks,
- second dielectric spacers of a second dielectric material formed on the sidewalls of said first dielectric spacers adjacent to said gate conductor stacks,
- highly doped regions in the surface of said substrate, said highly doped regions being spaced a distance A away from said gate conductor stacks,
- where
- A=x+y,
- x . . . is the thickness of said first dielectric spacer,
- y . . . is the thickness of said second dielectric spacer, and
- said highly doped regions being self-aligned with said second dielectric spacers where they are formed on said first dielectric spacers adjacent to said gate conductor stacks,
- said contact opening formed over a contact region including said first spacers formed in said contact opening, while excluding said second dielectric spacers in said contact opening down to said substrate,
- whereby said highly doped region in said contact opening is narrower than the spacing between said first dielectric spacers, and is equal to the spacing which would exist between second dielectric spacers if they were present between said first dielectric spacers.
- 2. A device in accordance with claim 1 wherein said first dielectric spacers have a thickness from about 300 .ANG. to about 700 .ANG..
- 3. A device in accordance with claim 2 wherein said second dielectric spacers have a thickness from about 200 .ANG. to about 800 .ANG..
- 4. A device in accordance with claim 2 wherein said first dielectric spacers are composed of silicon nitride.
- 5. A device in accordance with claim 2 wherein said second dielectric spacers are composed of silicon oxide.
- 6. A device in accordance with claim 1 wherein said second dielectric spacers have a thickness from about 200 .ANG. to about 800 .ANG..
- 7. A device in accordance with claim 6 wherein said first dielectric spacers are composed of silicon nitride.
- 8. A device in accordance with claim 6 wherein said second dielectric spacers are composed of silicon oxide.
- 9. A device in accordance with claim 1 wherein said first dielectric spacers are composed of silicon nitride.
- 10. A device in accordance with claim 1 wherein said second dielectric spacers are composed of silicon oxide.
- 11. A device in accordance with claim 1 wherein
- said dielectric cap layer is composed of silicon nitride,
- said first dielectric spacers are composed of silicon nitride with a thickness from about 300 .ANG. to about 700 .ANG., and
- said second dielectric spacers are composed of silicon oxide with a thickness from about 200 .ANG. to about 800 .ANG..
- 12. A semiconductor device on a doped silicon semiconductor substrate with a pair of gate conductor stacks formed thereon, said gate conductor stacks comprising a gate oxide layer, a gate electrode layer, a dielectric cap layer, and a contact opening, said device comprising:
- lightly doped regions in the surface of said substrate, said lightly doped regions being self-aligned with said gate conductor stacks,
- first dielectric spacers of a first dielectric material are formed on the sidewalls of said gate conductor stacks,
- second dielectric spacers of a second dielectric material are formed on the sidewalls of said first dielectric spacers adjacent to said gate conductor stacks,
- highly doped regions in the surface of said substrate, said highly doped regions being spaced a distance A away from said gate conductor stacks,
- where
- A=x+y,
- x . . . is the thickness of said first dielectric spacer,
- y . . . is the thickness of said second dielectric spacer, and
- said highly doped regions being self-aligned with said second dielectric spacers where they are formed on said first dielectric spacers adjacent to said gate conductor stacks,
- a blanket cap dielectric layer over said device including said spacers and said dielectric cap layer above said gate conductor stacks, and
- said contact opening extending through said blanket cap dielectric layer over a contact region excluding second dielectric spacers in said contact opening down to said substrate.
- 13. A device in accordance with claim 12 wherein
- said dielectric cap layer is composed of silicon nitride,
- said first dielectric spacers are composed of silicon nitride with a thickness from about 300 .ANG. to about 700 .ANG., and
- said second dielectric spacers are composed of silicon oxide with a thickness from about 200 .ANG. to about 800 .ANG..
- 14. A semiconductor device on a doped silicon semiconductor substrate with a pair of gate conductor stacks formed thereon, said gate conductor stacks comprising a gate oxide layer, a gate electrode layer, a dielectric cap layer, and a contact opening with a width W, said device comprising:
- lightly doped regions in the surface of said substrate, said lightly doped regions being self-aligned with said gate conductor stacks,
- first dielectric spacers of a first dielectric material are formed on the sidewalls of said gate conductor stacks,
- second dielectric spacers of a second dielectric material are formed on the sidewalls of said first dielectric spacers adjacent to said gate conductor stacks except for said second dielectric spacers having been been removed from said contact opening,
- highly doped regions in the surface of said substrate, said highly doped regions having a width W-2A and being spaced a distance A away from said gate conductor stacks,
- where
- A=x+y,
- x . . . is the thickness of said first dielectric spacer,
- y . . . is the thickness of said second dielectric spacer, and
- said highly doped regions being self-aligned with said second dielectric spacers where they are formed on said first dielectric spacers adjacent to said gate conductor stacks.
- 15. A device in accordance with claim 14 wherein:
- a blanket cap dielectric layer is formed over said device including said spacers and said dielectric cap layer above said gate conductor stacks, and
- a contact opening extends through said blanket cap dielectric layer over a contact region excluding second dielectric spacers in said contact opening down to said substrate.
- 16. A device in accordance with claim 14 wherein
- said dielectric cap layer is composed of silicon nitride,
- said first dielectric spacers are composed of silicon nitride with a thickness from about 300 .ANG. to about 700 .ANG., and
- said second dielectric spacers are composed of silicon oxide with a thickness from about 200 .ANG. to about 800 .ANG..
- 17. A device in accordance with claim 14 wherein:
- a blanket cap dielectric layer is formed over said device including said spacers and said dielectric cap layer above said gate conductor stacks,
- a contact opening extends through said blanket cap dielectric layer over a contact region excluding second dielectric spacers in said contact opening down to said substrate,
- said dielectric cap layer is composed of silicon nitride,
- said first dielectric spacers are composed of silicon nitride with a thickness from about 300 .ANG. to about 700 .ANG., and
- said second dielectric spacers are composed of silicon oxide with a thickness from about 200 .ANG. to about 800 .ANG..
Parent Case Info
This is a division of patent application Ser. No. 08/851,401, filing date May 5, 1997, now U.S. Pat. No. 5,763,312, Method Of Fabricating Ldd Spacers In Mos Devices With Double Spacers And Device Manufactured Thereby, assigned to the same assignee as the present invention.
US Referenced Citations (6)
Divisions (1)
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Number |
Date |
Country |
Parent |
851401 |
May 1997 |
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