The present invention relates to semiconductor light emitting devices and, in particular, to light emitting devices mounted to submounts.
Semiconductor light emitting devices such as light emitting diodes (LEDs) are among the most efficient light sources currently available. Material systems currently of interest in the manufacture of high brightness LEDs capable of operation across the visible spectrum include group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials; and binary, ternary, and quaternary alloys of gallium, aluminum, indium, and phosphorus, also referred to as III-phosphide materials. Such devices typically have a light emitting or active region sandwiched between a p-doped region and an n-doped region. Often III-nitride devices are epitaxially grown on sapphire, silicon carbide, or III-nitride substrates and III-phosphide devices are epitaxially grown on gallium arsenide by metal organic chemical vapor deposition (MOCVD) molecular beam epitaxy (MBE) or other epitaxial techniques.
A disadvantage of III-phosphide devices that are grown on gallium arsenide (GaAs) substrates is that the bandgap energy of GaAs is smaller than that of the III-phosphide material. As a result, the emission efficiency of an AlGaInP—GaAs device is significantly reduced. Attempts to solve this problem include bonding a support substrate to the epitaxy layers and removing the GaAs substrate. By way of example, mirrored or transparent support substrates may be used, such as that described in R. H. Horng, et al., “AlGaInP light-emitting diodes with mirror substances fabricated by wafer bonding”, Appl. Phys. Lett. Vol. 75, No.20, 15 Nov. 1999, pp 3054-3056 and Shoou-Jinn Chang et al., “AlGaInP-Sapphire Glue Bonded Light-Emitting Diodes”, IEEE Journal of Quantum Electronics, Vol. 38, No. 10, October 2002, pp. 1390-1394. Such devices, however, have contacts formed on the side of the device through which light is extracted. Wire bonds are then used to connect the contacts of the device with a submount. Unfortunately, the heat transfer through the wire bonds is poor, and thus, additional heat sinking structures are typically required. In addition, the submount includes leads that are connected to the wire bonds. Accordingly, the footprint of the submount is typically much larger than the light emitting device. Thus, the resulting device has large footprint relative to the light emitting area of the device.
According to an embodiment of the present invention, a device includes a semiconductor light emitting device with contacts formed on the same side of the device and is mounted on a transparent submount having conductive vias that are electrically connected to the contacts in a flip-chip configuration. A method of producing a semiconductor light emitting device includes producing a light emitting active region disposed between a first region of first conductivity type and a second region of second conductivity type on a growth substrate. A contact region is etched through the second region, the active region, and partially through the first region. Contacts are produced on the first region, i.e., in the etched contact region, and on the second region. A transparent submount with conductive vias is provided and bonded to the assembly before the growth substrate is removed. The submount and assembly are then diced together resulting in a device with a small footprint.
In accordance with an embodiment of the present invention, a semiconductor light emitting device is mounted on a transparent submount with conductive vias, which advantageously permit assembly without wire bonds. The presence of conductive vias in the transparent submount enables the production of a device with a flip-ship configuration, i.e., where the p and n contacts are formed on the same side of the device and light is extracted through the side of the device that is opposite the contact side. Accordingly, light extraction is improved. Moreover, the conductive vias provide an efficient means of heat transfer. The transparency of the submount permits easy alignment of the conductive vias with the contacts on the device, and thus, the submount may be bonded to the light emitting device at the wafer level. The bonded light emitting device and submount can then be diced together in a single operation. Accordingly, the resulting device includes a submount with a footprint that is approximately the same size as the footprint of the light emitting device.
The epi layers 101 are grown on a GaAs substrate 114, which as illustrated by the broken lines in
The table below gives examples of the approximate thicknesses, composition, and dopants appropriate for each layer in the epi layer 101. The characteristics given below for each layer are examples and are not meant to be limiting. More information on selecting the appropriate characteristics of the layers of the device may be found in chapters 1-3 of Semiconductors and Semimetals, Volume 64, Electroluminescence I, Academic Press, San Francisco, 2000, Gerd Mueller, ed., which is incorporated herein by reference.
The p contact layer 108 is electrically coupled to a metal contact 109 and n contact layer 110 is electrically coupled to another metal contact 111. Contacts 109 and 111 are illustrated in
Similarly, the n contact 111 may be formed with multiple layers, as illustrated in
As illustrated in
The submount 116 may be, e.g., 10 mils thick, and the vias 118 may be approximately 100 μm to 250 μm in diameter with a pitch of 200-50 μm. A suitable submount 116 with vias 118 can be manufactured to order by M/A-Com, located in Lowell, Mass. In addition, submounts with conductive vias, their production and their general use with LEDs is disclosed in U.S. Ser. No. 10/632,719, by Jerome C. Bhat et al., entitled “Mount for Semiconductor Light Emitting Device, filed Jul. 31, 2003, which is assigned to the assignee of the present disclosure and entirety of which is incorporated herein by reference.
The submount 116 may have a layer of gold or AuSn solder (not shown) on the top surface, i.e., the surface that is bonded to the contacts 109 and 111. Of course, if a bonding layer of gold or AuSn is on the top surface of the submount 116, the p and n contact portions of the bonding layer should be electrically isolated. A conductive region 120, which may be, e.g., a solderable layer of gold or AuSn, is in electrical contact with vias 118 that are coupled to the p contact 109, and another conductive region 122 is in electrical contact with the vias 118 that are coupled to the n contact 111. The conductive regions 120 and 122 may be used to solder the submount to structure such as a board, without the use of wire bonds.
The use of transparent submount 116 with conductive vias 118 is advantageous because it simplifies alignment of the vias 118 with the contacts 109 and 111. Accordingly, the submount 116 can be bonded to the semiconductor light emitting device 100a at the wafer level, e.g., a plurality of semiconductor light emitting devices in a wafer are simultaneously bonded to a respective plurality of submounts in a wafer. The submount wafer 116 also then serves as mechanical support for the epi layers 101 during and after the GaAs substrate 114 removal. The bonded submounts and semiconductor light emitting devices can then be diced in a single operation. Thus, the footprint of the submount in the resulting device is no larger than the footprint of the semiconductor light emitting device. Further, the conductive vias 118 through the submount 116 enable a flip-chip style LED, where the p and n contact layers 108 and 110 are formed on the same side of the semiconductor light emitting device 100a and light is extracted through the side of the device opposite the contact side, as illustrated in
It should be understood that the embodiment illustrated in
The n and p metal layers, e.g., the contact ohmic layers and guard layers are then formed (step 206). First, ohmic contact layers 109a, 111a and then guard layers 109b, 111b are formed on the appropriate semiconductor layers and alloyed to the semiconductor layers by, for example, a rapid thermal anneal or anneal in a furnace. The bonding layers 111c (and layers 111e and 111d, if used) are then deposited and patterned to form the n contact 111 (step 208). The bonding layers 109c (and layers 109e and 109d, if used) are then deposited patterned to form the p contact 109. The deposition and patterning of one or more of the layers in the multiplayer contacts 109 and 111 may be performed together or separately. If desired, a dielectric material, such as SiNi or Al2O3, may be deposited around the n contact region 112 before or after the n contact 109 is deposited to serves as a protective and passivating layer.
The vias 118 in submount 116 are then aligned with the contacts 109 and 111, and thermo-mechanically bonded to the assembly 100b, illustrated in
The bonding of the submount 116 to the assembly 100b may be performed at 325° C. for 1 to 5 minutes with a pressure of approximately 50 psi, if the bonding layers 109d and 1111d are an AuSn solder. Forming gas or hydrogen atmosphere is preferred. If the bonding layers are gold, the bonding may be performed at 300-400° C. at 100-800 psi for 1 to 10 minutes. A thermosonic scrubbing may be used to assist the bonding process.
Once the submount 116 is bonded to the assembly 100b, the devices may be tested at the wafer level (step 211), if desired. With the flip-chip configuration illustrated in
Because the submount 116 and LED 100a are mounted at the wafer level and diced together, the footprint of the resulting device 100 is small. As can be seen in
Having described the invention in detail, those skilled in the art will appreciate that, given the present disclosure, modifications may be made to the invention without departing from the spirit of the inventive concept described herein. For example, though the embodiment described above is a III-phosphide device, some embodiments may be applied to III-nitride devices. Therefore, it is not intended that the scope of the invention be limited to the specific embodiments illustrated and described.