BACKGROUND
Electronic devices, such as smart phones, tablet computers, digital media players, and so forth, increasingly employ light sensors to control the manipulation of a variety of functions provided by the device. For example, light sensors may be used by an electronic device to detect ambient lighting conditions in order to control the brightness of the device's display screen. Typical light sensors employ photodetectors such as photodiodes, phototransistors, or the like, which convert received light into an electrical signal (e.g., a current or voltage).
SUMMARY
Light sensors are described that include a trench structure integrated therein. In an implementation, the light sensor includes a substrate having a dopant material of a first conductivity type and multiple trenches disposed therein. The light sensor also includes a diffusion region formed proximate to the multiple trenches. The diffusion region includes a dopant material of a second conductivity type. A depletion region is created at the interface of the dopant material of the first conductivity type and the dopant material of the second conductivity type. The depletion region is configured to attract charge carriers to the depletion region, at least substantially a majority of the charge carriers generated due to light incident upon the substrate.
This Summary is provided solely to introduce subject matter that is fully described in the Detailed Description and Drawings. Accordingly, the Summary should not be considered to describe essential features nor be used to determine scope of the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
The detailed description is described with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different instances in the description and the figures may indicate similar or identical items.
FIG. 1-1 is a diagrammatic partial cross-sectional view illustrating an implementation of a light sensor in accordance with an example implementation of the present disclosure, where the light sensor includes a plurality of trenches having a diffusion region formed about the trenches to cause the generation of a depletion region proximate to the trenches.
FIG. 1-2 is a diagrammatic plan view illustrating an implementation of the light sensor shown in FIG. 1-1 in accordance with another example implementation of the present disclosure, where the light sensor includes a plurality of trench regions and each trench region includes a sub-grouping of trenches.
FIG. 2 is a flow diagram illustrating a process in an example implementation for fabricating light sensors having a trench formed therein, such as the sensors shown in FIGS. 1-1 and 1-2.
FIGS. 3 through 6 are diagrammatic partial cross-sectional views illustrating the fabrication of a light sensor, such as the light sensor shown in FIGS. 1-1 and 1-2, in accordance with the process shown in FIG. 2.
DETAILED DESCRIPTION
Overview
Increasingly, gesture detection is being employed by electronic devices to detect user input for various applications associated with the electronic device. Such electronic devices typically have light sensor configurations employing a number of photodetectors to improve range and operation (e.g., noise reduction) of gesture detection. These sensor configurations may also provide limited tracking and detection of complicated gestures (e.g., in-and-out gestures, diagonal swipe gestures, and so forth). Additionally, these electronic devices employ illumination sources, such as IR light sources to emit light. The emitted light may be reflected by an object in proximity of the electronic device, and the reflected light is detected by the photodetectors.
Light sensors are described that include a trench structure integrated therein. In an implementation, the light sensor includes a substrate having a dopant material of a first conductivity type and multiple trenches disposed therein. For example, the substrate may comprise a P−− doped substrate. In some implementations, a first sub-group of trenches may be at least substantially adjacent to a second sub-group of trenches. The light sensor also includes a diffusion region formed proximate to the multiple trenches. The diffusion region includes a dopant material of a second conductivity type. For example, the diffusion region may comprise an N+ doped diffusion region. A depletion region is created at the interface of the dopant material of the first conductivity type and the dopant material of the second conductivity type. The depletion region is configured to attract charge carriers to the depletion region, at least substantially a majority of the charge carriers generated due to light incident upon the substrate. By employing a plurality of trenches, the density of depletion regions may be improved. Additionally, by incorporating depletion regions about the trenches, a light, such as an infrared light, that generates charge carriers deeper (e.g., generate carriers deeper than two micrometers (2 μm or greater) within the substrate may be detected utilizing the deeper trench regions.
Example Light Sensor
FIGS. 1-1 and 1-2 illustrates an example light sensor 100 (e.g., photodetector) in accordance with example implementations of the present disclosure. As shown, the light sensor 100 includes a substrate 102. The substrate 102 comprises a base material utilized to form one or more integrated circuit devices through various semiconductor fabrication techniques, such as photolithography, ion implantation, deposition, etching, and so forth. In one or more implementations, the substrate 102 comprises a portion of a silicon wafer that may be configured in a variety of ways. For example, the substrate 102 may comprise a portion of an n-type silicon wafer or a portion of a p-type silicon wafer. In an implementation, the substrate 102 may comprise group V elements (e.g., phosphorus, arsenic, antimony, etc.) configured to furnish n-type charge carrier elements. In another implementation, the substrate 102 may comprise group MA elements (e.g., boron, etc.) configured to furnish p-type charge carrier elements. In a specific implementation, the substrate 102 comprises a P−− region. However, it is contemplated that other conductive types may be utilized, such as a P− region, a P region, or the like.
The substrate 102 includes a plurality of trenches 104 formed therein. In embodiments, the trenches 104 may be elongated trenches. The trenches 104 have a depth of about twenty micrometers (20 μm) or greater. For example, the depths of the trenches 104 range from about twenty micrometers (20 μm) to about forty micrometers (40 μm). In a specific implementation, the width of each trench 104 may be approximately five hundred nanometers (500 nm) or less, and the depth of each trench 104 may be about thirty micrometers (30 μm). The pitch of the trenches 104 may be about eight hundred nanometers (800 nm), or less in some configurations. The length of the trenches may be two micrometers (2 um) to twenty micrometers (20 um). In one or more implementations, the trenches 104 may have an aspect ratio of about fifty to one (50:1) to about one hundred and fifty to one (150:1).
The trenches 104 allow a subsequent N+ diffusion region 106 (e.g., portion of the substrate 102 that encompasses the trenches 104 is comprised of the N+ diffusion region 106) to form proximate (e.g., about, or surrounding the) trenches 104. The N+ diffusion region 106 is disposed within the P−− region of the substrate 102 (see FIG. 1). In a specific implementation, the P−− region of the substrate 102 may be doped 1×1019 atoms per square centimeter to allow for a larger depletion region (e.g., as compared to a depletion region created by a P− or a P region). The N+ diffusion region 106 may be doped at greater than 1×1019 atoms per square centimeter to achieve a suitable doping profile in high aspect ratio trenches. Thus, a p-n junction 108 is created at the interface 110 of the region 102 and the region 106. The p-n junction 108 serves to cause generation of a depletion region 112 proximate to the trenches 104. In a specific implementation, the depletion region 112 is an elongated depletion region 112. Additionally, the depletion region 112 may extend beyond the depth of the trenches 104. The depletion region 112 causes generation of an electric field due to exchange of charge carriers between the P−− region 102 and the N+ diffusion region 106 (which in turn leaves charged ions within each respective region 102, 106 and causes the generation of the electric field). As described in greater detail herein, the depletion region 112 is utilized to absorb (e.g., capture) electron-hole pairs created by the light incident upon the substrate 102.
The depth of the trenches 104 allow for absorption of light occurring in the infrared light spectrum. For example, light occurring at approximately nine hundred and fifty nanometers (e.g., light having a wavelength value at approximately nine hundred and fifty nanometers) penetrates further into the substrate 102 as compared to light occurring lower than nine hundred and fifty (e.g., light penetrates further into the substrate 102 before causing generation of an electron-hole pair). Thus, electron-hole pairs are generated by the light occurring at the nine hundred and fifty nanometer value deeper (e.g., further) in the substrate 102 as compared to electron-hole pairs generated by light occurring at values less than nine hundred and fifty nanometers (e.g., light occurring within the visible spectrum causes generation of electron-hole pairs within the substrate 102 at a shallower depth as compared to light occurring with the infrared spectrum). Due to the extended depth of the trenches 104, the depletion region 112 formed about the trenches 104 may absorb, or capture, electrons generated due to light occurring within the infrared spectrum. Thus, during operation of the light sensor 100, the electric field generated due to the presence of the depletion region 112 attracts the generated charge carriers to the depletion region 112, which may increase the amount of charge carriers within the depletion region 112 (and causes an increase in current).
As shown, the trenches 104 may include one or more layers 114. The layers 114 may comprise a variety of materials. In an implementation, the layers 114 may comprise an optically transparent layer (e.g., a layer that is configured to be transparent to light occurring within wavelengths of interest). For example, the optically transparent layer 114 may comprise an n-doped polysilicon layer that provides an electrical connection (e.g., a pin). In another implementation, the layer 114 may comprise an insulation layer(s). For example, the insulation layers may comprise a silicon dioxide (SiO2) layer.
As shown in FIG. 1-2, the light sensor 100 includes a plurality of trench regions 116. Each trench region 116 (e.g., a sub-grouping of trenches 104) includes a plurality of trenches 104 formed within the substrate 102. As shown, the trenches 104 of a respective trench region 116 are at least substantially parallel with respect to one another within that trench region 116. For example, the substrate 102 includes a first trench region 116-1 and a second trench region 116-2. The trenches 104 of the first trench region 116-1 are at least substantially parallel with the other trenches 104 of the first trench region 116-1, and the trenches 104 formed within the second trench region 116-2 are at least substantially parallel with the other trenches 104 of the second trench region 116-2.
The trenches 104 of a trench region 116 are at least substantially perpendicular with respect to the trenches 104 of the adjacent trench regions 116. For example, the trenches 104 of the first trench region 116-1 are at least substantially perpendicular with the trenches 104 of the second trench region 116-2. Thus, the trenches 104 of each respective trench region 116 is at least substantially perpendicular with the trenches 104 of the adjacent trench regions 116 (i.e., adjacent in the x- and y-directions). For example, as shown in FIG. 1-2, the light sensor 100 includes alternating perpendicular trench regions 116. The perpendicular orientation of the trenches 104 within adjacent trench regions 116 may provide for facilitating stress management and for detecting gestures (e.g., detecting light) from at least approximately ninety-degrees (90°) with respect to the surface of the light sensor 100. In some instances, the perpendicular orientation may reduce wafer bow and wafer warpage. Thus, a greater percentage of the substrate 102 may be utilized for other integrated components, such as integrated circuit devices, capacitors, and so forth. Additionally, the orientation of the trench regions 116 may increase the sensitivity of the light sensor 100 as compared to a light sensor having trenches oriented parallel to one another. For example, the orientation of the first trench region 116-1 may detect a greater amount of light incident upon the light sensor 100 from a first direction than the second trench region 116-2 detects. In another example, the orientation of the second trench region 116-2 may detect a greater amount of light incident upon the light sensor 100 from a second direction (e.g., a direction different than the first direction) than the first trench region 116-1 detects.
Example Fabrication Processes
FIG. 2 illustrates an example process 200 that employs semiconductor fabrication techniques to fabricate light sensors having a trench structures integrated therein, such as the light sensor 100 shown in FIGS. 1-1 through 1-2. FIGS. 3 through 6 illustrate formation of example light sensors 500 in an example semiconductor wafer 302. As illustrated in FIG. 2, a hardmask layer is formed over a semiconductor wafer (Block 202). In an implementation, as shown in FIG. 3, the wafer 302 includes a dopant material of a first conductivity type. For example, the wafer 302 is a P−− semiconductor wafer (e.g., the wafer is doped P−−). A hardmask layer 304 is formed (e.g., deposited) over a surface 306 of the wafer 302. In an implementation, the thickness of the hardmask layer 304 may range from about two micrometers (2 μm) to about six micrometers (6 μm). The hardmask layer 304 may be an oxide layer, or the like.
A plurality of trench regions are formed in the semiconductor wafer (Block 204). More specifically, a plurality of trenches are formed that define the trench regions (Block 206). As described above with respect to FIGS. 1-1 and 1-2, multiple trench regions (e.g., trench regions 116 shown in FIG. 1-2) are formed within the semiconductor wafer 302 by way of forming at least one trench 308 within the trench regions. Thus, multiple trenches 308 are formed within the semiconductor wafer to form and/or define the trench regions. Suitable i-line or deep ultraviolet (DUV) lithography techniques may be utilized to form the plurality of trenches 308 (see FIG. 4). For example, the hardmask layer 304 may be patterned (e.g., depositing photoresist over the hardmask layer and patterning the photoresist) and etched (e.g., a deep reactive-ion etching technique) to form the trenches 308. The thickness of the hardmask layer 304 assists in facilitating formation of trenches 308 having a depth ranging from about (20 μm) to about forty micrometers (40 μm). In a specific implementation, a suitable Bosch etching technique may be utilized to etch the wafer 302 to form the trenches 308. As described above, the trenches 308 of a respective capacitor region (e.g., sub-grouping of trenches 308) are at least substantially perpendicular to the trenches 308 of the adjacent capacitor region.
Once the trench regions and the trenches are formed, an N+ diffusion region is formed proximate to the trenches (Block 208) such that the trenches are at least substantially encapsulated by the N+ diffusion region. As shown in FIG. 5, the trench sidewalls 310 are subjected to a diffusion deposition to form a diffusion region 312 having dopant material of a second conductivity type. For example, the diffusion region 312 is an N+ diffusion region 312 proximate (e.g., adjacent) to the trenches 308. In an implementation, the N+ diffusion deposition is performed prior to the hardmask layer 304 being removed to allow the N+ diffusion region 312 to self-align with respect to the trenches 308. The N+ diffusion region 312 may also provide capacitor-to-capacitor bulk isolation. In an implementation, the N+ diffusion doping concentration is greater than 1×1019 atoms per square centimeter. The formation of the N+ diffusion region 312 serves to create the p-n junction 314 within the wafer 302. The p-n junction 314 causes the generation of a depletion region 316, which extends at least substantially the depth of the trenches 308. In some implementations, the depletion region 316 extends beyond the depth of the trenches 308. Additionally, in an implementation, a phosphoryl chloride (POCl3) doping step may be performed at less than nine hundred degrees Celsius (<900° C.), which may slow the reaction kinetics so that the sidewall and the bottom of the trenches 308 are at least substantially uniformly doped. For example, the doping process temperature may range from at least approximately eight hundred and seventy-five degrees Celsius (875° C.) to at least approximately eight hundred and ninety-five degrees Celcius (895° C.). In another example, the doping process temperature may range from at least approximately eight hundred and eighty degrees Celsius (880° C.) to at least approximately eight hundred and ninety degrees Celsius (890° C.).
An insulation layer is formed over the semiconductor wafer (Block 210). As shown in FIG. 6, a layer 318 is formed over the surface 306 of the wafer 302. The layer 318 may be a doped polysilion layer for furnishing an electrical contact, an insulation layer (e.g., a silicon dioxide (SiO2) layer), or the like.
CONCLUSION
Although the subject matter has been described in language specific to structural features and/or process operations, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Patent Application
20140264711
