Patent Grant
8289258
This application claims the benefit of the Korean Patent Application No. P2007-26070 filed on Mar. 16, 2007, Korean Patent Application Nos. P2007-030332, P2007-0030323, P2007-0030333, and P2007-0030454 filed on Mar. 28, 2007, and Korean Patent Application Nos. P2007-0046113 and P2007-0046126 filed on May 11, 2007, each of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device that is adapted to simplify a control printed circuit board (PCB).
2. Description of the Related Art
A liquid crystal display (LCD) device controls the light transmittance of liquid crystal cells in accordance with a video signal, thereby displaying a picture. An active matrix type LCD device actively controls data by switching data voltages supplied to liquid crystal cells using a thin film transistor (TFT) formed in each liquid crystal cell Clc, as shown in
As shown in
The system board 18 includes an analog to digital converter, a scaler, and a signal interpolation circuit (not shown). The signal interpolation circuit changes the data supplied through an interface circuit to comply with the resolution of the LCD panel and compensates for the deteriorated video data by the changing the resolution according to a signal interpolation method.
The control PCB 20 is equipped with a control circuit and a data transmitting circuit (not shown). The control PCB 20 supplies the data from the system board 18 via the wire cable 19 to the data ICs 23 of the source PCB 22. Further, it generates the timing control signals for controlling the data ICs 23 and supplies them to the source PCB 22 via the cable 21. Signal lines (not shown) in the source COFs 24 transmit the timing control signals and digital video data from the control PCB 20 to the data ICs 23.
Some of the LCD devices, including for example those made for televisions, have recently been increasing in size. As the LCD panel 25 of the LCD device becomes larger in size, the number of data lines and the number of source COFs 24 increase correspondingly. Moreover, in order to accommodate for more data lines and source COFs, the source PCB 22 becomes larger and more complex. Then, it becomes increasingly difficult to align the source PCB 22 and the source COF 24. Also, as the source PCB 22 becomes larger, it becomes increasingly difficult to couple it to the LCD panel 25 because an automatic mounting device, such as existing SMT (Surface Mount Technology) equipment, is designed on the basis of the source PCB 22 of a relatively small size. Thus, there is a limitation for increasing the size of the source PCB 22 using the existing equipment. Finally, as the LCD device becomes larger, more peripheral components such as memory chips and ICs are required, and the number of required output pins of the control circuit on the control PCB 20 increases. Hence, the cost for manufacturing the control PCB 20 increases.
Moreover, in the related art LCD device configuration as shown in
In the configuration of
The two port expansion part 121 divides the left/right data RGBl, RGBr inputted at half the frequency (f/2) from the left/right data divider 120 into the odd-numbered pixel data RGBlodd, RGBrodd and the even-numbered pixel data RGBleven, RGBreven. Then, the two port expansion part 121 supplies the data RGBlodd, RGBleven, RGBrodd, and RGBreven to the data modulator 122 at one quarter of the input frequency (f/4).
In the event that the data is modulated by employing the mini LVDS method, the data modulator 122 increases the frequency of the data RGBlodd, RGBrodd, RGBleven, RGBreven from the two port expansion part 121 in accordance with a quadruple speed mini LVDS clock, so as to separately output the left side data RGBlodd, RGBleven and the right side data RGBrodd, RGBreven to two different output ports 141 and 142, respectively, of the timing controller at the same frequency (f) as the input frequency. Each of the left side data RGBlodd, RGBleven and the right side data RGBrodd, RGBreven includes three pairs of odd-numbered pixel data, three pairs of even-numbered pixel data, and a pair of mini clocks. The left side data RGBlodd, RGBleven are transmitted to the first source PCB 141A through the first output port 161 of the timing controller 131, the first connection line 154A and the first FFC (flexible flat cable) 153A. The right side data RGBrodd, RGBreven are transmitted to the second source PCB 141B through the second output port 162 of the timing controller 131, the second connection line 154B and the second FFC 153B. Thus, the number of the output pins of the timing controller 131 needs to be about twice as many as that of a conventional configuration with a single source PCB, causing the timing controller 131 and control PCB 140 to be larger in size and more costly.
Accordingly, the present invention is directed to a liquid crystal display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.
Accordingly, it is an object of the present invention to provide to a liquid crystal display device that is adaptive for dividing a source PCB into multiple source PCBs and reducing the number of output pins of the timing controller and the size of the control PCB. In this regard, the timing controller is configured to have a fewer number of output ports than the number of source PCBs, e.g., one output port for a device with two source PCBs.
Moreover, it is an object of the present invention to integrate elements and functions of the control PCB into the system board to reduce the size and complexity of the control PCB, and to reduce the overall manufacturing time and cost.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
In order to achieve these and other objects of the invention, a display according to an aspect of the present invention includes: a display panel including a first group of data lines and a second group of data lines, a plurality of gate lines crossing the first and second groups of data lines, and a plurality of picture cells arranged in a matrix; a first source PCB coupled to first data integrated circuits (ICs) to supply first data voltages to the first group of data lines; a second source PCB coupled to second data ICs to supply second data voltages to the second group of data lines; a timing controller having a single output port with a plurality of output pins which are configured to output video data to both the first and second data ICs, and to output a timing control signal to control both the first and second data ICs; and a first connection cable coupling the single output port of the timing controller to at least one of the first and second source PCBs to transmit the video data and the timing control signal from the timing controller to the at least one of the first and second source PCBs, wherein the first data ICs and second data ICs are configured to generate the first and second data voltages, respectively, based on the video data and the timing control signal.
In another aspect, a liquid crystal display according to the present invention includes: a liquid crystal display panel including a first group of data lines and a second group of data lines, a plurality of gate lines crossing the first and second groups of data lines, a plurality of liquid crystal cells arranged in a matrix, and lines on glass (LOGs); a first source PCB coupled to first data integrated circuits (ICs) to supply first data voltages to the first group of data lines; a second source PCB coupled to second data ICs to supply second data voltages to the second group of data lines; and a timing controller configured to output video data and a timing control signal to the first source PCB, wherein the LOGs couple the first and second source PCBs to transmit the video data and the timing control signal from the first source PCB to the second source PCBs, and wherein the first data ICs and second data ICs are configured to generate the first and second data voltages, respectively, based on the video data and the timing control signal.
In yet another aspect, a liquid crystal display according to the present invention includes: a liquid crystal display panel including a first group of data lines and a second group of data lines, a plurality of gate lines crossing the first and second groups of data lines, and a plurality of liquid crystal cells arranged in a matrix; a first source PCB coupled to first data ICs to supply first data voltages to the first group of data lines; a second source PCB coupled to second data ICs to supply second data voltages to the second group of data lines; and a timing controller configured to output video data to both the first and second data ICs and to output a timing control signal to control both the first and second data ICs, wherein the timing controller is configured to receive an input video data at a first frequency and to output the video data at a second frequency that is substantially higher than the first frequency, and wherein the first data ICs and second data ICs are configured to generate the first and second data voltages, respectively, based on the video data and the timing control signal.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.
As shown in
Formed on the lower glass substrate of the LCD panel 30 are, among others, data lines D1 to Dm, gate lines G1 to Gn, thin film transistors (TFTs), pixel electrodes 1 of liquid crystal cells Clc connected to the TFTs, and storage capacitors Cst. Also formed on the lower glass substrate of the LCD panel 30 are a plurality of LOGs (Lines On Glass) which transmit, among others, data, timing control signals, and drive voltage signals between the source COFs as will be described later.
Formed on the upper glass substrate of the LCD panel 30 are, among others, a black matrix (not shown), color filters (not shown) and a common electrode 2. The common electrode 2 is formed on the upper glass substrate in devices employing a vertical electric field driving method, such as a TN (Twisted Nematic) mode or a VA (Vertical Alignment) mode. Alternatively, the common electrode 2 may be formed along with the pixel electrode 1 on the lower glass substrate in devices employing a horizontal electric field driving method, such as an IPS (In-Plane Switching) mode or an FFS (Fringe Field Switching) mode. Polarizers (not shown) with the optical axes perpendicularly crossing each other are respectively applied to the upper glass substrate and the lower glass substrate of the LCD panel 30. Alignment films (not shown) for setting the pre-tilt angle of liquid crystal molecules are then formed in the internal surfaces of the respective polarizers which face the liquid crystal layer.
The timing controller 31 receives timing signals such as vertical and horizontal synchronization signals Vsync and Hsync, a data enable signal DE, and clock signals such as a dot clock (DCLK) signal, which comply with the resolution of the LCD panel 30. For example, the timing controller 31 may receive these signals from an image or graphic processing circuit 64 as shown in
The timing control signals include gate timing control signals, such as a gate start pulse GSP, a gate shift clock signal GSC, and a gate output enable GOE. The gate start pulse GSP indicates a starting horizontal line from which a scan starts in a first vertical period when an image or data is displayed on the LCD panel 30. The gate shift clock signal GSC is inputted to a shift register within the gate drive circuit and is generated to have a pulse width corresponding to the on-period of the TFT as a timing control signal for sequentially shifting the gate start pulse GSP. The gate output enable signal GOE indicates the output of the gate drive circuit 33.
Further, the timing control signals includes data timing control signals such as a source sampling clock SSC, a source output enable signal SOE, a polarity control signal POL and the like. The source sampling clock SSC indicates a latch operation of the data within the data drive circuit 32 on the basis of a rising or falling edge. The source output enable signal SOE indicates the output of the data drive circuit 32. The polarity control signal POL indicates the polarity of the data voltage which is to be supplied to the liquid crystal cell Clc of the liquid crystal display panel 30.
Further, the timing controller 31 divides digital video data into an odd-numbered pixel data RGBodd and an even-numbered pixel data RGBeven, and supplies the divided data RGBodd, RGBeven to the data drive circuit 32. In order to reduce the swing width of the data voltage and EMI in the transmission path of the data, the timing controller 31 modulates the data by a mini LVDS (low voltage differential signaling) method or an RSDS (reduced swing differential signaling) method, and supplies the modulated data to the data drive circuit 32.
The data drive circuit 32 latches the digital video data RGBodd, RGBeven under control of the timing controller 31. And, the data drive circuit 32 converts the data into an analog positive/negative gamma compensation voltage in accordance with the polarity control signal POL to generate a positive/negative analog data voltage, and supplies the data voltage to the data lines D1 to Dm.
The gate drive circuit 33 is configured to have a plurality of gate ICs (not shown), each of which includes a shift register, a level shifter for converting a swing width of an output signal of the shift register into a swing width which is suitable for driving the TFT of the liquid crystal cell, and an output buffer connected between the level shifter and the gate line G1 to Gn. The gate drive circuit 33 sequentially outputs the scan pulses to the gate lines G1 to Gn. The IC's of the gate drive circuit 33 are mounted on the COF or the TCP to be connected to gate pads (not shown) which are formed on the lower glass substrate of the liquid crystal display panel with an ACF (anisotropic conductive film). Alternatively, the gate drive circuit 33 may be formed directly on the lower glass substrate of the liquid crystal display panel 30 at the same time the TFTs, the gate lines G1 to Gn, and the data lines D1 to Dm are formed in a pixel array with the use of a gate-in-panel process. As a further alternative, the ICs of the gate drive circuit 33 may be directly bonded onto the lower glass substrate of the liquid crystal display panel 30 by a chip-on-glass method.
As shown in
Dummy lines 51, as shown in
Formed in the first and second source PCBs 41A, 41B are bus lines to which the digital video data RGBodd, RGBeven are transmitted, bus lines to which the data timing control signals are transmitted, and bus lines to which drive voltages are transmitted.
The input terminals of the first source PCB 41A are electrically connected through an FFC (flexible flat cable) 43 to connection lines 44 formed on the control PCB 40. The second source PCB 41B is not connected to the control PCB 40. The source PCBs 41A, 41B are electrically connected to each other through the LOG lines 45 and through the source COFs 42A, 42B. Accordingly, the first source PCB 41A is supplied with the digital video data RGBodd, RGBeven, the data timing control signals, and the drive voltages from a single output port of the control PCB 40 through the connection lines 44 formed in the control PCB 40. Further, the second source PCB 41B is supplied with the digital video data RGBodd, RGBeven, the carry signal, the data timing control signals, and the drive voltages from the first source PCB 41A through the LOG lines 45 and through the source COFs 42A, 42B.
Provided in the control PCB 40 are a timing controller 31, an EEPROM 31a, and connection lines 44. The control PCB 40 may also have a circuit, such as a DC-DC converter (not shown), for generating the drive voltages of the liquid crystal display panel 30. The drive voltages generated in the DC-DC converter include, for example, a gate high voltage Vgh, a gate low voltage Vgl, a common voltage Vcom, a high level power supply voltage Vdd, a low level power supply voltage Vss, and a plurality of gamma reference voltages, which are divided between the high level power supply voltage and the low level power supply voltage. The gamma reference voltages are sub-divided into analog gamma compensation voltages, each of which corresponds to a respective gray level within the data ICs 32A up to the number of gray levels that can be expressed with the number of bits in the digital video data RGBodd, RGBeven. The gate high voltage Vgh and the gate low voltage Vgl represent a swing voltage of the scan pulse. The EEPROM 31a stores waveform option information for the timing control signals generated from the timing controller 31 for each mode and supplies the waveform information to the timing controller 31 in the pertinent mode in accordance with an input from a user. The timing controller 31 generates the timing control signals, which are different in each mode, in accordance with the waveform option information from the EEPROM 31a.
The connection lines 44 formed in the control PCB 40 connect the single output port 63 of the timing controller 31, shown in
In the above example, the source PCB is divided into two source PCBs—the first and second source PCBs 41A and 41B. However, the source PCB may be divided into more than two source PCBs, in which case additional sets of LOG lines and dummy lines may be employed.
The two port expansion part 34 divides the digital video data RGB inputted at a given input frequency (f) from a main system board (not shown) into odd-numbered pixel data RGBodd and even-numbered pixel data RGBeven. The two port expansion part 34 supplies the divided data RGBodd, RGBeven to the data modulator 35 at one half of the input frequency (f/2). The frequency is reduced to one half of the input frequency in order to reduce EMI (electromagnetic interference). The swing voltage of the data RGBodd, RGBeven outputted from the two port expansion part 34 is relatively high at a TTL (transistor to transistor) level of about 3.3V.
The data modulator 35 modulates the data RGBodd, RGBeven, for example, by a mini LVDS method. Then, the swing width of the data RGBodd, RGBeven from the two port expansion part 34 is decreased to between about 300 mV and about 600 mV. On the other hand, the frequency of the data is increased to twice the input frequency (2f) in accordance with a mini LVDS clock, shown for example in
The data modulator 35 generates the negative data signal (N) to be out-of-phase with the positive data signal (P), as shown in
The data timing control signals generated in the timing controller 31 are transmitted together with the digital video data RGBodd, RGBeven to the data ICs 32A, connected to the first source PCB 41A, through the single output port 63 of the timing controller 31, the connection lines 44, and the FFC 43. Further, the data timing control signals are transmitted to the data ICs 32B, connected to the second source PCB 41B, through the single output port 63 of the timing controller 31, the connection lines 44, the first source PCB 41A, the dummy lines 51 of the source COF 42, and the LOG lines 45 of the LCD panel 30.
After sampling the data subsequent to the start pulse the number of times substantially equal to the number of its own output channels, as shown in
The drive voltages generated from the DC-DC converter (not shown) mounted on the control PCB 40 are transmitted to the data ICs 32A, connected to the first source PCB 41A, through the output terminal of the DC-DC converter, the connection lines 44, and the FFC 43. Further, the drive voltages are transmitted to the data ICs 32B, connected to the second source PCB 41B, through the output terminal of the DC-DC converter, the connection lines 44, the first source PCB 41A, the dummy lines 51 of the source COF 42A, and the LOG lines 45 of the LCD panel 30.
The data restoring part 92 temporarily stores the odd-numbered pixel data RGBodd and the even-numbered pixel data RGBeven, which are divided by the timing controller 31. The data storing part 92 restores the data by demodulating the data RGBodd, RGBeven received from the timing controller 31 by employing a demodulation method corresponding to the modulation method employed by the data modulator 35 of the timing controller 31. For example, the data restoring part 92 generates ‘1’ when the positive data is at a high logic level and ‘0’ when the positive data is at a low logic level, as shown in
The shift register 91 shifts the sampling signal in accordance with the source sampling clock SSC. Further, the shift register 91 generates the carry signal when being supplied with the data with bits exceeding the number of latches of the first latch array 93. The shift register 91 of the first data IC (1st 32B) for sampling the first data detects the data supplied subsequently to the start pulse and the reset signal as the first data to be sampled.
The first latch array 93 samples the restored digital video data RGBeven, RGBodd from the data restoring part 92 in response to the sampling signals sequentially inputted from the shift register 91. The first latch array 93 latches the data RGBeven, RGBodd for pixels in one horizontal line and then simultaneously outputs the latched data.
The second latch array 94 latches the data inputted from the first latch array 93 and then outputs the latched digital video data RGBeven, RGBodd substantially simultaneously as the second latch array 94 of the other data ICs 32A for a logic low period of the source output enable signal SOE.
As shown in
The charge share circuit 96 shorts the adjacent data output channels for the logic high period of the source output enable signal SOE to output an average value of the adjacent data voltages as a charge share voltage, or supplies the common voltage Vcom to the data output channels for the logic high period of the source output enable signal SOE, thereby reducing a rapid change of the positive and negative data voltages. The output circuit 97 includes a buffer and minimizes a signal attenuation of the analog data voltages supplied to the data line D1 to Dk.
As can be seen in
In order to compensate for the line resistance RLOG on the LOG lines 45, the LCD device according to the first embodiment of the present invention determines the resistance value of the resistors RTA, RTB, which are connected between the positive and negative input terminals of the data ICs 32A, 32B, respectively, as detailed below.
The voltage (VswingA) of the mini LVDS signal supplied to the data IC 32A, which is not affected by the line resistance RLOG on the LOG lines 45, is as follows:
VswingA=((RDIV/2)/((RDIV/2)+RDRIVER+RS))×((RTB/2)/((RTB/2)+REQ))×Vcco. [Mathematical Formula 1]
The voltage (VswingB) of the mini LVDS signal supplied to the data IC 32B, which is affected by the line resistance RLOG on the LOG lines 45, is as follows:
VswingB=((RDIV/2)/((RDIV/2)+RDRIVER+RS))×((RTA/2)/((RTA/2)+REQ+RLOG))×Vcco. [Mathematical Formula 2]
In Mathematical Formulas 1 and 2, RDRIVER represents an internal resistance within the timing controller 31, and Vcco represents a data transmission drive voltage of the timing controller 31.
In order to avoid the potential deviation between the mini LVDS signal input voltages supplied to the data IC 32A and data IC 32B, the mini LVDS signal input voltage VswingA, which is not affected by the resistance RLOG, should be the same as the mini LVDS signal input voltage VswingB, which is affected by the resistance RLOG, as follows:
VswingA=VswingB=(RTB/(RTB+2REQ))=(RTA/(RTA+2REQ+2RLOG)). [Mathematical Formula 3]
Accordingly, the resistor RTA connected between the positive and negative signal input terminals of the data IC 32A connected to the first source PCB 41A is determined to have a resistance value as follows:
RTA=(RTB(REQ+RLOG))/REQ [Mathematical Formula 4]
In an LCD device according to the second embodiment of the present invention, some of the components and functions of the control PCB in the related art LCD devices are removed from the control PCB and are instead integrated into the system board. Hereinafter, to the extent that the components of the LCD device according to the first embodiment of the present invention are also employed in the LCD device according to the other embodiments of the present invention, such components are given the same reference numerals, and the detailed description of such components provided in connection with the first embodiment above may not be repeated.
As shown in
The interface circuit 62 receives various kinds of video data from such external devices as a DVD player, VCD and HDD, a TV set-top box, and the like and supplies the video data to the graphic processing circuit 64.
The graphic processing circuit 64 includes the analog to digital converter 64a, scaler 64b, and an image processor 64c. The graphic processing circuit 64 converts the video data from the interface circuit 62 to be compatible with the LCD panel 30 and generates the timing signals that are compatible with the resolution of the LCD panel 30 based on the video data. The graphic processing circuit 64 supplies the converted digital video data and the timing signals to the timing controller 31 via the wire cable 68.
The analog to digital converter 64a coverts the analog video data supplied from the interface circuit 62 into digital video data. The scaler 64b changes the resolution of the digital video data from the analog to digital converter 64a to be compatible with the resolution of the LCD panel 30. Further, in order to adjust one or both of the response characteristics and contrast of the LCD panel 30, the scaler 64b also modulates the digital video data using a predetermined compensation. To do so, the scaler 64b includes one or both of a first modulator for enhancing the response characteristics of the LCD panel 30 and a second modulator for emphasizing the contrast of the LCD panel 30.
The first modulator, as shown for example in
The first frame memory 111 and the second frame memory 102 alternate storing the digital video data (RiGiBi) by frame unit and outputting the stored data. As a result, they supply the data Fn−1 for the previous frame, or the (n−1)-th frame, to the look-up table 113. The look-up table 113 is a memory including a number of predetermined first compensation values. The look-up table 113 compares the data Fn for the current frame, or the n-th frame, with the data Fn−1 for the previous or (n−1)-th frame received from the first and second frame memories 111 and 112. The look-up table 113 outputs a first compensation corresponding to the result of the comparison as a modulated digital video data ODC(RGB).
For example, when the digital video data Fn for a given pixel in the present or n-th frame is higher than the digital video data Fn−1 for that pixel in the previous or (n−1)-th frame, the first modulator modulates the digital video data with a larger value than the data Fn for the present frame using one of the predetermined first compensation values. On the other hand, if the digital video data Fn for a given pixel in the present or n-th frame is lower than the digital video data Fn−1 for that pixel in the previous or (n−1)-th frame, the first modulator modulates the digital video data with a smaller value than the data Fn for the present frame. Further, if the data Fn for the present frame is the same as the data Fn−1 for the previous frame, the first modulator outputs the data Fn for the present frame as is without modulating it.
The first modulator may employ any one of the modulating methods described in the Korean Patent Application No. 10-2001-0032364, No. 10-2001-0057119, No. 10-2001-0054123, No. 10-2001-0054124, No. 10-2001-0054125, No. 10-2001-0054127, No. 10-2001-0054128, No. 10-2001-0054327, No. 10-2001-0054889, No. 10-2001-0056235, No. 10-2001-0078449, and No. 10-2002-0046858, which are incorporated herein by reference.
The second modulator, as shown for example in
To perform the above procedure, the second modulator may, for example, includes a brightness/color separator 201, a delaying part 202, a brightness/color mixer 203, a histogram analyzer 205, a data processor 204, a back light controller 206, and an inverter 207, as shown in
The histogram analyzer 205 receives the brightness component Y from the brightness/color separator 201, counts the number of each gray scale in the video data and makes a histogram with an accumulated distribution graph, as shown in
The data processor 204 selectively modulates the brightness component Y of the input video data based on the result of the histogram analysis from the histogram analyzer 205 and the second compensation from the memory. The data processor 204 then outputs modulated brightness component YM, whose contrast is selectively emphasized.
The delaying part 202 delays the color components U and V until the modulated brightness component YM is generated by the data processor 204 to synchronize the delayed color components UD and VD with the modulated brightness component YM in order to have them input to the brightness/color mixer 203 substantially at the same time. Based on the modulated brightness component YM and the delayed color components UD and VD, the brightness/color mixer 203 calculates and outputs the modulated digital video data AI(RGB).
The backlight controller 206 receives the results of the histogram analysis and the determined position of the digital video data RiGiBi on the histogram from the histogram analyzer 205. Based on the information received from the histogram analyzer 205, the back light controller 206 generates various dimming control signals Dim to control the brightness of the backlight which radiates light to the LCD panel displaying the modulated digital video data AI(RGB), whose contrast has been emphasized as described above.
The inverter 207 receives the dimming control signal Dim from the backlight controller 206. Based on the dimming control signal, the inverter 207 then separately controls the duty ratio of the driving AC power supplied to each light source of the backlight unit, thereby separately controlling the brightness of each individual light source in accordance with the brightness of the video data RiGiBi.
The second modulator may employ any one of modulating methods described in the Korean Patent Applications No. 10-2003-0099334, No. 10-2004-0030334, No. 10-2003-0041127, No. 10-2004-0078112, No. 10-2003-0099330, No. 10-2004-0115740, No. 10-2004-0049637, No. 10-2003-0040127, No. 10-2003-0081171, No. 10-2004-0030335, No. 10-2004-0049305, No. 10-2003-0081174, No. 10-2003-0081175, No. 10-2003-0081172, No. 10-2003-0080177, No. 10-2003-0081173, and No. 10-2004-0030336, which are incorporated herein by reference.
The image processor 64c, shown in
The DC-DC converter 38 generates driving voltages required to drive the LCD panel 30. The driving voltages generated at the DC-DC converter 38 include a gate high voltage (Vgh), a gate low voltage (Vgl), a common voltage (Vcom), a high-level power voltage (Vdd), a low-level power voltage (Vss), and a plurality of gamma reference voltages between the high-level power voltage (Vdd) and the low-level power voltage (Vss). The gamma reference voltages are divided within the data ICs 32A and 32B according to the number of gray scales that can be provided with the number of bits in the digital video data (RGBodd and RGBeven). Accordingly, the gamma voltages are subdivided into analog gamma compensation voltages, each of which corresponds to a respective gray scale. The gate high voltage (Vgh) and the gate low voltage (Vgl) represent a swing voltage of the scanning pulse. These driving voltages are supplied to the signal wires 46 on the control PCB 40 via the wire cable 68.
The driving voltages generated from the DC-DC converter 38 mounted on the system board 60 are then transmitted to the first data ICs 32A connected to the first source PCB 41A via the one-port linking lines 44 and the FFC 43. Also, the driving voltages are transmitted to the second data ICs 32B connected to the second PCB 41B via the first source PCB 41A, the dummy lines 51 of the source COF 42A, and the LOG lines 45 of the LCD panel 30 (see, e.g.,
As described above, in the second embodiment of the present invention, some elements of the control PCB in the related art LCD device are integrated into the system board. For example, in the second embodiment of the present invention, the system board 60 includes a graphics processing circuit that modulates the digital video data with a predetermined compensation in order to adjust one or both of the response characteristics and contrast of the LCD panel 30. The system board 60 also includes the DC-to-DC converter 38 that generates driving voltages required to drive the LCD panel 30. Therefore, the LCD device according to the second embodiment of the present invention has a control PCB with a significantly reduced size.
In the third embodiment of the present invention, all of the elements of the control PCB in the related art device are integrated into the system board 60. As shown in
The detailed description of the elements of the integrated system board 60, shown in
The LCD device according to the fourth embodiment of the present invention employs compensation resistors Rc as shown in
As shown in
On the other hand, the second data ICs 32B have substantially the same configuration as the first data ICs 32A except for the gamma compensation voltage generator 98. Although not shown in the drawings, the gamma compensation voltage generator of the second data ICs 32B each include voltage dividers having resistor strings and do not include the compensation resistors Rc connected in parallel to the respective resistor strings.
The LOG lines 45 are formed on the lower substrate of the LCD panel 30 to couple the source COF 42, coupled to the first source PCB 41A and adjacent to the second source PCB 41B, and the source COF 42, coupled to the second source PCB 41B and adjacent to the first source PCB 41A. The LOG lines 45 transmit between these two source COFs 42 the data timing control signals and drive voltages.
As discussed above, the LOG lines 45 have a relatively high line resistance as described above, and the sum of the line resistance is represented as resistor Rlog in
In order to prevent or reduce this difference in the gamma compensations voltages, the fifth embodiment of the present invention employs first and second dummy lines 51a and 51b having different widths. As shown in
As shown in
Though not separately depicted, the second data ICs 32B may have substantially the same configuration as that of the first data ICs 32A.
As shown in
The input terminals of the first source PCBs 41A are connected to two-port connecting lines 44, which are formed on the control PCB 40, via first FFC 43A. The input terminals of the second source PCBs 41B are connected to the two-port connecting lines 44 via second FFC 43B.
The control PCB 40 includes the two-port connecting lines 44 and such circuits as the timing controller 31, an EEPROM 31a, and a DC-DC converter (not shown) that generates driving voltages for the LCD panel 30. The driving voltages generated at the DC-DC converter may include a gate high voltage Vgh, a gate low voltage Vgl, a common voltage Vcom, a high-level power voltage Vdd, a low-level power voltage Vss, and a plurality of gamma reference voltages divided between the high-level power voltage Vdd and the low-level power voltage Vss. The gamma reference voltages are further divided by the data ICs 32A, 32B into analog gamma compensation voltages, each of which corresponds to a gray scale. Thus, the number of generated gamma compensation voltages substantially equals the number of gray scales that can be obtained with the number of bits in the digital video data RGBodd and RGBeven. The gate high voltage Vgh and the gate low voltage Vgl represent a swing voltage of the scanning pulse.
The EEPROM 31a stores waveform option information for the timing control signals generated from the timing controller 31 for each mode and supplies the waveform information to the timing controller 31 in the pertinent mode in accordance with an input from a user. The timing controller 31 generates the timing control signals, which are different in each mode, in accordance with the waveform option information from the EEPROM 31a.
The two-port connecting lines 44, which are formed on the control PCB 40, are patterned in a “Y” shape to connect a single output port 63 of the timing controller 31 (shown in
As shown in
On the other hand, right data RGBodd, RGBeven, which are also modulated with the mini LVDS method, the RSDS method, or other appropriate methods by the timing controller 31, are transmitted to the second data ICs 32B. The second data ICs 32B are connected to the second source PCB 41B, which in turn is connected to the single output port 63 of the timing controller 31 via the second FFC 43B and the two-port connecting line 44. If the source COFs 42 are coupled to the data pads at the top edge of the LCD panel 30, the right data RGBodd, RGBeven represent the image to be displayed on the left half of the LCD panel 30. Alternatively, if the source COFs 42 are coupled to the data pads at the bottom edge of the LCD panel, the right data RGBodd, RGBeven represent the image to be displayed on the right half of the LCD panel 30.
The timing control signals generated from the timing controller 31 are also transmitted to the first data ICs 32A, connected to the first source PCB 41A, via the single output port 63 of the timing controller 31 and the first FFC 43A. Also, the timing control signals are transmitted to the second data ICs 32B, connected to the second source PCB 41B, via the single output port 63 of the timing controller 31 and the second FFC 43B.
The rightmost second data IC 32B samples the first data subsequent to the start pulse the number of times substantially equal to the number of its own output channels, as shown for example in
The driving voltages from the DC-DC converter (not shown), which may be mounted on the control PCB 40 or the system board, are simultaneously supplied to all data ICs 32A, 32B via the two-port connecting line 44, and the first and second FFCs 43A and 43B, respectively.
As shown in
The input terminals of the first source PCB 41A are electrically connected to the system board 60 via the first output terminal 43A of the Y-shaped FFC (Flexible Flat Cable) and the common input terminal 43C of the Y-shaped FFC. The input terminals of the second source PCB 41B are electrically connected to the system board 60 via the second output terminal 43B of the Y-shaped FFC and the common input terminal 43C of the Y-shaped FFC.
The system board 60 may include such circuits as the timing controller 31, an EEPROM 31a, and a DC-DC converter 38 that generates driving voltages for the LCD panel 30. The system board 60 may also include the interface circuit 62 for receiving various video data from the external appliances. Further, the system board 60 may include the graphic processing circuit 64 having an analog-to-digital converter, a scaler for changing the resolution of the input data to be compatible with the resolution of the LCD panel 30, and an image processing circuit for signal interpolation and image processing. A detailed description of the structure and operation of the system board 60 and the components of the system board are provided above in connection with other embodiments of the present invention and are not repeated.
As shown in
As shown in
On the other hand, right data RGBodd, RGBeven, which are also modulated with the mini LVDS method, the RSDS method, or other appropriate methods by the timing controller 31, are transmitted to the second data ICs 32B. The second data ICs 32B are connected to the second source PCB 41B, which in turn is connected to the single output port 63 of the timing controller 31 via the second output terminal 43B and the common input terminal 43C of the Y-shaped FFC. If the source COFs 42 are coupled to the data pads at the top edge of the LCD panel 30, the right data RGBodd, RGBeven represent the image to be displayed on the left half of the LCD panel 30. Alternatively, if the source COFs 42 are coupled to the data pads at the bottom edge of the LCD panel, the right data RGBodd, RGBeven represent the image to be displayed on the right half of the LCD panel 30.
The timing control signals generated from the timing controller 31 are also transmitted to the first data ICs 32A, connected to the first source PCB 41A, via the single output port 63 of the timing controller 31, the single input terminal 43C of the Y-shaped FFC, and the first output terminal 43A of the Y-shaped FFC. Also, the timing control signals are transmitted to the second data ICs 32B, connected to the second source PCB 41B, via the single output port 63 of the timing controller 31, the single input terminal 43C of the Y-shaped FFC, and the second output terminal 43B of the Y-shaped FFC.
The rightmost second data IC 32B samples the first data subsequent to the start pulse the number of times substantially equal to the number of its own output channels, as shown for example in
The driving voltages generated from the DC-DC converter 38 mounted on the system board 60 are transmitted to the first data ICs 32A, connected to the first source PCB 41A, via the output terminal 73 of DC-DC converter 38, the common input terminal 43C of the Y-shaped FFC, and the first output terminal 43A of the Y-shaped FFC. The driving voltages are also transmitted to the second data ICs 32B, connected to the second source PCB 41B, via the output terminal 73 of the DC-DC converter 38, the common input terminal 43C of the Y-shaped FFC, and the second output terminal 43B of the Y-shaped FFC.
As described above, the LCD device according to one aspect of the present invention divides the source PCB into a plurality of smaller source PCBs. Further, since the timing controller employs a single output port, the timing controller has a smaller number of output pins, and the size of the control PCB may be reduced. In addition, the LCD device according to the present invention may remove one of the FFCs and instead employ the LOG lines formed in the LCD panel and dummy lines on COFs, thereby simplifying the connections between the control PCB and the source PCBs and reducing the number of parts needed to build the LCD device.
Further, the LCD device thereof according to another aspect of the present invention respectively connects compensation resistors to data ICs connected to the source PCB which receives the drive signals from the control PCB directly through an FFC. This reduces or prevents potential discrepancy between the gamma compensation voltages from the source PCB receiving the driving voltages directly through an FFC and those from the source PCB receiving the driving voltages via the LOG lines.
In addition, the dummy lines in the source COF or the source TCP for transmitting the drive voltages may be formed wider than the other dummy lines for transmitting the data timing control signals. Likewise, the LOG lines for transmitting the drive voltages may be formed wider than the other LOG lines for transmitting the data timing control signals. As a result, the drop in the drive voltages caused by the line resistance on the LOG lines can be minimized or substantially prevented such that the discrepancy in the gamma compensation voltages from different PCBs is reduced or prevented.
Also as explained above, in the LCD device according to another aspect of the present invention, the elements and functions of the control PCB are integrated into the system board. Further, the timing controller employs a single output port, thereby reducing the number of output pins of the timing controller and reducing the size of the system board. As a result, the cost of manufacturing LCD devices can be reduced, and the manufacturing time shortened. Further, the LCD devices may be made thinner than the related art devices.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
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| 10-2007-0026070 | Mar 2007 | KR | national |
| 10-2007-0030323 | Mar 2007 | KR | national |
| 10-2007-0030332 | Mar 2007 | KR | national |
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| 10-2007-0030454 | Mar 2007 | KR | national |
| 10-2007-0046113 | May 2007 | KR | national |
| 10-2007-0046126 | May 2007 | KR | national |
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| Number | Date | Country |
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| Number | Date | Country | |
|---|---|---|---|
| 20080225036 A1 | Sep 2008 | US |
