Logic analyzer having search and comparison capabilities

Abstract

A logic analyzer is disclosed which displays at least an input logic signal on a cathode ray tube, controls a cursor position on the cathode ray tube and obtains a relationship between a predetermined phenomenon included in the input logic signal and the cursor position. In a search mode, the predetermined phenomenon is a search word or a glitch. In a compare mode, the predetermined phenomenon is a reference logic signal.

Description

BACKGROUND OF THE INVENTION

The subject matter of the present invention pertains to a logic analyzer having search and comparison capabilities.

In various kinds of electronic apparatus, logic techniques are increasingly popular as a result of developments of microprocessors and computers. Oscilloscopes, logic probes and logic analyzers are utilized for developing, calibrating and trouble-shooting an electronic apparatus using these logic techniques. A logic analyzer is especially ideal for use as a measurement instrument of such electronic apparatus, because it can store multi-channel input logic signals (data) in a memory, such as a random access memory (RAM) and display the data stored in the memory on a display means, such as a cathode ray tube (CRT), so that the displayed data (before a trigger signal occurence) may be measured. There are two display modes used by a logic analyzer; one is a timing display mode for displaying the logic signals as signal waveforms; the other is a state display mode for displaying the stored data as characters (alphanumerics) of words, such as binary, octal and hexadecimal. In the state display mode, data stored in only selected addresses of the memory are displayed. All of the data stored in the memory cannot be displayed simultaneously because of the relationship between a display area and the sizes of the characters to be displayed.

Conventional logic analyzers have many functions, and one of them is a search function (or search mode). This mode is frequently selected especially in the state display mode, wherein a search word set by an operator is detected from the data stored in the memory. The searched word and the memory address thereof are displayed on a first line, and a predetermined number of words followed by this address are displayed on the following lines thereby constituting a state table. However, since all the data stored in the memory cannot be displayed in the state display mode as described hereinbefore, it is difficult to know a total number of the search words included in all the data and a relation between the total number and the search words displayed on the display means. As a result, measurement is troublesome. On the other hand, the search mode is not available in the timing display mode, so that it is troublesome to measure a timing relation among a plurality of logic signals with respect to a desired word.

Another function of a conventional logic analyzer is the detection of a glitch (a narrow width pulse signal which affects the operation of logic circuits). The glitch can be detected if a clock frequency is increased when storing the input logic signal in the memory. However, the glitch is detected commonly by a glitch detector consisting of logic circuits, such as latch circuits or the like, since the maximum clock frequency is limited by the characteristics of the memory. The detected glitch is displayed as a pulse of one bit width in the timing display mode (the glitch intensity is sometimes modulated). It is difficult to know a total number of the glitches in all the data stored in the memory and a relationship between the total number and a glitch displayed on the display means. As a result, measurement is inconvenient. Moreover, conventional logic analyzers cannot display the glitch in the state display mode. Therefore, it cannot be determined whether or not the displayed data includes the glitch.

The conventional logic analyzers have a further function, a comparison function (or comparison mode). This function is especially used in the state display mode, wherein the input logic signals stored in a first memory are compared with reference logic signals stored in a second memory and one or both of the input and reference logic signals are displayed on the display means. Conventional logic analyzers modulate the intensity of different parts of the input and reference logic signals, invert the different parts (inversion between white and black) or add markers to the different parts for distinguishing between the different parts of the input and reference logic signal from other parts thereof (easy measurement). Since all the data stored in the memory cannot be displayed simultaneously in the state display mode as described hereinbefore, it is difficult to know a total number of the different (or other) parts of the input and reference logic signal included on the display means, namely, a relationship between all the data and the displayed parts. Thus, measurement is troublesome.

SUMMARY OF THE INVENTION

According to a logic analyzer of the present invention, a search phenomenon, such as a word or a glitch, is input via input means, such as a keyboard, and processing means, such as a central processing unit (CPU), calculates a total number of the search phenomenon included in stored data. In addition, the CPU obtains a relationship between the total number and a cursor position controlled by a cursor control means, such as the keyboard. The relationship is displayed on a CRT. Moreover, the CPU compares the input logic signals with the reference logic signals, counts the total number of the different (or other) parts (words), obtains a relationship between the total number and the cursor position, and displays the comparison results on the CRT. The different or other parts may be regarded as the search phenomenon.

It is therefore one object of the present invention to provide an improved logic analyzer which is free from the disadvantages of the aforementioned prior art.

It is another object of the present invention to provide a logic analyzer which obtains a relationship between a total number of a predetermined phenomenon included in a stored input logic signal and a cursor position on a display means.

It is a further object of the present invention to provide a logic analyzer which obtains a relationship between a total number of a predetermined word included in a stored input logic signal and a cursor position on a display means.

It is an additional object of the present invention to provide a logic analyzer which obtains a relationship between a total number of glitches included in a stored input logic signal and a cursor position on a display means.

It is another object of the present invention to provide a logic analyzer which counts a total number of different or other parts of input and reference logic signals, and obtains a relationship between the total number and a cursor position displayed on a display means.

It is a further object of the present invention to provide a logic analyzer which obtains a relationship between a total number of a predetermined phenomenon included in a stored input logic signal and a cursor position on a display means when operating in a timing display mode and a state display mode.

Other objects, advantages, and features of the present invention will become apparent to those having ordinary skill in the art from a reading of the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a logic analyzer in accordance with the present invention;

FIG. 2 illustrates the contents of a memory circuit 28 used in FIG. 1;

FIG. 3 illustrates a display of a word search mode when in a timing display mode according to the present invention;

FIGS. 4A-4E in combination illustrate flow charts for explaining the present invention;

FIG. 5 illustrates another display of the word search mode when in the timing display mode according to the present invention;

FIG. 6 illustrates a display of a glitch search mode when in the timing display mode according to the present invention;

FIG. 7 illustrates a display of the word search mode when in a state display mode according to the present invention;

FIG. 8 illustrates a display of the glitch search mode when in the state display mode according to the present invention;

FIG. 9 illustrates a display of the glitch search mode when in the state display mode according to the present invention;

FIG. 10 illustrates a display of the word compare mode in the state display mode according to the present invention; and

FIG. 11 illustrates a display of a pattern compare mode when in the state display mode according to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Referring now to FIG. 1, there is shown a block diagram of a logic analyzer according to the present invention. Probe 10 has eight tips for detecting eight channel input logic signals from a circuit to be measured. The eight channel logic signals from probe 10 are applied to comparator/glitch detector 12, wherein the comparator converts the levels of the input logic signals to a proper logic level for each block of FIG. 1 (e.g. TTL level), and the converted signals are applied to data memory circuit 14, consisting of high speed RAMs or the like, and to trigger circuit 16 including a word recognizer (circuit for detecting a predetermined word) and a counter. The glitch detector of block 12 detects glitches from the input logic signals, and the detected glitches are applied to glitch memory circuit 18 consisting of high speed RAMs. The glitch detector may be a conventional circuit consisting of latch circuits, gates, etc. Blocks 14, 16, and 18 are connected to bus 20 (including data, address and control buses). Start/stop control circuit 22 causes memory circuits 14 and 18 to commence acquisitions in response to an instruction from bus 20, and stops the acquisitions in response to an output from trigger circuit 16. Central processing unit (CPU) 24 is, for example, a type Z80A microprocessor, and acts as a processing means. The Z80A is fully disclosed in "Z80/Z80A CPU Technical Manual" and "Z8400, Z80 CPU Product Specification" published by Zilog. Read only memory (ROM) 16 is a memory circuit for firmware to store data processing sequences of CPU 24, and RAM 28 is a memory means for acting as a temporary memory of CPU 24 and including a display RAM area. ROM 26 and RAM 28 are connected to bus 20. Keyboard 30 is connected to bus 20, and includes a plurality of keys for controlling a cursor position, inputting a search phenomenon in a search mode, and other control and input operations. Thus, keyboard 300 acts as an input means and a cursor control means. Display control circuit 32 connected to bus 20 controls the display of data on a display means 34, such as a raster scan type CRT by generating an intensity signal and horizontal and vertical scanning signals in accordance with the data stored in the display RAM area of RAM 28. Clock pulse generator 36 supplies a clock pulse to blocks 14, 16 and 18, the clock frequency being controlled in accordance with an instruction from bus 20. The clock frequency for blocks 24, 26, 28 and 30 is fixed to, for example, 4 MHz (is the CPU is the Z80A type).

For storing the input logic signals, an operator sets the clock frequency, a trigger word and a clock number for a trigger delay via keyboard 30. These set data are stored in a first area of RAM 28 (refer FIG. 2 showing the contents of RAM 28) through bus 20 and CPU 24, and are used to set trigger circuit 16 and clock pulse generator 36. When a write start instruction is applied from keyboard 30 to start/stop control circuit 22 through bus 20 and CPU 24, circuit 22 switches data memory circuit 14 and glitch memory circuit 18 to a write mode to start a write operation. As described hereinbefore, the data and glitch components of the input logic signals from probe 10 are respectively and sequentially stored in different addresses of memory circuits 14 and 18 through block 12. The addresses of memory circuits 14 and 18 are determined by an address signal from an address generator (not shown). It should be noted that the appointed addresses of memory circuits 14 and 18 correspond to each alternately occuring (i.e. every other) clock pulse. After the word recognizer in trigger circuit 16 detects the trigger word from the data components of the input logic signals, the counter counts a predetermined number of the clock and generates an output signal. In response to this output signal, start/stop control circuit 22 stops the write operations of memory 14 and 18. Thus, memory circuits 14 and 18 complete the storage of the logic signal to be measured.

When a display instruction is input via keyboard 30 in search mode or glitch mode, CPU 24 transfers the contents of memory circuits 14 and 18 to second and third areas of RAM 28 respectively in accordance with the firmware of ROM 28. The selections of the display modes (timing or state display mode) and the display area (selecting a display part of the stored logic signal to be measured) are made via keyboard 30, and information of the selected display mode and display area are stored in the first area of RAM 28 through bus 20 and CPU 24. Assuming that the selected display mode is the timing display mode, CPU 24 converts the data information in the second area of RAM 28 corresponding to the selected display area into FONT information of logic waveforms, converts the glitch information in the third area into ATTRIBUTE information, and stores the FONT and ATTRIBUTE information in the display RAM area of RAM 28 in accordance with the firmware of ROM 26. Display control circuit 32 is conventional type including a ROM for storing various patterns of logic waveforms and characters' (alphanumerics') patterns, a shift register for converting the parallel output from the ROM to a serial signal to generate a Z-axis (intensity) signal, and vertical and horizontal scan signal generators. Display control circuit 32 reads the contents of the display RAM area of RAM 28 repeatedly to display logic waveforms on CRT 34 as shown in FIG. 3. In FIG. 3, "A0" through "A7" at the left side indicate the channel number of logic signal and correspond to each tip of probe 10. These channel numbers are displayed similarly to the logic waveforms under control of the firmware of ROM 26. Characters surrounded by frames in the drawings indicate an inversion between black and white displays, the inversion being controlled by the ATTRIBUTE information stored in the display RAM area of RAM 28. In a bar graph consisting of crosshatched parts and a white part displayed at the top right side of FIG. 3, the length of the bar graph corresponds to all the stored logic signals to be measured (capacities of the second and third areas in RAM 28), and the white part corresponds to the present display area. A relationship between all the logic signals and the display may be determined by reference to this bar graph which is displayed in accordance with a method disclosed in Japanese Published Unexamined Patent Application 56-24579 corresponding to U.S. Pat. Ser. No. 172,107.

In the display of FIG. 3, "C" and seven black squares arranged longitudinally at the center portion indicate a cursor, and the position thereof is controlled by keyboard 30. When keyboard 30 determines the address of the cursor position with respect to the displayed waveforms, the cursor position information is stored in the first area of RAM 28 through bus 20 and CPU 24. CPU 24 stops the FONT and ATTRIBUTE information of the cursor in the corresponding addresses of the display RAM area of RAM 28 in accordance with the cursor position information under control of the firmware of ROM 26. Since display control circuit 32 reads the contents of the display RAM area repeatedly, the cursor is displayed on CRT 34. "10110001" positioned longitudinally at the right side of FIG. 3 indicates logic levels of each logic signal at the cursor position (cursor word). This word is useful to confirm the cursor word, when a channel number of the displayed waveforms is large or a pulse width (a period between the rising and falling edges) is narrow. The cursor word is displayed by CPU 24 in accordance with the firmware of ROM 26 as follows. Firstly, CPU 24 reads the data at the cursor position from the data information stored in the second area of RAM 28 in response to the cursor position information stored in the first area of RAM 28. CPU 24 judges "1" and "0"0 of the read-out data, and stores FONT information of the words (1 and 0) in the display RAM area of RAM 28 for displaying on CRT 34 simultaneously with other information.

If the cursor is moved by keyboard 30, the cursor position information in the first area of RAM 28 changes and the aforementioned operation is repeated. If a signal from the keyboard 30 instructs the movement of the cursor toward the outside of the displayed waveforms after the cursor is positioned at the end of the displayed waveforms, the displayed waveforms are moved, however the position of the cursor remains fixed at the end of the displayed waveforms. Therefore, the cursor is substantially moved. For example, if the cursor is instructed to further move to the right after the cursor is moved to the right end of the displayed waveforms, the displayed waveforms are moved to the left, i.e., the displayed waveforms are erased from the left end in accordance with the cursor movement value, and new waveforms appear from the right end. In this instance, the white part of the bar graph is moved. This operation is generally known as a scroll mode. In the scroll mode, the displayed window area is determined by the cursor, and CPU 24 may read all the logic signals of a new display area from the second and third areas of RAM 28 for repeating the above described display operation. However, it is effective to shift the waveform information in the display RAM area of RAM 28 by a number of the addresses corresponding to the cursor movement value, read the new waveform information corresponding to the value lacked by shifting (the end part of the waveform information is erased by shifting) from the second and third areas of RAM 28, and store the new waveform information in the display RAM area under control of CPU 24.

The search mode of the present invention will be discussed, which follows the above description. When the search word mode is selected via keyboard 30, CPU 24 displays "SRCH" (meaning the search mode) at the top left portion of the display screen by a use of the display RAM area in accordance with the firmware of ROM 26. If the search phenomenon is a word, "WD" (meaning the word) is displayed under "SRCH". The search word is input by keyboard 30 and stored in the first area of RAM 28 through bus 20 and CPU 24. In this embodiment, the search word is "01011000" and converted into the character information (FONT and ATTRIBUTE information) to be stored in the display RAM area for displaying as shown in FIG. 3.

The following operations will be discussed by reference to flow charts shown in FIGS. 4A through 4E. The operations are controlled by CPU 24 under control of the firmware of ROM 26. CPU 24 counts a total number of the selected phenomena (or parts, words, different from reference logic signals) stored in the second or third area of RAM 28 at step 50 which is shown in FIG. 4C in detail. Of course, the present mode is the search word mode, however, it should be noted that the flow charts of FIGS. 4A through 4E are available to all the search word, search glitch and comparison modes. In FIG. 4C, CPU 24 clears a fourth area of RAM 28 at step 52, and sets a memory address of the first area for storing the total number to zero at step 54. In step 56, CPU 24 compares the search word stored in the first area of RAM 28 with the data information stored in each address of the second area, and stores "1" in a corresponding address of the fourth area if the data information is the same as the search word. If the data information and the search word are different from each other, the data of the fourth area is not changed, i.e, "0" remains in the corresponding address of the fourth area. CPU 24 counts the total number of the search word stored in the second area at step 56 by counting one when the data information corresponds to the search word. The counted total number is stored in the first area of RAM 28. In FIG. 4C, "S.R." means the search phenomenon (word or glitch) or the reference logic signal. The total number is two hundred in this example, and is displayed as "200" on CRT 34 by converting it into the character information to be stored in the display RAM area in step 58.

Returning to FIG. 4A, CPU 24 judges whether the total number is zero or not at step 60. Step 84 of FIG. 4B is followed through 62 if so, and step 64 is followed if not so. In step 62, CPU 24 displays "0" on CRT 34 as a search number that is a number of the search word stored in the addresses of the second area of RAM 28 on or before the cursor position address. The cursor position address may be obtained from the cursor position information in the first area. In step 64, CPU 24 sets the search number to zero and further sets a pointer to zero. CPU 24 judges whether the pointer position is equal to the cursor position in step 66, wherein step 74 of FIG. 4B is led if so, and step 68 is led if not so. In step 68, CPU 24 judges whether the contents of the fourth area of RAM 28 corresponding to the pointer position is one or not. If the pointer's contents is "1", i.e., if the data information at the pointer position is the same as the search word, step 70 is followed. If the pointer's contents is not "1", i.e., if the data information at the pointer position is different from the search word, step 72 is followed. In step 70, CPU 24 adds one to the search number, and step 72 is led. In step 72, CPU 24 increases the pointer position by one and returns to step 66. In other words, CPU 24 counts the search number on or before the cursor position by counting "1" in the fourth area of RAM 28 through steps 66-72.

Referring to FIG. 4B, CPU 24 judges the search number counted through steps 66-72 is zero or not in step 74, wherein step 76 or 78 are followed if so or not so respectively. In step 76, CPU 24 displays ".dwnarw.1" (state display mode) or ".fwdarw.1" (timing display mode) on CRT 34, and the display means that the first search word is positioned after the cursor position. After step 76, this mode ends. In step 78, CPU 24 judges whether the data information at the cursor position is the search word (S.R.) and leads to step 80 or 82. When the cursor positions' data (cursor word) corresponds to the search word, CPU 24 displays the search number on CRT 34 in step 80 and leads to step 84. When the cursor word differs from the search word, CPU 24 displays ".uparw.(search number)" (state display mode) or ".rarw.(search number)" (timing display mode) on CRT 34 in step 82 and leads to step 84. This display indicates that the search word at the search number is located before the cursor position. In the embodiment of FIG. 3, there are 113 search words prior to the cursor, and the 114th search word is positioned after the cursor. ".rarw.113" indicates that the 113rd search word is positioned before the cursor, and the corresponding character information is stored in the display RAM area by CPU 24. When the cursor position corresponds to the 114th search word by sequentially moving the cursor to the right via keyboard 30, CRT 34 displays as shown in FIG. 5, where "SRCH=114/200" indicates that the cursor position corresponds to the 114th of the 200 search words. It should be noted that the arrow is erased, because CPU 24 counts the search words on and before the cursor position, and detects the cursor position is on the search word. After the detection, CPU 24 changes the ATTRIBUTE of the character information of the cursor word stored in the display RAM area for reversing the black and white of the cursor word display. This reverse operation is controlled as follows.

Returning to FIG. 4B, CPU 24 judges whether the present mode is the timing display mode or not in step 84. If the timing display mode is selected, step 86 is followed (this step is shown in FIG. 4D). If the timing display mode is not selected (the state display mode is selected), step 88 shown in FIG. 4E is followed. After step 86 or 88, the mode ends.

The reverse operation in the timing display mode will be discussed by reference to FIG. 4D. In step 90, CPU judges whether the code in the fourth area of RAM 28 at the cursor position is "1" or not. If the code is "1", i.e., if the data at the cursor position is the search word, step 92 is followed. If not so, i.e., if the search word is not located on the cursor position, step 94 is followed wherein CPU 24 displays the cursor word by reading the data information in the second area at the cursor position and outputs a normal code as the ATTRIBUTE. Thus, the cursor word is displayed normally as shown in FIG. 3. After step 94, CPU 24 returns to the sequence of FIG. 4B. In step 92, CPU 24 judges whether the present mode is the glitch search mode or not. If the glitch search mode is selected, CPU 24 processes step 96 and returns to the main routine. If the word search mode is selected, CPU 24 outputs a reverse code as the ATTRIBUTE for reversing the cursor word display in step 98 as shown in FIG. 5. After step 98, CPU 24 returns to the main routine.

Therefore, the logic signal measurement becomes very easy because of the relationship between the cursor position and the total number of the search word in the logic signals stored in the memory means. Moreover, the search function is available in the timing display mode, so that the measurement is further improved. If the search word is positioned after (at the right of) the cursor position, the display may be "SRCH=113/200". In the case to display the search word with the arrow (the cursor word is not the search word), it is convenient to display the arrow ".rarw." when the cursor is moved to the right and the arrow ".fwdarw." when the cursor is moved to the left because the cursor movement process can be judged. The search word can be detected automatically (automatic search mode) by moving the cursor sequentially and stopping automatically the cursor movement when the cursor position is on the search word under control of the firmware of ROM 26. For this automatic search mode, the counter counts the low frequency clock pulse to renew sequentially the cursor position information in the first area of RAM 38, and CPU 24 stops the counter to count when the cursor word corresponds to the search word. The next search word can be detected to restart the counter operation.

FIG. 6 is an example display, wherein the search phenomenon is the glitch in the timing display mode. In the display, the glitches are displayed as black thick lines in the logic waveforms by converting the glitch information in the third area of RAM 28 into the ATTRIBUTE information and storing it in the display play RAM area under control of CPU 24. When the glitch search instruction is input via keyboard 30, CPU 24 stores the character information of "GLITCH" in the display RAM area and displays it on CRT 34 in accordance with the firmware of ROM 26. Similarly to the search word mode, CPU 24 counts a total number of the glitches stored in the third area of RAM 28 in accordance with steps 52-58 of FIG. 4C, counts a number of the glitches (search number) on and before the cursor position in accordance with steps 60-72 of FIG. 4A, and stores these counted values as the character information in the display RAM area for displaying on CRT 34. In the glitch search mode, even if the glitches are present on the same address of a plurality of channels (i.e., a plurality of glitches are present on the same time point of the display), these glitches are counted as one in step 56. For applying the flow charts of FIGS. 4A-4E to the glitch search mode, the word "search word" of the above description is changed to "glitch". In the glitch search mode, step 96 is followed after step 92. It should be noted that step 96 is led when the input logic signals at the cursor position include a least one glitch. After CPU 24 detects "1" of the fourth area of RAM 28 at the cursor position, CPU 24 reads the contents of the third area at the cursor position which are glitch information for checking each channel includes the glitch. CPU 24 outputs the reverse code as the ATTRIBUTE of the cursor word if the selected channel includes the glitch, and outputs the normal code as the ATTRIBUTE thereof if not so. Therefore the cursor word display is reversed at only the channel including the glitch. In example of FIG. 6, the total number of the glitches is one hundred and eighty-nine, and the glitches at the cursor position (channels A4 and A7) are the 135th. As described hereinbefore, only the channel data of the cursor word including the glitch is inverted (surrounded by the squares), however, all the channel data may be reversed.

FIG. 7 shows a display example, wherein the search phenomenon is the word in the state display mode. A different point from the operations of FIGS. 3 and 5 is that the logic signals are displayed with only characters "1" and "0". For this end, CPU 24 converts the data of the second area appointed by keyboard 30 into the character information to be stored in the display RAM area. In the display of FIG. 7, "A0" through "A7" on the third line indicate the channel numbers, and the display under them indicates the data of each channel. "0, 1, 2 . . . 11, 12" arranged longitudinally at the left side indicate the address numbers of the second area of RAM 28. These channel numbers and address numbers are displayed in accordance with the firmware of ROM 26. Three lines at the address number "8" are the cursor controlled by keyboard 30. A display "SRCH=.uparw.2/200" at the top indicates that the total number of the search word is two hundreds, and the second search word is positioned before (higher than) the cursor position of the address "8". If "SRCH=.dwnarw.3/200" is displayed, the third search word is positioned after (lower than) the cursor position. Since the data at the addresses 2 and 5 are the search word, the display is inverted. This inversion is done by controlling the ATTRIBUTE of the character information corresponding to the addresses of the search word detected by comparing the data of the second area of RAM 28 with the search word. This display method is the same as the aforementioned word search mode of the timing display mode by reference to FIGS. 4A-4C except step 84.

In step 84, step 88 is followed since the timing display mode is not selected. Step 88 will be described in detail by reference to FIG. 4E. In step 100, CPU 24 sets the pointer to the address of the fourth area of RAM 28 corresponding to the selected first display address of the second area, e.g., the address 0 in the case of FIG. 7. CPU 24 judges whether the pointer contents (contents of the fourth area at the pointer position) is one or not in step 102. If the data information of the second area at the first display address is the same as the search word, the pointer contents are "1" and thereby step 104 is followed. If the pointer contents are not "1", step 106 is followed wherein CPU 24 generates the normal code as the ATTRIBUTE for displaying the selected (first) line of the state table in the normal display. After step 106, the next is step 112. In step 104, CPU 24 judges whether the word search mode is selected or not. If the word search mode is selected, CPU 24 generates the reverse code as the ATTRIBUTE for reversing the selected line display in step 108, since the selected line includes the search word. The next of step 108 is step 112. If the word search mode is not selected, i.e., if the glitch search or the comparison mode is selected, step 112 is followed through step 110. In step 112, CPU 24 judges whether the pointer position is equal to the first address plus twelve or not. Since, only thirteen lines (date) is displayed simultaneously in the state display mode, CPU 24 checks the pointer address corresponds to the final line of the state display in step 112. If the pointer address is the final line, CPU 24 returns to the main routine. If the pointer address is before the final line, CPU 24 increases the pointer address by one and returns to step 102. Thus, CPU 24 controls the display of the state table via steps 110-114, and inverses only the search words as shown in FIG. 7.

FIG. 8 shows a display example of CRT 34 wherein the search phenomenon is the glitch in the state display mode. Since the operation of the search mode is substantially equal to that of FIG. 6 and the operation of the state display is substantially equal to that of FIG. 7, only differences will be discussed. The display of FIG. 8 is obtained via the steps of FIGS. 4A, 4B, 4C and 4E. In step 104 of FIG. 4E, since the glitch search mode is selected, step 110 is followed. This step 110 is similar to step 96, and CPU 24 reads each channel of the third area of RAM 28 at the address including at least one glitch. If the selected channel does not include the glitch, CPU 24 outputs the normal code as the ATTRIBUTE for displaying the normal state table. If the selected channel includes the glitch, CPU 24 outputs the reverse code as the ATTRIBUTE for displaying the reversed state table. Thus, only the channel data including the glitch are reversed every address. The display of FIG. 8 indicated that a total number of the glitches is one hundred and twenty-four, the seventy third glitch is located on the cursor position at the address "104", and the inverted data include the glitches. The state display mode is different from the timing display mode, since the former does not display the glitch in the prior arts. Thus, it is useful to invert the data including the glitch in the state display mode. All the data at the address including the glitch may be inverted.

FIG. 9 shows another display example of CRT 34, wherein the search phenomenon is the glitch in the state display mode. This display is similar to the display of FIG. 8, however, the data are displayed in hexadecimal. CPU 24 divides the data stored in the second area of RAM 28 into two groups, one consisting of the channels 0, 1, 2 and 3 and the other one consisting of the channels 4, 5, 6, and 7, and converts the divided data to the hexadecimal in accordance with the firmware of ROM 26. A display "H" at the third line indicates the hexadecimal.

The scroll mode described in the timing display mode is available in the state display mode. When the cursor is instructed to move to the outside of the display by keyboard 30 after the cursor is positioned at the top or bottom of the display, the display is moved with fixing the cursor at the top or bottom of the display so that the cursor is substantially moved. For example, if the cursor is instructed to move upward after the cursor is positioned at the top of the display, the display data is moved downward, wherein the data corresponding to the cursor movement value is erased from the bottom end of the display, and new data corresponding to the erased data value appears from the top end of the display. In the scroll mode, the display area is determined by the cursor, and CPU 24 may read all the logic signals of a new display area from the second and third areas of RAM 28 for repeating the above described display operation. However, it is effective to shift the data information (logic signals) in the display RAM area of RAM 28 by a number of the addresses corresponding to the cursor movement value, read the new data information corresponding to the value lacked by shifting (the end part of the data information is erased by shifting) from the second and third areas of RAM 28, and store the new data information in the display RAM area under control of CPU 24.

In the comparison mode, input logic signals are detected by probe 10 and stored in data memory circuit 14 as described hereinbefore. When the transfer instruction is input from keyboard 30, CPU 24 transfers the contents of memory circuit 14 to the second area of RAM 28 in accordance with the firmware of ROM 26. The second area is first memory means, and the logic signals stored in this first memory means are reference logic signals. In this instance, it is desirable that probe 10 detects logic signals from a reference apparatus.

Similarly to the aforementioned operation, logic signals from an apparatus to be measured are stored in memory circuit 14. In response to a display instruction from keyboard 30, CPU 24 transfers the contents of memory circuit 14 to a third area of RAM 28 under control of the firmware of ROM 26. The third area is second memory means, and the logic signals stored in this second memory means are the input logic signals. When the display mode and a display area (a part of the stored logic signals to be displayed) are selected via keyboard 30, CRT 34 displays one of or both of the contents of the second and third areas of RAM 28 in accordance with the processes described hereinbefore by reference to FIGS. 7, 8 and 9. FIG. 10 shows a display of both of the contents of the second and third areas. "1" and "0" at the left half of CRT 34 are logic states of the selected addresses in the third area of RAM 28. "ACQ" at the third line of the left half means the acquired input logic signals, and a display "CH=0 1 2 3 4 5 6 7" under the third line indicates a channel number of each logic signal which corresponds to each tip of probe 10. In other words, the display under the channel number is its data. These display "ACQ" and the channel numbers are displayed via the display RAM area by CPU 24 under control of the firmware of ROM 26. "123, 124 . . . 134, 135" at the left side of the display indicates the addresses of the third area of RAM 28, and is displayed by CPU 24 in accordance with the display area code in the first area of RAM 28 under control of the firmware of ROM 26.

Similarly, the contents of the second area of RAM 28 corresponding to the selected (displayed) addresses of the third area are displayed at the right half of the display. "REF" at the first line of the right half display means the reference logic signals, and "CH=0 1 2 3 4 5 6 7" under the first line indicates the channel numbers. These displays are based on FONT information stored in the display RAM area of RAM 28.

CPU 24 compares all the contents of the second and third areas of RAM 28 under control of the firmware of ROM 26. This comparison operation is made between the addresses 0 and 255 in accordance with step 50 (FIG. 4C) of the aforementioned flow charts. In step 56, CPU 24 stores "1" in the corresponding address of the fourth area of RAM 28, when the data information (acquired logic signals) at the selected address of the third area is different from the reference logic signal at the corresponding address of the second area. In this mode, "S.R." in steps 56, 58 and 78 means the data different from the reference logic signals. CPU 24 counts the total number of different parts (words) between the input (acquired) and reference logic signals through steps 52-56, the displays the total number on CRT 34 in step 58. In the example of FIG. 10, the total number is 225. The search number is counted via steps 60-72, wherein the search number is a number of the different parts on or before the cursor position. This search number is displayed in accordance with steps 74-82 as shown in FIG. 10. In this example, the search number is 103, and "CMPR=.uparw.103/225" is displayed. "CMPR" means the comparison mode, and ".uparw.103/225" indicates that the total number of the different parts is 225 and the 103rd different part is located at an upper portion (.uparw.), a prior address (129) with respect to the cursor position (130). The arrow is displayed, since the input and reference logic signals at the address 130 are equal to each other. If the cursor is located at the address 129 or 131, the display may respectively be "103/225" or "104/225". The total number and the search number may be directly converted to the FONT information and stored in the display RAM area, instead of staring them in the first area of RAM 28.

The different parts (words) of the displayed data are reversed in accordance with steps 100-114 similarly to the glitch search mode. Especially in step 110, after CPU 24 detects the different part by reference to the fourth area of RAM 28, CPU 24 obtains an exclusive OR of each channel of the input and reference logic signals at the different parts. The results of the exclusive OR is "1" at a channel including different logic signals, and it is "0" at a channel including the same logic signal. In accordance with this exclusive OR operation, CPU 24 controls the ATTRIBUTE of the state display, so that the different parts are reversed every channel. Thus, the display of FIG. 10 is obtained.

When the cursor position is moved by keyboard 30, the cursor position information in the first area of RAM 28 is changed, and CPU 24 counts the search number by a use of the fourth area of RAM 28 to obtain the relationship between the total number of the different parts and the cursor position. If the cursor is moved upward from the bottom end and reaches to the address 130, the relationship may be displayed as "CMPR=.dwnarw.104/225". This indicates that the 104th different part is located under (after) the cursor.

A display "CMPR WDO=0-255" at the second line of FIG. 10 indicates that the data between the addresses 0 and 255 are compared. In other words, "CMPR WDO" means a comparison window, and "0-255" indicates the address range. The addresses are selected by keyboard 30, and stored in the first area of RAM 28. The total number of the different parts is within this comparison range. When CPU 24 judges that the addresses of the displayed data are within the comparison range in accordance with the firmware of ROM 26, a character "C" is displayed at the left side of the address number. "C" is stored at the FONT information in the display RAM area of RAM 28. Therefore, it is easy to judge the comparison range.

In the above explanation, CPU 24 counts the different parts of the logic signals stored in the second and third areas of RAM 28, and obtains the relationship between the total number and the cursor position. However, CPU 24 may count the same parts and obtain the relationship between the total number of the same parts and the cursor position. Moreover, the display of the same parts may be inverted between black and white. In this instance, when the outputs of the comparison function of CPU 24, an exclusive OR function, are zero in all channels, the counting operation is enabled. The other operations are the same as the above-described operations.

In the embodiment of FIG. 10, the comparison is made every address and channel. However, the comparison operation may be done by regarding the data of a plurality of addresses in the reference logic signals as one pattern (pattern search mode). This operation will be discussed by reference to FIGS. 1 and 11. Firstly, the data of the desired addresses are selected from the reference logic signals via keyboard 30. In this embodiment, the addresses 39, 45, and 41 are selected in this order. For selecting the addresses, all the reference logic signals may be displayed in the scroll mode, and the selected address display by keyboard 30 may be inverted between black and white. The selected addresses are stored in the first area of RAM 28, and they are displayed on CRT 34 as the right half of FIG. 11 simultaneously with the data of these addresses. After that, the address order may be exchanged. the data of the three addresses are regarded as a single reference pattern. CPU 24 compares the data of the address 39 in the second area (reference logic signal) of RAM 28 with the data of each address in the third area (input logic signal) under control of the firmware of ROM 26. When CPU 24 finds the data in the third area corresponding to the address 39's data of the second area, CPU 24 compares the data at the next address of the third area with the data at the address 45 of the second area. If these data are equal to each other, CPU 24 compares the data at the further next address of the third area with the data at the address 41 of the second area. If the data at the further next address of the third area is the same as the address 41's data of the second area, the reference pattern is detected in the third area, and thereby CPU 24 counts by one and reverses the reference pattern portion of the acquired logic signal display. If the data at the next address of the third area is different from the address 45's data of the second area, or the data at the further next address of the third area is different from the address 41's data of the second area, CPU 24 continues to find the address 39's data of the second area in the third area and repeats the foregoing operation. Thus, CPU 24 can search the reference pattern in the third area and counts the total number of the corresponding patterns. In addition, CPU 24 counts the corresponding patterns on and before the cursor position, displays "CMPR PATER=13/13" at the first line of FIG. 11 similarly to FIG. 10, and inverts the display of the corresponding pattern. "CMPR PATER" indicates the comparison pattern mode, and "13/13" indicates that the total number of the reference patterns is 13 and the cursor position (address 203 in the example) is located on the thirteenth reference pattern. If the cursor position is the address 205, a display may be ".uparw.13/13". Since the comparison window is from the addresses 0 to 206 in this example, the character "C" is not displayed at the left sides of the addresses 207, 208, and 209.

In the above description, CPU 24 displays the relationship between the total number of the input logic signals corresponding to the reference pattern and the cursor position, and inverts the input logic signals' display corresponding to the reference pattern. However, the relationship between the total number of the input logic signals different from the reference pattern and the cursor position may be displayed. The address number of the reference pattern may be any number including three.

As described hereinbefore, the logic analyzer of the present invention can obtain the relationship between the total number of the predetermined phenomenon (search word or glitch) included in the input logic signals stored in the memory means and the cursor position of the display means, so that the search mode is very useful. Since the word and glitch search modes are available in the timing and state display modes, the measurement is more convenient. In addition, the present invention compares the input logic signal with the reference logic signal, counts the total number of different or equal parts, and obtains the relationship of the total number and the cursor position.

The software controlling CPU 24 in the preferred embodiment described with respect to FIGS. 4A-4E is shown in Appendix A. This software is the machine code of the Z80A.

While we have shown and described herein the preferred embodiment of our invention, it will be apparent to those skilled in the art that many changes and modifications may be made without departing from our invention in its broader aspects. For example, the automatic search function described in conjunction with FIGS. 3 and 5 may be applied to the operations of the state display mode. In this instance, when the predetermined phenomenon or the different (or same) part is detected, the inversion technique may be applied to the display. However, an intensity modulation technique or an underline may be used to indicate the desired portions. In the comparison mode, the reference logic signals may be obtained by inputting via the keyboard or modifying a part of the signals detected by the probe by the keyboard instead of using the signals detected by the probe. The display means may be a flat display such as liquid crystal and plasma displays, and an X-Y plotter instead of the CRT. The state table may be displayed in the octal or hexadecimal by dividing the input logic signals to groups each consisting of three or four channels. A number of the probe tips, namely, a number of the channel, may be any desired number. The addresses of the input or reference logic signals may be offset when displaying and comparing the input and reference logic signals. If the addresses of the reference logic signals are offset by, for example, +50, the input logic signals at the addresses 0 through 205 and the reference logic signals at the addresses 50 through 255 are displayed and compared with each other. There may be a case that the data at one addres of the input logic signals is the common parts of two reference patterns in the comparison of the reference pattern and the input logic signals, if the data of the first address of the reference pattern is the same as the last address. However, there is no problem, if the reference pattern is detected only when the cursor is positioned on the first address of the reference pattern. Therefore, the scope of the present invention should be determined only by the following claims. ##SPC1##

Claims

1. A logic analyzer storing and displaying a sequence of input logic signal states occurring in a collection of digital signals comprising:

an addressable memory for storing logic signal states, said collection of digital signals being input to said memory;

means for addressing and write enabling said addressable memory such that a first set of successive logic signal states of said collection of digital signals is stored at successive addresses in said addressable memory;

means responsive to operator input for permitting an operator to define a reference signal state, for permitting the operator to select a second set of successive addresses of said addressable memory wherein said second set of memory addresses contains less than all of the logic signal states of said first set of logic signal states, and for permitting the operator to select one of said logic signal states stored at one of the memory addresses of the second set;

means for generating a first count of logic signal states of said first set which were stored in said addressable memory before said selected one logic signal state was stored and which match said reference logic signal state; and

means for displaying a representation of the logic signal states stored at said second set of memory addresses, for displaying said first count, and for displaying an indication of which addresses of said addressable memory are included in said second set and which addresses are not included in said second set.

2. A logic analyzer according to claim 1 wherein said selected one logic signal state is included in said first count when said selected one logic signal state matches said reference logic signal state.

3. A logic analyzer according to claim 1 further comprising means for generating a second count of logic signal states of said first set which match said reference signal, said second count being displayed by said means for displaying.

4. A logic analyzer according to claim 1 wherein said means for displaying also displays an indication as to whether said selected logic signal state matches said reference state.

5. A logic analyzer for storing and displaying a sequence of input logic signal states occurring in a collection of digital signals comprising:

means for generating a glitch signal of a state indicating whether each state of a sequence of input logic signal states in a collection of digital signals occurs during a period when the collection of digital signals contains a glitch;

an addressable memory for storing an input logic signal state and a glitch signal state at each address, said collection of digital signals and said glitch signal being applied as inputs to said memory;

means for addressing and write enabling said addressable memory such that a first set of successive logic signal states of said collection of digital signals is stored in said addressable memory, successive logic signal states of said collection of digital signals being stored at successive addresses, and such that a glitch signal state generated by said means for generating a signal is stored in said addressable memory with each stored logic signal state, said glitch signal state indicating whether the logic signal state stored with the glitch signal state occurred during a period when the collection of digital signals contained a glitch;

means responsive to operator input for permitting an operator to select a second set of successive addresses of said addressable memory wherein said second set of memory addresses contains less than all of said first set of logic signal states, and for permitting the operator to select one of said logic signal states stored at one of the memory addresses of the second set;

means for generating a first count of glitch signal states stored in said addressable memory indicating a glitch occurring prior to said selected one logic signal state; and

means for displaying a representation of the logic signal states stored at said second set of memory addresses, for displaying an indication of which of said displayed logic signal states occurred during a period in which the collection of logic signals contained a glitch, and for displaying said first count.

6. A logic analyzer according to claim 5 further comprising means for generating a second count of glitch indicating signal states stored in memory with all of said first set of logic signal states.

7. A logic analyzer according to claim 1 wherein said selected one logic signal state is included in said first count when a glitch signal state stored with said further selected one logic signal state indicates said selected one logic signal state includes a glitch.