Patent Application
20150146179
This invention relates to the manufacture of integrated circuit devices with minimum feature sizes down to about 10 nm to 20 nm, and more particularly, to apparatus and a method for use in such manufacture.
A critical part of the manufacture of integrated circuit devices is the patterning of various layers on the surface of the semiconductor wafer, which after processing is diced up to provide the integrated circuit devices. These patterns define the various regions in the integrated circuit device, such as ion implantation regions, contact window regions, bonding pad regions, etc., and are generally formed by transferring patterns of geometric shapes in a mask to a thin layer of radiation resistive material, termed the “resist”, that overlies the silicon wafer within which are to be formed the integrated circuit devices. Typically the pattern on the mask is on an enlarged scale and needs to be reduced for incidence on the resist.
Presently the pattern transfer process is generally performed by photolithography and the radiation used for the transfer is energy at optical wavelengths.
As the size of features in the pattern to be made in the resist has decreased, as the result of higher packing density of circuit elements in the integrated circuit, there has been a need to decrease correspondingly the wavelength of the optical radiation used for the transfer. It appears that the technology is rapidly approaching the limit at which optical radiation can serve usefully as the radiation needed to pattern the resist appropriately.
There are several alternatives that are currently being considered for use in the transfer of geometric patterns on a mask to the resist layer including the use of extreme ultraviolet radiation, and electron beams.
Electron beams, which have the promise of precise control with fine detail, currently are being used primarily in the preparation of the masks used in optical lithography. While there is also some use of electron beams for direct writing of patterns on resists, on silicon wafers, such use is limited to custom circuits that are made in small runs and sold at very high prices.
A recognized difficulty with the use of electron beams for use in patterning resists in the manufacture of integrated circuits is the low throughput of such use, that is compounded by the relatively high cost of electron beam exposure systems. Accordingly, the potential of electron beam exposure systems for use in the manufacture of integrated circuits is generally deemed not promising and the effort to develop commercial systems for such use has been limited.
In a paper entitled “High Throughput Submicron Lithography with Electron Beam Proximity Printing”, published in September 1984, Solid State Technology, pps 210-217, there is described an electron beam lithography system in which the electron beam is operated with an energy of 10 KeV, which was deemed very low at that time, with a stencil mask that was 2 microns thick, a thickness that was then thinner than was conventional, and with a separation between the mask and wafer of 0.5 millimeters (500 microns) which was then deemed unusually close. The electron beam, which had a diameter of about 1 millimeter (1000 microns), only a small fraction of the area of the mask, was raster scanned across the mask by a first pair of deflection coils. A second pair of deflection coils was used to tilt the beam about a pivot point in the mask plane. A silicon wafer that included a central membrane that was thinned to 2 microns served as the mask. With such a mask and a beam energy of 10 KeV it was necessary to include an absorber layer of a suitable metal on the mask to intercept electrons that were not directed at openings in the mask. Otherwise such electrons would have passed through the thin silicon mask membrane and would have blurred the pattern to be formed on the resist. However, the use of a thicker silicon mask makes it more difficult to achieve narrow line widths because of the high aspect ratio of the line width versus the thickness of the mask.
However, this paper appeared to have little impact on workers in the field and effort on such proximity projection printing systems languished since 1984. Instead, the work on electron beam exposure systems generally has involved systems that employ high energy electrons in the beam to provide “stiffness” to the beam. A stiff beam is one whose diameter is well controlled and so better amenable to focusing and creating sharp images, and also less affected by stray fields. Stiffness is generally related to the energy or velocity of the electrons in the beam, the higher the energy the stiffer the beam.
For this reason, the commercial practice generally has been to use beams of at least 50 KeV in energy for very fine resolution, especially if currents large enough for fast writing are to be used. Apparatus employing such beams generally include: a source of such electrons, an illumination system that focuses and shapes such electrons into a beam and passes the beam through a mask and a projection system that projects such beams through a lens, all the while reducing the mask pattern, by a factor of five to twenty five, before it impinges on the resist.
However, it appears that, as the density of circuit elements in the integrated circuit are increased and the feature size of the pattern in the resist decreases, problems arise with the use of high energy beams. In particular, there is increased the proximity effect, which results in deformation of the pattern formed in the resist as the result of back scattering of electrons from the underlying silicon wafer substrate into the resist. This effect becomes more troublesome the finer the pattern sought to be formed in the resist. There is some evidence that if the accelerating voltages are made high enough, higher energy electrons forward scatter less in the resist and the back scattered electron scatter via a wider area, so that a relatively constant dose results in the resist. This makes the proximity effect correction easier, although it is impossible to eliminate the proximity effect completely. Additionally, it is characteristic of electron beam resists that their sensitivity tends to decrease the higher the energy of the electrons in the beam since the more energetic or faster electrons spend less time and deposit low energy in the resist. Accordingly, the more energetic the electrons, the larger the current (i.e., the higher the density of electrons in the beam) required for a given sensitivity. Moreover, the higher the density of electrons in the beam, the larger the space charge effects, which tend to defocus the beam, which causes a blurring of the pattern and deterioration of the resolution of the pattern. Moreover, the larger the current, the higher the heating of the mask, the resist layer, and the substrate, the greater the distortion of the projected pattern. Therefore one has to limit the operating current in order to maintain the required accuracy. This, in turn, limits the throughput of the apparatus.
To meet some of these problems, fresh interest developed for a time in the use of low energy electron beams for patterning resists. In particular, a paper entitled “Low voltage alternative for electron beam lithography” J Vac. Sci Tech B 10 (6), November/December 1992, pps 3094-3098, describes experiments that demonstrate that proximity effects can be substantially reduced by using electrons of relatively low energy in the beam. In particular, it reports that the proximity effect was substantially reduced with electron beam energies of 2 KeV used on a silicon substrate with a PMMA resist 66 nanometers thick. The work was intended primarily to show that low energy electron beams were potentially useful to expose resists sufficiently thick to be useful for patterning. It recognizes, however, that low voltage has some drawbacks such as a tendency of low brightness of the electron beam and a difficulty of the application of the ultra-thin resist layer.
As a consequence, although it has long been recognized that low energy electron beams are feasible for patterning resists and have some potential advantages, the disadvantages were thought to outweigh the advantages and widespread commercial use on high volume devices has failed to result. Nevertheless, there have been substantial development efforts recently to utilize low voltage lithography by the use of 1. retarding field electron optical column, 2. multiple arrayed miniature electron beam columns, and 3. multiple arrayed scanning tunneling microscope tips.
On Oct. 31, 1997 the present inventor filed a patent application entitled “LOW ENERGY ELECTRON BEAM LITHOGRAPHY” that became U.S. Pat. No. 5,831,272 that issued on Nov. 3, 1998. Corresponding applications were filed in Japan and Germany and a Japanese patent and a German patent were issued. One embodiment of the system of U.S. Pat. No. 5,831,272 is a system for patterning a resist on a semiconductor substrate. The system comprises a 1X stencil mask of monocrystalline silicon positioned in the path of the electron and an electron-beam sensitive resist-covered substrate in the path of the electron beam and the mask. The resist is thin, the voltage accelerating the beam is sufficiently low such that the proximity effect is insignificant, the power of the beam is sufficiently low such that heating of the mask, resist, and substrate is also insignificant, and the density of electrons in the beam is sufficiently low that space charge effects are insignificant. The electron beam accelerating voltage is about 2 KeV, with a range of about 1 to 5 KeV, the mask is positioned about 50 microns from the resist covered substrate, the resist is about 100 nm thick, with a range of 30 to about 300 nm, the current of the electron beam is about 3 microamperes, with a range of about 0.3 to about 20 microamperes, the beam diameter is about 1.0 millimeter, with a range of about 0.1 to about 5 millimeter, and the mask is a stencil mask having a thickness of about 500 nm, with a range of about 200 to 1000 nm. Alignment errors of the mask and semiconductor wafer were kept down to about 15 nm. By 2007 the LOW ENERGY ELECTRON BEAM LITHOGRAPHY system of U.S. Pat. No. 5,831,272 had been built, tested, and found to be functional. Using this system it was found that feature sizes well below 1 micron and potentially down to about only 45 nm. It took a substantial amount of testing to determine the limit of how small feature sizes could be achieved while keeping throughput at a high enough level to be commercially viable.
Between 1997 and the present there has been considerable work on improving conventional systems (i.e., ArF Immersion Lithography) for transferring an image contained on a mask to a semiconductor wafer to form an integrated circuit that was meant for high volume production. This technology, which has become wide spread, has resulted in systems that can generate integrated circuits for high volume production with features down to about 40 nm.
The present invention represents a substantial improvement in the results obtainable using the apparatus of U.S. Pat. No. 5,831,272 which is incorporated herein by reference. While much of the apparatus of the present invention is common with the inventors previous invention, there are significant changes to the apparatus and the operating parameters resulting from the sixteen years of work by the present inventor on improving his earlier invention.
In the next few years it is desirable to further improve lithographic systems that can generate integrated circuits with features in a range of about 10 to 20 nm. One such feature might be the length of a gate of a Metal-Oxide-Silicon transistor or the wide of a metal conductor. These proposed systems, such as ArF double patterning and EUV lithography systems, are complex and expensive and it is not clear which, if any, will actually go into wide spread use.
The present invention is directed to a system for low energy electron beam proximity projection lithography with a sufficient throughput and accuracy for patterning minimum feature size in the range of about 10 to 20 nm for mass produced integrated circuits.
Viewed from one aspect, the present invention is a system for patterning an electron sensitive resist layer covering a semiconductor wafer. The system comprises an electron beam system characterized by an accelerating voltage of about 0.5 to about 5 KeV, an electron beam current of about 50 to about 800 microamperes, the beam has a diameter of about 1 to about 9 mm, and fine deflectors for adjusting tilt of the electron beam. It further comprises an n Division Complementary Mask (nDCM), where n is an integer greater than 2, having struts that surround and support each membrane that has formed therein a pattern that is to be transferred to the resist layer, the thickness of the resist layer being about 10 to about 300 nm, and the thickness of each membrane is about 50 to about 500 nm, the nDCM and the resist layer are spaced about 10 to about 300 microns from each other and are positioned in the path of the electron beam. The resist layer has a thickness of about 10 to 300 nm.
The system further comprises a nonmetallic conductor layer having a thickness of about 50 to 500 nm and lying under the resist layer.
The system further comprises a distortion sensor and tilt means. The distortion sensor means senses for distortions in the membranes and the semiconductor wafer. The tilt means has an input coupled to an output of the distortion sensor means for generating a distortion error correction signal at an output thereof that is coupled to inputs of the fine deflectors such that distortions in the membranes of the nDCM and the semiconductor wafer are compensated for so as to minimize image placement errors.
Viewed from a second aspect, the present invention is a system for forming a pattern on a electron sensitive resist layer covering a chip semiconductor wafer having a plurality of areas into each of which an individual integrated circuit is to be formed. The system comprises an electron beam system characterized by an accelerating voltage of about 0.5 to about 5 KeV, an electron beam current of about 50 to about 800 microamperes, the beam has a diameter of about 1 to about 9 mm, and fine deflectors for adjusting tilt of the electron beam.
The system further comprises a mask semiconductor wafer comprising a plurality of n Division Complementary Masks (nDCMs), where n is an integer greater than 2, each of the nDCMs has struts that surround and support a membrane that has formed therein a pattern that is to be transferred to the resist layer, the thickness of each membrane is about 50 to about 500 nm, and the mask semiconductor wafer and the chip semiconductor wafer are spaced about 10 to about 300 microns from each other and are positioned in the path of the electron beam. The resist layer has a thickness of, about 10 to about 300 nm.
The system further comprises a nonmetallic conductor layer, distortion sensor means, and tilt means. The nonmetallic conductor layer has a thickness of about 50 to 500 nm and is under the resist layer. The distortion sensor means senses distortions in the membranes and the chip semiconductor wafer. The tilt means, which has an input coupled to an output of the distortion sensor means, generates a distortion error correction signal at an output thereof that is coupled to inputs of the fine deflectors such that distortions in the membranes and the chip semiconductor wafer are compensated for so as to minimize image placement errors.
Viewed from a third aspect, the present invention is a process, in the manufacture of silicon integrated circuits, of patterning an electron sensitive resist layer covering a nonmetallic conductor layer that covers a semiconductor wafer. The process comprises the steps of:
Using an electron beam system having an accelerating voltage in the range of about 0.5 to about 5 KeV with a beam current in the range of about 50 to 800 microamperes and with the beam diameter being in the range of about 1 to 9 mm, aligning a mask that contains a pattern that is to be transferred to the resist layer with the semiconductor wafer. The mask and the semiconductor wafer are in the path of the electron beam and are separated from each other by 10 to 300 microns. The thickness of the resist layer is about 10 to 300 nm. The mask is an n Division Complementary Mask (nDCM), where n is a whole integer greater than 2. The nDCM has struts that surround and support membranes that have formed therein the pattern that is to be transferred to the electron sensitive resist layer. The membranes having a thickness in the range of about 50 to about 500 nm.
Sensing distortions in the nDCM and the semiconductor wafer and generating therefrom a distortion error correction signal.
Applying the error correction signal to fine deflectors of the electron beam system that control tilt of the electron beam so as to adjust the tilt of the beam to compensate for distortions in the nDCM and wafer so as to minimize image placement errors.
Scanning the electron beam across the membrane with an accelerating voltage in the range of about 0.5 to about 5 KeV, a beam current in the range of about 50 to 800 microamperes and with the beam diameter being in the range of about 1 to 9 mm, whereby the pattern in the membranes is transferred to the resist layer.
The invention will be better understood from the following more detailed description taken in conjunction with the accompanying drawing. The drawings are not necessarily to scale.
Referring now to
The system 10 further comprises first and second fine tuning sets of deflecting coils (or electrodes) 51 and 52, which are also denoted as fine deflectors 51 and 52. Deflecting coils 51 and 52 are used to tilt the beam slightly (i.e., a fine tune) at the pivot on the mask structure 200 plane for the purpose of compensating for distortions in the mask structure 200 and the wafer 210 that limit pattern placement accuracy. Spaced about 50 microns below the mask structure 200 is a workpiece comprising a relatively large semiconductor wafer (substrate) 210 of monocrystalline silicon. Covering a top surface 211 of wafer 210 is an optional planarizing insulator layer 221, typically photo-resist, that is covered by a conductive layer 222, that is covered by an ultra thin electron sensitive resist layer 216 having a top surface 220 that is to be patterned. The layer 222 is a nonmetallic conductor, typically a hydro-carbon resist like material or amorphous carbon. The electron sensitive resist layer 216, in a preferred embodiment, is about 20 nm thick, and can be in a range of about 10 to about 300 nm. It can be any of the resists amenable at ultrathin thicknesses to patterning by an electron beam. Layer 222 is typically about 50 nm thick but can be thicker. In a preferred embodiment the operating beam voltage is about 2 KeV with a range of about 0.5 to about 5 KeV, the beam current is about 200 microamperes with a range of about 50 to about 800 microamperes.
System 10 further comprises a system control unit 108, a scanning beam control unit 110, a fine beam tilt control unit 112, a stage control unit 114, a distortion sensor 106 (also denoted as distortion sensor means), a location sensor 104, high precision wafer stage 100, and a high precision mask stage 102. System control unit 108 comprises a computer and memory. Arrows on lines typically show the direction of the flow of information (signals). The opposite sided arrows on the lines from stage control unit 114 indicate that a mechanical force is exerted pushing and/or pulling mask stage 102 and wafer stage 100. The fine beam tilt control unit 112 and portions of the system control unit 108 may be denoted as tilt means.
The semiconductor wafer 210 is supported on the high precision wafer stage 100 that allows the wafer 210 to be stepped in the usual fashion so that successive areas the resist-covered wafer 210 can be exposed in turn to the electron beam 15 for a time appropriate for patterning the resist layer 216. The mask structure 200 is supported on a mask stage 102.
The stage control unit 114 is in mechanical contact with the mask stage 102 and the wafer stage 100. The location sensor 104 senses the exact locations of the mask structure 200 that is being held on the mask stage 102 and the wafer 210 that is being held on the wafer stage 100. An output of the location sensor 104 is coupled to an input of the system control unit 108. Unit 108 receives mask structure 200 and wafer 210 information from the location sensor 104 as to the exact locations of the mask structure 200 on the mask stage 102 and the wafer 210 on the wafer stage 100. It then sends a signal to the stage control unit 114 that causes the wafer stage 100 and mask stage 102 to be moved relative to each other such that the mask structure 200 is aligned with a preselected portion of the wafer 210 to within about 2 nm or less.
The scanning beam control unit 110 is electrically connected to the main deflectors 22 and 24 and controls the scanning of the electron beam 15 through the mask structure 200 and across portions of the electron sensitive resist layer 216 on wafer 210. System control unit 108 has an output connected to an input of scanning beam control unit 110 and controls unit 110.
During processing a semiconductor wafer can get distorted due to induced stresses and how it is held (chucked). During the creation of a mask the processing used to form a pattern thereon and how it is held (chucked) can cause distortions in its surface. In order to achieve very small feature sizes, about 10 nm, it is necessary for alignment of the plane of the mask 200 (membranes 204 shown in
The distortion sensor 106 senses distortions in the mask structure 200, specifically in the membrane 204 portion that is shown in detail in
The system 10 further comprises appropriate housing (not shown), typically a vacuum envelope, for enclosing the system. There would also be included the various components (not shown) used to establish the accelerating voltages that are necessary for operation in the manner described.
The 4DCM has many advantages over a single conventional 1X stencil mask. It has greater mechanical stability and higher thermal stability. When the pattern density formed in a particular 1X stencil mask is very high, there can result a hole-opening ratio of 50% which makes it is very difficult to have high pattern placing accuracy. This is particularly true in the case an integrated circuit chip there are areas of very dense patterns close to areas where there are sparse patterns. The use of a 4DCM essentially divides the pattern density by four and makes it feasible to generate 10 to 20 nm features with proper pattern placement accuracy.
The membrane layer 204 can be a conductive material such as doped silicon, silicide, or even a metallic layer. Struts 202 are typically monocrystalline silicon.
When electron's of relatively low accelerating energy, such a 2 KeV impinging on the ultra-thin electron sensitive resist layer 216, they are not scattered in a wide angle, but go straight down to sensitize a narrow region of resist layer 216. This results in forming a high resolution pattern. Any electrons that pass through layer 216 are essentially trapped in nonmetallic conductor layer 122 which eliminates charge-up effect in the resist layer 216. The struts 202 act as large heat sinks for membranes 204. This helps cool them and thus reduces thermal distortion. This essentially limits the need for complex steps to compensate for distortions of membranes (masks) 204 caused by the electron beam 15 which heats membranes 204.
The transfer of a pattern contained in 4DCM's of mask semiconductor wafer 810 to the areas 712 of chip wafer 710 can be accomplished using the mask semiconductor wafer(s) 810 using at least two different methods.
In the first method each of the four sections of the 7 4DCM's of mask wafer 810 all contain the same ¼ of the pattern that is to be transferred to the 28 areas 712 of chip semiconductor wafer 170. A first mask semiconductor wafer 810 is positioned above a chip semiconductor wafer 710 in system 10 of
In the second method each of the four sections of the 7 4DCM's of mask semiconductor wafer 810 contain a separate ¼ of the pattern that is to be transferred to the 28 areas 712 of chip semiconductor wafer 170. The mask semiconductor wafer 810 is positioned above a chip semiconductor wafer 710 in system 10 of
The specific values described are merely illustrative of a presently preferred mode of operation and a range of such values can be used without causing any of the specific undesired effects discussed becoming significant. For example, the resist thickness may be in the range between about 10 to 300 nm thick; the accelerating voltage may be in the range from about 0.5 to 5 KeV; the beam diameter may be in the range of about 1 to 9 millimeters; and the distance between the mask and the wafer may be in the range of 10 to 300 microns. In the presently preferred embodiment, the electron sensitive resist layer 216 is about 20 nm thick, the nonmetallic conductor layer 222 is about 50 nm thick, the beam diameter is about 3 millimeter, the mask 200 is a 4 Division Complementary mask (4DCM) with the membrane 204 having a thickness of 100 nm and being spaced about 50 microns from the resist layer 216.
It is to be understood that the specific embodiment described is merely illustrative of the general principles of the invention and that, accordingly, other embodiments may be devised by a skilled worker in the art without departing from the spirit and scope of the invention. For example, as the density of components on integrated circuits increases, it becomes beneficial to use masks of the nDCM type where n equals 5 or a greater integer. Still further, the tilt control unit can be modified by adding computer power and memory such that it can provide the entire tilt means function with the output of the distortion sensor being coupled to it rather than to the system control unit. Furthermore, the physical structure of the mask and wafer stages can be different than shown. For example, each could be a essentially flat surface with the mask and wafer being held in place by electrostatic forces.
