BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, and more particularly, to a memory device with low power consumption.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram showing a memory device of the prior art. As shown in FIG. 1, the memory device 100 comprises a plurality of memory cells MC, a plurality of word lines WL0-WL255, and a plurality of bit lines BL0-BL255. The memory cells MC are arranged in a matrix form. For example, the memory cells are arranged into a matrix having 256 rows and 256 columns. The word lines WL0-WL255 are elongated along a first direction A, and each of the word lines WL0-WL255 is configured to select a corresponding row of the memory cells MC for a read/write operation. The bit lines BL0-BL255 are elongated along a second direction B different from the first direction A, and each of the bit lines BL0-BL255 is configured to transmit data of a corresponding column of the memory cells MC.
Please refer to FIG. 2. FIG. 2 is a diagram showing a memory device 200 with a first bit line arrangement of the prior art. As shown in FIG. 2, the plurality of memory cells MC are divided into a predetermined number (such as 8) of memory blocks bk0-bk7, and each of the memory blocks bk0-bk7 comprises 32 columns of the memory cells MC. Moreover, in addition to the memory cells MC, the word lines WL0-WL255, and the bit lines (bit0_bk0 to bit31_bk7), the memory device 200 further comprises a plurality of multiplexers MUX0-MUX7. Each of the multiplexers MUX0-MUX7 is coupled to bit lines (bit0_bk0 to bit31_bk7) of 32 columns of the memory cells MC of a corresponding memory block bk0-bk7. For example, the multiplexer MUX0 is coupled to bit lines (bit0_bk0 to bit31_bk0) of 32 columns of the memory cells MC of the memory block bk0, the multiplexer MUX7 is coupled to bit lines (bit0_bk7 to bit31_bk7) of 32 columns of the memory cells MC of the memory block bk7,and so on.
Please refer to FIG. 3. FIG. 3 is a diagram showing a memory device 300 with a second bit line arrangement of the prior art. As shown in FIG. 3, in addition to the memory cells MC, the word lines WL0-WL255, and the bit lines (bit0_bk0 to bit31_bk7), the memory device 300 with the second bit line arrangement further comprises a plurality of multiplexers MUX0-MUX31. Moreover, the bit lines (bit0_bk0 to bit31_bk7) of each memory block bk0-bk7 are scattered sequentially. For example, the multiplexer MUX0 is coupled to bit lines (bit0_bk0 to bit0_bk7) of first columns of the memory cells of the memory blocks bk0-bk7, the multiplexer MUX31 is coupled to bit lines (bit31_bk0 to bit31_bk7) of 32th columns of the memory cells of the memory blocks bk0-bk7, and so on. Comparing with the first bit line arrangement of FIG. 2, the second bit line arrangement of FIG. 3 can simplify wiring.
In the memory devices 100, 200, 300 of the prior art, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC, all the bit lines BL0-BL255 are coupled to corresponding selected memory cells for the read/write operation. However, during the read/write operation, some of the bit lines BL0-BL255 are not required to transmit data. The idle bit lines consume power during the read/write operation, such that the memory device 100 of the prior art has higher power consumption.
SUMMARY OF THE INVENTION
The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; wherein one of the column switches and one of the row switches are electrically coupled in series between the at least one bit line and one of the local bit line.
The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; and a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal coupled to one of the local bit lines, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the local bit lines; wherein a plurality of the memory units are arranged along the first direction, a number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.
The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; a plurality of local bit lines, elongated along the second direction, wherein a memory cell group is coupled to a local bit line; a column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; wherein the selected memory cell is selected by a corresponding word line, the column word line and a corresponding row word line.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a diagram showing a memory device of the prior art.
FIG. 2 is a diagram showing a memory device with a first bit line arrangement of the prior art.
FIG. 3 is a diagram showing a memory device with a second bit line arrangement of the prior art.
FIG. 4 is a diagram showing a memory unit with a first word line arrangement of the present invention.
FIG. 5 is a diagram showing a memory device of the present invention with the first word line arrangement and the first bit line arrangement.
FIG. 6 is a diagram showing a memory device of the present invention with the first word line arrangement and the second bit line arrangement.
FIG. 7 is a diagram showing a memory unit with a first embodiment of a second word line arrangement of the present invention.
FIG. 8 is a diagram showing a memory unit with a second embodiment of the second word line arrangement of the present invention.
FIG. 9 is a diagram showing a memory unit with a first embodiment of a third word line arrangement of the present invention.
FIG. 10 is a diagram showing a memory unit with a second embodiment of the third word line arrangement of the present invention.
FIG. 11 is a diagram showing a memory device of the present invention with the third word line arrangement and the first bit line arrangement.
FIG. 12 is a diagram showing a portion of the memory device of FIG. 11.
FIG. 13 is a diagram showing a memory device of the present invention with the third word line arrangement and the second bit line arrangement.
FIG. 14 is a diagram showing a portion of the memory device of FIG. 13.
FIG. 15 is a diagram showing a memory unit with a first embodiment of a fourth word line arrangement of the present invention.
FIG. 16 is a diagram showing a memory unit with a second embodiment of the fourth word line arrangement of the present invention.
FIG. 17 is a diagram showing a memory device of the present invention with the fourth word line arrangement and the first bit line arrangement.
FIG. 18 is a diagram showing a memory device of the present invention with the fourth word line arrangement and the second bit line arrangement.
FIG. 19 is a diagram showing an embodiment of a switch of the memory device of the present invention.
FIGS. 20-22 are diagrams showing examples of the memory device of the present invention configured to operate in a byte enable mode
DETAILED DESCRIPTION
Please refer to FIG. 4 and FIG. 5 together. FIG. 4 is a diagram showing a memory unit 40 with a first word line arrangement of the present invention. FIG. 5 is a diagram showing a memory device 400a of the present invention with the first word line arrangement and the first bit line arrangement. The memory device 400a comprises a plurality memory blocks bk0-bk7 arranged along a first direction A. Each memory block (e.g., bk0) comprises a plurality of memory units arranged along the first direction A. The memory unit in FIG. 5 can be realized by the memory unit 40. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 5. As shown in figures, arrangements of memory cells MC, word lines WL0-WL255, bit lines (bit0_bk0 to bit31_bk7) and multiplexers MUX0-MUX7 of the memory device 400a are similar to those of the memory device 200 of FIG. 2. The memory device 400a further comprises a plurality of column word lines CWL0-CWL7 elongated along the second direction B and a plurality of switches SW. Each of the switches SW has a control terminal coupled to a corresponding column word line CWL0-CWL7, a first terminal coupled to a single memory cell MC, and a second terminal coupled to a corresponding bit line (bit0_bk0 to bit31_bk7). Each of the column word lines CWL0-CWL7 is configured to control on/off states of the switches SW of a corresponding memory block bk0-bk7. For example, the column word line CWL0 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk0, the column word line CWL7 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk7, and so on. As such, each of the column word lines CWL0-CWL7 can control on/off states of all the switches SW of a corresponding memory block bk0-bk7 simultaneously, and the switches SW of different memory blocks bk0-bk7 can be controlled individually.
According to the above arrangement, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC for a read/write operation, the column word lines CWL0-CWL7 can be used to further select the memory cells MC of the specific memory block bk0-bk7 for the read/write operation. For example, when the column word line CWL0 transmits a control signal to the control terminals of the switches SW of the memory block bk0, only the switches SW of the memory block bk0 are turned on to couple the memory cells MC of the memory block bk0 to the corresponding bit lines (bit0_bk0 to bit31_bk0), for allowing the corresponding bit lines (bit0_bk0 to bit31_bk0) to transmit data. On the other hand, other bit lines corresponding to the memory block bk1-bk7 are not driven to transmit data. Therefore, the power consumption of the memory device 400a can be reduced.
In addition, the memory cell MC may correspond to a plurality of bit lines. For example, when the memory cell is a memory cell of SRAM, the memory cell may be selected to couple to two bit lines. Accordingly, two or more column word lines can be arranged to control electrical connections between the memory cell and the two bit lines.
Please refer to FIG. 4 and FIG. 6 together. FIG. 6 is a diagram showing a memory device 500a of the present invention with the first word line arrangement and the second bit line arrangement. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 6. As shown in figures, arrangements of memory cells MC, word lines WL0-WL255, bit lines (bit0_bk0 to bit31_bk7) and multiplexers MUX0-MUX31 of the memory device 500a are similar to those of the memory device 300 of FIG. 3. Although the bit lines (bit0_bk0 to bit31_bk7) of each memory block bk0-bk7 are scattered sequentially, each of the column word lines CWL0-CWL7 is still configured to control on/off states of the switches SW of a corresponding memory block bk0-bk7. For example, the column word line CWL0 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk0, the column word line CWL7 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk7, and so on. As such, each of the column word lines CWL0-CWL7 can control on/off states of all the switches SW of a corresponding memory block bk0-bk7 simultaneously, and the switches SW of different memory blocks bk0-bk7 can be controlled individually.
Similarly, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC for the read/write operation, the column word lines CWL0-CWL7 can be used to further select the memory cells MC of the specific memory block bk0-bk7 for the read/write operation. For example, when the word line CWL0 transmits a control signal to the control terminals of the switches SW of the memory block bk0, only the switches SW of the memory block bk0 are turned on to couple the memory cells MC of the memory block bk0 to the corresponding bit lines (bit0_bk0 to bit31_bk0), for allowing the corresponding bit lines (bit0_bk0 to bit31_bk0) to transmit data. On the other hand, other bit lines corresponding to the memory block bk1-bk7 are not driven to transmit data. Therefore, the power consumption of the memory device 500a can be reduced.
Note that, in the memory device 500a in FIG. 6, the memory units receiving the bit lines (e.g., bit0_bk0-bit31_bk0) may form a memory block (e.g., bk0, not shown in FIG. 6). That is, the memory units within the memory block (e.g., bk0, not shown in FIG. 6) may be disposed in a distributed/interleaved manner. In other words, in FIG. 6, the memory units within the memory block bk0 (not shown in FIG. 6), which are the memory units receiving the bit lines bit0_bk0-bit31_bk0, and the memory units within the memory block bk1 (not shown in FIG. 6), which are the memory units receiving the bit lines bit0_bk1-bit31_bk1, are disposed in an interleaved manner.
Please refer to FIG. 7. FIG. 7 is a diagram showing a memory unit 70 with a first embodiment of a second word line arrangement of the present invention. The memory unit 70 comprises the word lines WL0-WL255 elongated along the first direction A, a plurality of memory cell groups MCG arranged along a second direction B, a bit line BL elongated along the second direction B, a plurality of local bit lines LBL elongated along the second direction B, and a column word line CWL elongated along the second direction B, and a plurality of column switches SW1 arranged along the second direction B. Each of the memory cell groups MCG comprising a plurality of memory cells MC. Each column switch SW1, controlled by the column word line (signal) CWL, connects the bit line BL and one of the local bit lines LBL, so as to control conduction between the bit line BL and the corresponding local bit line LBL. Note that, in the present application, column/row word line and column/row word line signal are used interchangeably.
As shown in FIG. 7, a column of the memory cells MC are divided into a predetermined number (such as 32) of memory cell groups, and each of the 32 memory cell groups comprises 8 memory cells. The switch SW is coupled between one of the 32 memory cell groups and a corresponding bit line. The column word line is configured to turn on/off 32 switches SW of each column of the memory cells MC of a corresponding memory block simultaneously.
The second word line arrangement of FIG. 7 is applicable to the memory device 400a of FIG. 5 and the memory device 500a of FIG. 6. For example, the column word line CWL0 is coupled to the control terminals of the 32 olumn switches SW1 of each column of the memory cells MC of the memory block bk0, the column word line CWL7 is coupled to the control terminals of the 32 column switches SW1 of each column of the memory cells MC of the memory block bk7, and so on. As such, each of the column word lines CWL0-CWL7 can control on/off states of all the column switches SW1 of a corresponding memory block bk0-bk7 simultaneously.
In other words, the memory unit 70 may be applied to the memory unit within the memory device 400a of FIG. 5. In FIG. 5, the plurality memory blocks bk0-bk7 receives the column word line signals CWL0-CWL7, respectively. The column switches SW1 within a first memory block (e.g., bk0) are controlled by a first column word line signal (e.g., CWL0) among the plurality of column word line signals (CWL0-CWL7).
Please refer to FIG. 8. FIG. 8 is a diagram showing a memory unit 80 with a second embodiment of the second word line arrangement of the present invention. Different from the embodiment of FIG. 7, the memory cells MC of each memory cell group of FIG. 8 are coupled in series (such as memory cells of a flash memory device). The column word line is configured to turn on/off 32 switches SW of each column of the memory cells MC of a corresponding memory block simultaneously. Similarly, the second word line arrangement of FIG. 8 is also applicable to the memory device 400a of FIG. 5 and the memory device 500a of FIG. 6.
In the embodiments of FIG. 7 and FIG. 8, each of the memory cell group comprises 8 memory cells, but the present invention is not limited to it. In other embodiments of the present invention, each of the memory cell group can comprises other number of memory cells according to design requirements.
Comparing with the first word line arrangement of FIG. 4, the second word line arrangements of FIG. 7 and FIG. 8 comprise fewer switches, in order to reduce overall area of the memory devices.
Please refer to FIG. 9 and FIGS. 11-12 together. FIG. 9 is a diagram showing a memory unit 90 with a first embodiment of a third word line arrangement of the present invention. FIG. 11 is a diagram showing a memory device 400b of the present invention with the third word line arrangement and the first bit line arrangement. FIG. 12 is a diagram showing a portion of the memory device 400b of FIG. 11. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 11, and word lines are omitted in FIGS. 11 and 12. As shown in figures, a column of the memory cells MC are divided into a predetermined number (such as 32) of memory cell groups, and each of the 32 memory cell groups comprises 8 memory cells. The switch SW is coupled between one of the 32 memory cell groups and a corresponding bit line. The memory device 400b comprises a plurality of row word lines (RWL0_bk0 to RWL31_bk7) elongated along the first direction A, and each of the row word lines (RWL0_bk0 to RWL31_bk7) is configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block. For example, the row word line RWL0_bk0 is coupled to the control terminal of the switch SW corresponding to the first memory cell group of each column of the memory block bk0, the row word line RWL31_bk0 is coupled to the control terminal of the switch SW corresponding to the 32th memory cell group of each column of the memory block bk0, and so on. As such, the row word lines (RWL0_bk0 to RWL31_bk7) can further select a specific memory cell group of each column of the memory cells MC of a corresponding memory block bk0-bk7 for transmitting data.
Please refer to FIG. 9 and FIGS. 13-14 together. FIG. 13 is a diagram showing a memory device 500b of the present invention with the third word line arrangement and the second bit line arrangement. FIG. 14 is a diagram showing a portion of the memory device 500b of FIG. 13. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 13, and word lines are omitted in FIGS. 13 and 14. Although the bit lines (bit0_bk0 to bit31_bk7) of each memory block bk0-bk7 are scattered sequentially, the row word lines (RWL0_bk0 to RWL31_bk7) in FIGS. 13-14 is still configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block. For example, the row word line RWL0_bk0 is coupled to the control terminal of the switch SW corresponding to the first memory cell group of each column of the memory block bk0, the row word line RWL31_bk0 is coupled to the control terminal of the switch SW corresponding to the 32th memory cell group of each column of the memory block bk0, and so on. As such, the row word lines (RWL0_b0k0 to RWL31_bk7) can further select a specific memory cell group of each column of the memory cells MC of a corresponding memory block bk0-bk7 for transmitting data.
Please refer to FIG. 10. FIG. 10 is a diagram showing a memory unit with a second embodiment of the third word line arrangement of the present invention. Different from the embodiment of FIG. 9, the memory cells MC of each memory cell group of FIG. 10 are coupled in series (such as memory cells of a flash memory device). The row word line is configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block. Similarly, the third word line arrangement of FIG. 10 is also applicable to the memory device 400b of FIG. 11 and the memory device 500b of FIG. 13.
Comparing with the first word line arrangement and the second word line arrangement, the third word line arrangement only turns on one switch SW of each column of the memory cells MC for transmitting data. Thus the third word line arrangement can further reduce power consumption of the memory device. However, a number of the row word lines (RWL0_bk0 to RWL31_bk7) is a multiple of a number of the column word lines CWL0-CWL7. The third word line arrangement may need to form the plurality of row word lines in different metal layers, but the first word line arrangement and the second word line arrangement can form the plurality of column word lines in a same metal layer. For example, when each of the memory cell group comprises four memory cells, and the memory device comprises 32 memory blocks, there are totally 32 row word lines need to be arranged within a layout area of the four memory cells for passing through. Thus the 32 row word lines must be form in different metal layers. As to the first word line arrangement and the second word line arrangement, only one column word line needs to be arranged within the layout area of the memory cells. Thus the column word lines can be formed in a same metal layer.
Please refer to FIG. 15. FIG. 15 is a diagram showing a memory unit F0 according to an embodiment of the present invention. The memory unit F0 is similar to the memory unit 70. The memory unit F0 comprises the word lines WL0-WL255 elongated along the first direction A, the plurality of memory cell groups MCG arranged along the second direction B, the bit line BL elongated along the second direction B, a plurality of local bit lines LBL elongated along the second direction B, and a column word line CWL elongated along the second direction B, the plurality of column switches SW1 arranged along the second direction B, a plurality of row word lines RWL0-RWL31 elongated along the first direction A, and a plurality of row switches SW2 arranged along the second direction B. Between the bit line BL and one of the local bit lines LBL, one column switch SW1 and one row switch SW2 are electrically coupled in series. The rest feature of the memory unit F0 may be referred to the paragraph stated in the above, which is not narrated herein for brevity.
Please refer to FIG. 15 and FIG. 17 together. FIG. 15 is a diagram showing a memory unit F0 with a first embodiment of a fourth word line arrangement of the present invention. FIG. 17 is a diagram showing a memory device 400c of the present invention with the fourth word line arrangement and the first bit line arrangement. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit, and word lines are omitted in FIG. 17. As shown in figures, the memory device 400c comprises a plurality of column switches SW1 and a plurality of row switches SW2. The column switch SW1 is controlled by the corresponding column word line CWL0-CWL7. The row switch SW2 is controlled by the corresponding row word line (RWL0_bk0 to RWL31_bk7). The column switch SW1 of FIG. 15 operates similarly to the switch SW of FIG. 7, and the row switch SW2 operates similarly to the switch SW of FIG. 9. The electrical connection of the row word lines (RWL0_bk0 to RWL31_bk7) of FIG. 17 is similar to that of FIG. 12. The column switch SW1 and the row switch SW2 are coupled between one of the memory cell groups and a corresponding bit line in series (bit0_bk0 to bit31_bk7). The memory cells MC can be selected by the corresponding word line, column word line CWL0-CWL7, row word line (RWL0_bk0 to RWL31_bk7).
According to the above arrangement, the memory device 400c can also reduce power consumption. Moreover, the memory device 400c can operate in two modes. For example, when the column word lines are configured to turn on all the column switches SW1 in default, the memory device 400c can operate similarly to the memory device 400b; and when branches of column word lines, which extend to the memory units, of each memory block are further grouped into four groups to respectively control eight columns of memory cells to work individually, the memory device 400c can operate in a byte enable mode for outputting data in byte format.
When the third word line arrangement in FIG. 11 is further configured to operate in a byte enable mode, the number of the row word line of a memory block needs to be multiplied by four for respectively controlling eight columns of memory cells to work individually. For example, as shown in FIG. 20, each of four row word lines (RWL0_bk0_byte0 to RWL0_bk0_byte3) of the memory block bk0 is arranged to control eight columns of memory cells of the first memory cell groups to work individually. In other words, there are totally 32 row word lines need to be arranged within a layout area of the eight memory cells of a memory cell group for passing through, where the fourth word line arrangement needs only eight row word lines to be arranged within the layout area of the eight memory cells of a memory cell group for passing through. Thus the third word line arrangement must form the 32 row word lines in different metal layers, but the fourth word line arrangement can form the eight row word lines in a same metal layer. For example, as shown in FIG. 21, for controlling the first memory cell groups of the eight memory blocks of the third word line arrangement to operate in the byte enable mode, the row word lines (RWL0_bk0_byte0 to RWL0_bk7_byte3) corresponding to the first memory cell groups of the eight memory blocks are all arranged to pass through each of the first memory cell groups. However, as shown in FIG. 22, branches of column word lines of the memory block bk0 are grouped into four column word lines (CWL0_byte0 to CWL0_byte3) to respectively control eight columns of memory cells to operate in the byte enable mode, and the number of the row word lines (RWL0_bk0 to RWL31_bk7) of the fourth word line arrangement remains the same. As mentioned above, the fourth word line arrangement of the memory device 400c can operate similarly to the third word line arrangement of the memory device 400b, thus the power consumption of the memory device 400c and the memory device 400b are almost the same. Therefore, the fourth word line arrangement has both the advantages of the first/second word line arrangement and the third word line arrangement.
Please refer to FIG. 15 and FIG. 18 together. FIG. 18 is a diagram showing a memory device 500c of the present invention with the fourth word line arrangement and the second bit line arrangement. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit, and word lines are omitted in FIG. 18. The electrical connection of the row word lines (RWL0_bk0 to RWL31_bk7) of FIG. 18 is similar to that of FIG. 14. Although the bit lines (bit0_bk0 to bit31_bk7) of each memory block bk0-bk7 are scattered sequentially, the column word lines CWL0-CWL7, the row word lines (RWL0_bk0 to RWL31_bk7), the column switches SW1 and the row switches SW2 of FIG. 18 still operate similarly to those of FIG. 17. Therefore, no further illustration is provided.
Please refer to FIG. 16. FIG. 16 is a diagram showing a memory unit with a second embodiment of the fourth word line arrangement of the present invention. Different from the embodiment of FIG. 15, the memory cells MC of each memory cell group of FIG. 16 are coupled in series (such as memory cells of a flash memory device). Similarly, the fourth word line arrangement of FIG. 16 is also applicable to the memory device 400c of FIG. 17 and the memory device 500c of FIG. 18.
Please refer to FIG. 19. FIG. 19 is a diagram showing an embodiment of a switch of the memory device of the present invention. As shown in figures, the aforementioned switches SW, SW1, SW2 can be transistors, but the present invention is not limited to it. The switches SW, SW1, SW2 can be other type of switch element for controlling electrical connections between the memory cells and the bit lines.
In the above embodiments, the memory cells MC are arranged into a matrix having 256 rows and 256 columns, the plurality of memory cells are divided into 8 memory blocks bk0-bk7, each of the 8 memory blocks bk0-bk7 comprises 32 columns of the memory cells MC, and each memory cell group comprises 8 memory cells. However, the present invention is not limited to the above embodiment. In other embodiment of the present invention, the numbers of rows and columns of the matrix, the number of the memory blocks in the memory device, the number of columns of the memory cells in the memory block, and the number of the memory cells in the memory cell group can be different from the above numbers and determined according to design requirements.
In contrast to the prior art, the memory device of the present invention comprises the column word lines and/or the row word lines for further selecting specific memory cells to be coupled to corresponding bit lines, such that other bit lines corresponding to the unselected memory cells are not driven to transmit data. Therefore, the memory device of the present invention has lower power consumption.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Patent Application
20200194046
