Claims
- 1. A method of forming a titanium suicide layer on a silicon substrate of a semiconductor device, comprising:disposing a titanium alloy layer over the silicon substrate wherein said titanium alloy comprises from 1 to 20 atomic percent refractory metal; and heating said titanium alloy to a temperature of less than about 700° C. sufficient to substantially form C54 phase titanium silicide.
- 2. The method of claim 1 wherein said substrate is heated to a temperature sufficient to completely transform said titanium alloy layer to C54 phase titanium silicide.
- 3. The method of claim 1 wherein said refractory metal comprises one or more elements of the group consisting of Ta, Nb, W, V and Cr.
- 4. The method of claim 1 wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal.
- 5. The method of claim 4 wherein said refractory metal comprises a refractory metal selected from the group consisting of Ta and Nb.
- 6. The method of claim 1 wherein said titanium alloy comprises titanium, silicon and a refractory metal.
- 7. The method of claim 1 wherein said titanium alloy layer is disposed 10 to 60 nm thick over said silicon substrate.
- 8. The method of claim 1 wherein said silicon substrate is selected from the group consisting of monocrystalline silicon, polycrystalline silicon, amorphous silicon, and a silicon germanium alloy.
- 9. The method of claim 1 wherein said silicon substrate is selected from the group of silicon on insulator containing N-type dopant and silicon on insulator containing P-type dopant.
- 10. The method of claim 1 wherein said titanium alloy is deposited over said silicon substrate by physical vapor deposition.
- 11. The method of claim 1 wherein said titanium alloy is deposited over said silicon substrate by chemical vapor deposition.
- 12. The method of claim 1 wherein said titanium alloy comprises 1 to about 5 atomic percent Mo.
- 13. A method of forming a titanium silicide layer in a semiconductor device, comprising:depositing a 10 to 200 nm titanium alloy layer over a semiconductor device, wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal and said semiconductor device incorporates a plurality of electronic components having exposed silicon surfaces; heating said titanium alloy layer to a temperature sufficient to substantially form C54 phase titanium silicide in the titanium alloy layer overlying said silicon surfaces, said temperature being less than about 700° C.; and etching unreacted portions of said titanium alloy layer.
- 14. A method of forming a titanium silicide layer in a semiconductor device, comprising:depositing a 10 to 200 nm titanium alloy layer over a semiconductor device, wherein said titanium alloy comprises from 1 to 15 atomic percent refractory metal and said semiconductor device incorporates a plurality of electronic components having exposed silicon surfaces; heating said titanium alloy layer sufficient to form titanium silicide m the titanium alloy overlying said silicon surfaces; etching unreacted portions of said titanium alloy; and heating said titanium silicide to a temperature sufficient to substantially form C54 phase titanium silicide, said temperature being less than about 700° C.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a division of application Ser. No. 08/586,046 filed Jan. 16, 1996 which application is now U.S. Pat. No. 5,828,131. This application is a continuation-in-part of U.S. patent application Ser. No. 08/145,921 filed Oct. 29, 1993 now U.S. Pat. No. 5,510,295.
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Non-Patent Literature Citations (2)
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Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
08/145921 |
Oct 1993 |
US |
Child |
08/586046 |
|
US |