Claims
- 1. The process for forming a trench type MOSgated device; said process comprising the steps of etching a trench having spaced side walls and a bottom surface into a silicon wafer wherein said bottom surface and side walls meet at a sharp angle; forming a silicon nitride layer on said side walls and said bottom surface; removing said silicon nitride layer from said bottom surface only; forming silicon dioxide layer on said trench bottom which has a thickness in excess of 1000 Å on said bottom surface and rounding said bottom surface and sharp corners while forming said bottom silicon dioxide layer, and thereafter removing the silicon nitride layer on said walls and then forming silicon dioxide layers on said side walls which have a thickness substantially less than 1000 Å.
- 2. The process of claim 1 wherein said silicon dioxide layers on said walls have a thickness of about 320 Å.
- 3. The process for forming a trench type MOSgated device; said process comprising the steps of etching a trench having spaced side walls and a bottom surface into a monocrystalline silicon wafer; amorphizing the bottom surface of the trench but not its side walls; and thereafter growing a silicon dioxide layer on the side walls and bottom of the trench, wherein the silicon dioxide layer will be substantially thicker at the bottom of said trench than on the side walls.
- 4. The process of claim 3, wherein the silicon oxide coating on said walls have a thickness of greater than about 1000 Å.
- 5. The process of claim 3, wherein the step of amorphizing the silicon at the bottom of said trench is carried out by an ion implant of a neutral species into the bottom of said trench.
- 6. The process of claim 5, wherein said ion implant is at a heavy dose of greater than about 1E16 atoms/cm2.
- 7. The process of claim 6, wherein the silicon oxide coating on said walls have a thickness of greater than about 1000 Å.
RELATED APPLICATIONS
[0001] This application is a divisional of U.S. application Ser. No. 09/814,081, filed Mar. 21, 2001 entitled Low Voltage Power MOSFET Device and Process for its Manufacture which claims priority to Provisional Application Serial No. 60/194,386 filed Apr. 4, 2000 in the name of Naresh Thapar.
Provisional Applications (1)
|
Number |
Date |
Country |
|
60194386 |
Apr 2000 |
US |
Divisions (1)
|
Number |
Date |
Country |
Parent |
09814081 |
Mar 2001 |
US |
Child |
10421024 |
Apr 2003 |
US |